xref: /linux/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include <dt-bindings/gpio/gpio.h>
7#include "mpfs.dtsi"
8#include "mpfs-beaglev-fire-fabric.dtsi"
9
10/* Clock frequency (in Hz) of MTIMER */
11#define MTIMER_FREQ		1000000
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16	model = "BeagleBoard BeagleV-Fire";
17	compatible = "beagle,beaglev-fire", "microchip,mpfs";
18
19	aliases {
20		serial0 = &mmuart0;
21		serial1 = &mmuart1;
22		serial2 = &mmuart2;
23		serial3 = &mmuart3;
24		serial4 = &mmuart4;
25	};
26
27	chosen {
28		stdout-path = "serial0:115200n8";
29	};
30
31	cpus {
32		timebase-frequency = <MTIMER_FREQ>;
33	};
34
35	ddrc_cache_lo: memory@80000000 {
36		device_type = "memory";
37		reg = <0x0 0x80000000 0x0 0x40000000>;
38		status = "okay";
39	};
40
41	reserved-memory {
42		#address-cells = <2>;
43		#size-cells = <2>;
44		ranges;
45
46		hss: hss-buffer@103fc00000 {
47			compatible = "shared-dma-pool";
48			reg = <0x10 0x3fc00000 0x0 0x400000>;
49			no-map;
50		};
51	};
52
53	imx219_clk: camera-clk {
54		compatible = "fixed-clock";
55		#clock-cells = <0>;
56		clock-frequency = <24000000>;
57	};
58
59	imx219_vana: fixedregulator-0 {
60		compatible = "regulator-fixed";
61		regulator-name = "imx219_vana";
62		regulator-min-microvolt = <2800000>;
63		regulator-max-microvolt = <2800000>;
64	};
65
66	imx219_vdig: fixedregulator-1 {
67		compatible = "regulator-fixed";
68		regulator-name = "imx219_vdig";
69		regulator-min-microvolt = <1800000>;
70		regulator-max-microvolt = <1800000>;
71	};
72
73	imx219_vddl: fixedregulator-2 {
74		compatible = "regulator-fixed";
75		regulator-name = "imx219_vddl";
76		regulator-min-microvolt = <1200000>;
77		regulator-max-microvolt = <1200000>;
78	};
79
80};
81
82&gpio0 {
83	interrupts = <13>, <14>, <15>, <16>,
84		     <17>, <18>, <19>, <20>,
85		     <21>, <22>, <23>, <24>,
86		     <25>, <26>;
87	ngpios = <14>;
88	status = "okay";
89};
90
91&gpio1 {
92	interrupts = <27>, <28>, <29>, <30>,
93		     <31>, <32>, <33>, <34>,
94		     <35>, <36>, <37>, <38>,
95		     <39>, <40>, <41>, <42>,
96		     <43>, <44>, <45>, <46>,
97		     <47>, <48>, <49>, <50>;
98	ngpios = <24>;
99	status = "okay";
100};
101
102&gpio2 {
103	interrupts = <53>, <53>, <53>, <53>,
104		     <53>, <53>, <53>, <53>,
105		     <53>, <53>, <53>, <53>,
106		     <53>, <53>, <53>, <53>,
107		     <53>, <53>, <53>, <53>,
108		     <53>, <53>, <53>, <53>,
109		     <53>, <53>, <53>, <53>,
110		     <53>, <53>, <53>, <53>;
111	ngpios = <32>;
112	gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
113			  "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
114			  "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
115			  "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
116			  "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20",
117			  "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26",
118			  "P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1",
119			  "M2_W_DISABLE2", "VIO_ENABLE", "SD_DET";
120	status = "okay";
121
122	vio-enable-hog {
123		gpio-hog;
124		gpios = <30 30>;
125		output-high;
126		line-name = "VIO_ENABLE";
127	};
128
129	sd-det-hog {
130		gpio-hog;
131		gpios = <31 31>;
132		input;
133		line-name = "SD_DET";
134	};
135};
136
137&i2c0 {
138	status = "okay";
139};
140
141&i2c1 {
142	status = "okay";
143
144	eeprom: eeprom@50 {
145		compatible = "atmel,24c32";
146		reg = <0x50>;
147	};
148
149	imx219: sensor@10 {
150		compatible = "sony,imx219";
151		reg = <0x10>;
152		clocks = <&imx219_clk>;
153		VANA-supply = <&imx219_vana>;   /* 2.8v */
154		VDIG-supply = <&imx219_vdig>;   /* 1.8v */
155		VDDL-supply = <&imx219_vddl>;   /* 1.2v */
156
157		port {
158			imx219_0: endpoint {
159				data-lanes = <1 2>;
160				clock-noncontinuous;
161				link-frequencies = /bits/ 64 <456000000>;
162			};
163		};
164	};
165};
166
167&irqmux {
168	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
169			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
170			<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
171			<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
172			<12 &plic 25>, <13 &plic 26>,
173
174			<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
175			<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
176			<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
177			<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
178			<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
179			<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
180			<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
181			<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
182
183			<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
184			<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
185			<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
186			<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
187			<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
188			<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
189			<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
190			<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
191			<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
192			<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
193			<94 &plic 53>, <95 &plic 53>;
194};
195
196&mac0 {
197	status = "okay";
198	phy-mode = "sgmii";
199	phy-handle = <&phy0>;
200	phy0: ethernet-phy@0 {
201		reg = <0>;
202	};
203};
204
205&mbox {
206	status = "okay";
207};
208
209&mmc {
210	bus-width = <4>;
211	disable-wp;
212	cap-sd-highspeed;
213	cap-mmc-highspeed;
214	mmc-ddr-1_8v;
215	mmc-hs200-1_8v;
216	sd-uhs-sdr12;
217	sd-uhs-sdr25;
218	sd-uhs-sdr50;
219	sd-uhs-sdr104;
220	status = "okay";
221};
222
223&mmuart0 {
224	status = "okay";
225};
226
227&mmuart1 {
228	status = "okay";
229};
230
231&refclk {
232	clock-frequency = <125000000>;
233};
234
235&refclk_ccc {
236	clock-frequency = <50000000>;
237};
238
239&rtc {
240	status = "okay";
241};
242
243&spi0 {
244	status = "okay";
245};
246
247&spi1 {
248	status = "okay";
249};
250
251&qspi {
252	status = "okay";
253	cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>, <&gpio0 12 GPIO_ACTIVE_LOW>;
254	num-cs = <2>;
255
256	adc@0 {
257		compatible = "microchip,mcp3464r";
258		reg = <0>; /* CE0 */
259		spi-cpol;
260		spi-cpha;
261		spi-max-frequency = <5000000>;
262		microchip,hw-device-address = <1>;
263		#address-cells = <1>;
264		#size-cells = <0>;
265		status = "okay";
266
267		channel@0 {
268			/* CH0 to AGND */
269			reg = <0>;
270			label = "CH0";
271		};
272
273		channel@1 {
274			/* CH1 to AGND */
275			reg = <1>;
276			label = "CH1";
277		};
278
279		channel@2 {
280			/* CH2 to AGND */
281			reg = <2>;
282			label = "CH2";
283		};
284
285		channel@3 {
286			/* CH3 to AGND */
287			reg = <3>;
288			label = "CH3";
289		};
290
291		channel@4 {
292			/* CH4 to AGND */
293			reg = <4>;
294			label = "CH4";
295		};
296
297		channel@5 {
298			/* CH5 to AGND */
299			reg = <5>;
300			label = "CH5";
301		};
302
303		channel@6 {
304			/* CH6 to AGND */
305			reg = <6>;
306			label = "CH6";
307		};
308
309		channel@7 {
310			/* CH7 is connected to AGND */
311			reg = <7>;
312			label = "CH7";
313		};
314	};
315
316	mmc@1 {
317		compatible = "mmc-spi-slot";
318		reg = <1>;
319		gpios = <&gpio2 31 1>;
320		voltage-ranges = <3300 3300>;
321		spi-max-frequency = <5000000>;
322		disable-wp;
323	};
324};
325
326
327&syscontroller {
328	microchip,bitstream-flash = <&sys_ctrl_flash>;
329	status = "okay";
330};
331
332&syscontroller_qspi {
333	status = "okay";
334
335	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
336		compatible = "jedec,spi-nor";
337		#address-cells = <1>;
338		#size-cells = <1>;
339		spi-max-frequency = <20000000>;
340		spi-rx-bus-width = <1>;
341		reg = <0>;
342	};
343};
344
345&usb {
346	status = "okay";
347	dr_mode = "otg";
348};
349