1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include <dt-bindings/clock/sun6i-rtc.h> 5#include <dt-bindings/clock/sun8i-de2.h> 6#include <dt-bindings/clock/sun8i-tcon-top.h> 7#include <dt-bindings/clock/sun20i-d1-ccu.h> 8#include <dt-bindings/clock/sun20i-d1-r-ccu.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/reset/sun8i-de2.h> 11#include <dt-bindings/reset/sun20i-d1-ccu.h> 12#include <dt-bindings/reset/sun20i-d1-r-ccu.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 dcxo: dcxo-clk { 19 compatible = "fixed-clock"; 20 clock-output-names = "dcxo"; 21 #clock-cells = <0>; 22 }; 23 24 de: display-engine { 25 compatible = "allwinner,sun20i-d1-display-engine"; 26 allwinner,pipelines = <&mixer0>, <&mixer1>; 27 status = "disabled"; 28 }; 29 30 soc { 31 compatible = "simple-bus"; 32 ranges; 33 dma-noncoherent; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 pio: pinctrl@2000000 { 38 compatible = "allwinner,sun20i-d1-pinctrl"; 39 reg = <0x2000000 0x800>; 40 interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, 41 <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, 42 <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, 43 <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, 44 <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, 45 <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&ccu CLK_APB0>, 47 <&dcxo>, 48 <&rtc CLK_OSC32K>; 49 clock-names = "apb", "hosc", "losc"; 50 gpio-controller; 51 interrupt-controller; 52 #gpio-cells = <3>; 53 #interrupt-cells = <3>; 54 55 /omit-if-no-ref/ 56 can0_pins: can0-pins { 57 pins = "PB2", "PB3"; 58 function = "can0"; 59 }; 60 61 /omit-if-no-ref/ 62 can1_pins: can1-pins { 63 pins = "PB4", "PB5"; 64 function = "can1"; 65 }; 66 67 /omit-if-no-ref/ 68 clk_pg11_pin: clk-pg11-pin { 69 pins = "PG11"; 70 function = "clk"; 71 }; 72 73 /omit-if-no-ref/ 74 dsi_4lane_pins: dsi-4lane-pins { 75 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 76 "PD6", "PD7", "PD8", "PD9"; 77 drive-strength = <30>; 78 function = "dsi"; 79 }; 80 81 /omit-if-no-ref/ 82 i2c2_pd_pins: i2c2-pd-pins { 83 pins = "PD20", "PD21"; 84 function = "i2c2"; 85 }; 86 87 /omit-if-no-ref/ 88 i2c3_pg_pins: i2c3-pg-pins { 89 pins = "PG10", "PG11"; 90 function = "i2c3"; 91 }; 92 93 /omit-if-no-ref/ 94 i2s1_pins: i2s1-pins { 95 pins = "PG12", "PG13"; 96 function = "i2s1"; 97 }; 98 99 /omit-if-no-ref/ 100 i2s1_din0_pin: i2s1-din0-pin { 101 pins = "PG14"; 102 function = "i2s1_din"; 103 }; 104 105 /omit-if-no-ref/ 106 i2s1_dout0_pin: i2s1-dout0-pin { 107 pins = "PG15"; 108 function = "i2s1_dout"; 109 }; 110 111 /omit-if-no-ref/ 112 lcd_rgb666_pins: lcd-rgb666-pins { 113 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 114 "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", 115 "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", 116 "PD18", "PD19", "PD20", "PD21"; 117 function = "lcd0"; 118 }; 119 120 /omit-if-no-ref/ 121 mmc0_pins: mmc0-pins { 122 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 123 function = "mmc0"; 124 }; 125 126 /omit-if-no-ref/ 127 mmc1_pins: mmc1-pins { 128 pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; 129 function = "mmc1"; 130 }; 131 132 /omit-if-no-ref/ 133 mmc2_pins: mmc2-pins { 134 pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; 135 function = "mmc2"; 136 }; 137 138 /omit-if-no-ref/ 139 rgmii_pe_pins: rgmii-pe-pins { 140 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 141 "PE5", "PE6", "PE7", "PE8", "PE9", 142 "PE11", "PE12", "PE13", "PE14", "PE15"; 143 function = "emac"; 144 }; 145 146 /omit-if-no-ref/ 147 rmii_pe_pins: rmii-pe-pins { 148 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 149 "PE5", "PE6", "PE7", "PE8", "PE9"; 150 function = "emac"; 151 }; 152 153 /omit-if-no-ref/ 154 spi0_pins: spi0-pins { 155 pins = "PC2", "PC3", "PC4", "PC5"; 156 function = "spi0"; 157 }; 158 159 /omit-if-no-ref/ 160 spi1_pins: spi1-pins { 161 pins = "PD10", "PD11", "PD12", "PD13"; 162 function = "spi1"; 163 }; 164 165 /omit-if-no-ref/ 166 spi1_hold_pin: spi1-hold-pin { 167 pins = "PD14"; 168 function = "spi1"; 169 }; 170 171 /omit-if-no-ref/ 172 spi1_wp_pin: spi1-wp-pin { 173 pins = "PD15"; 174 function = "spi1"; 175 }; 176 177 /omit-if-no-ref/ 178 uart1_pg6_pins: uart1-pg6-pins { 179 pins = "PG6", "PG7"; 180 function = "uart1"; 181 }; 182 183 /omit-if-no-ref/ 184 uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { 185 pins = "PG8", "PG9"; 186 function = "uart1"; 187 }; 188 189 /omit-if-no-ref/ 190 uart3_pb_pins: uart3-pb-pins { 191 pins = "PB6", "PB7"; 192 function = "uart3"; 193 }; 194 }; 195 196 ccu: clock-controller@2001000 { 197 compatible = "allwinner,sun20i-d1-ccu"; 198 reg = <0x2001000 0x1000>; 199 clocks = <&dcxo>, 200 <&rtc CLK_OSC32K>, 201 <&rtc CLK_IOSC>; 202 clock-names = "hosc", "losc", "iosc"; 203 #clock-cells = <1>; 204 #reset-cells = <1>; 205 }; 206 207 gpadc: adc@2009000 { 208 compatible = "allwinner,sun20i-d1-gpadc"; 209 reg = <0x2009000 0x400>; 210 clocks = <&ccu CLK_BUS_GPADC>; 211 resets = <&ccu RST_BUS_GPADC>; 212 interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>; 213 status = "disabled"; 214 #io-channel-cells = <1>; 215 }; 216 217 dmic: dmic@2031000 { 218 compatible = "allwinner,sun20i-d1-dmic", 219 "allwinner,sun50i-h6-dmic"; 220 reg = <0x2031000 0x400>; 221 interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&ccu CLK_BUS_DMIC>, 223 <&ccu CLK_DMIC>; 224 clock-names = "bus", "mod"; 225 resets = <&ccu RST_BUS_DMIC>; 226 dmas = <&dma 8>; 227 dma-names = "rx"; 228 status = "disabled"; 229 #sound-dai-cells = <0>; 230 }; 231 232 i2s1: i2s@2033000 { 233 compatible = "allwinner,sun20i-d1-i2s", 234 "allwinner,sun50i-r329-i2s"; 235 reg = <0x2033000 0x1000>; 236 interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&ccu CLK_BUS_I2S1>, 238 <&ccu CLK_I2S1>; 239 clock-names = "apb", "mod"; 240 resets = <&ccu RST_BUS_I2S1>; 241 dmas = <&dma 4>, <&dma 4>; 242 dma-names = "rx", "tx"; 243 status = "disabled"; 244 #sound-dai-cells = <0>; 245 }; 246 247 i2s2: i2s@2034000 { 248 compatible = "allwinner,sun20i-d1-i2s", 249 "allwinner,sun50i-r329-i2s"; 250 reg = <0x2034000 0x1000>; 251 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&ccu CLK_BUS_I2S2>, 253 <&ccu CLK_I2S2>; 254 clock-names = "apb", "mod"; 255 resets = <&ccu RST_BUS_I2S2>; 256 dmas = <&dma 5>, <&dma 5>; 257 dma-names = "rx", "tx"; 258 status = "disabled"; 259 #sound-dai-cells = <0>; 260 }; 261 262 timer: timer@2050000 { 263 compatible = "allwinner,sun20i-d1-timer", 264 "allwinner,sun8i-a23-timer"; 265 reg = <0x2050000 0xa0>; 266 interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, 267 <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&dcxo>; 269 }; 270 271 wdt: watchdog@20500a0 { 272 compatible = "allwinner,sun20i-d1-wdt-reset", 273 "allwinner,sun20i-d1-wdt"; 274 reg = <0x20500a0 0x20>; 275 interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 277 clock-names = "hosc", "losc"; 278 status = "reserved"; 279 }; 280 281 uart0: serial@2500000 { 282 compatible = "snps,dw-apb-uart"; 283 reg = <0x2500000 0x400>; 284 reg-io-width = <4>; 285 reg-shift = <2>; 286 interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&ccu CLK_BUS_UART0>; 288 resets = <&ccu RST_BUS_UART0>; 289 dmas = <&dma 14>, <&dma 14>; 290 dma-names = "tx", "rx"; 291 status = "disabled"; 292 }; 293 294 uart1: serial@2500400 { 295 compatible = "snps,dw-apb-uart"; 296 reg = <0x2500400 0x400>; 297 reg-io-width = <4>; 298 reg-shift = <2>; 299 interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&ccu CLK_BUS_UART1>; 301 resets = <&ccu RST_BUS_UART1>; 302 dmas = <&dma 15>, <&dma 15>; 303 dma-names = "tx", "rx"; 304 status = "disabled"; 305 }; 306 307 uart2: serial@2500800 { 308 compatible = "snps,dw-apb-uart"; 309 reg = <0x2500800 0x400>; 310 reg-io-width = <4>; 311 reg-shift = <2>; 312 interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&ccu CLK_BUS_UART2>; 314 resets = <&ccu RST_BUS_UART2>; 315 dmas = <&dma 16>, <&dma 16>; 316 dma-names = "tx", "rx"; 317 status = "disabled"; 318 }; 319 320 uart3: serial@2500c00 { 321 compatible = "snps,dw-apb-uart"; 322 reg = <0x2500c00 0x400>; 323 reg-io-width = <4>; 324 reg-shift = <2>; 325 interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&ccu CLK_BUS_UART3>; 327 resets = <&ccu RST_BUS_UART3>; 328 dmas = <&dma 17>, <&dma 17>; 329 dma-names = "tx", "rx"; 330 status = "disabled"; 331 }; 332 333 uart4: serial@2501000 { 334 compatible = "snps,dw-apb-uart"; 335 reg = <0x2501000 0x400>; 336 reg-io-width = <4>; 337 reg-shift = <2>; 338 interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&ccu CLK_BUS_UART4>; 340 resets = <&ccu RST_BUS_UART4>; 341 dmas = <&dma 18>, <&dma 18>; 342 dma-names = "tx", "rx"; 343 status = "disabled"; 344 }; 345 346 uart5: serial@2501400 { 347 compatible = "snps,dw-apb-uart"; 348 reg = <0x2501400 0x400>; 349 reg-io-width = <4>; 350 reg-shift = <2>; 351 interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&ccu CLK_BUS_UART5>; 353 resets = <&ccu RST_BUS_UART5>; 354 dmas = <&dma 19>, <&dma 19>; 355 dma-names = "tx", "rx"; 356 status = "disabled"; 357 }; 358 359 i2c0: i2c@2502000 { 360 compatible = "allwinner,sun20i-d1-i2c", 361 "allwinner,sun8i-v536-i2c", 362 "allwinner,sun6i-a31-i2c"; 363 reg = <0x2502000 0x400>; 364 interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&ccu CLK_BUS_I2C0>; 366 resets = <&ccu RST_BUS_I2C0>; 367 dmas = <&dma 43>, <&dma 43>; 368 dma-names = "rx", "tx"; 369 status = "disabled"; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 }; 373 374 i2c1: i2c@2502400 { 375 compatible = "allwinner,sun20i-d1-i2c", 376 "allwinner,sun8i-v536-i2c", 377 "allwinner,sun6i-a31-i2c"; 378 reg = <0x2502400 0x400>; 379 interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&ccu CLK_BUS_I2C1>; 381 resets = <&ccu RST_BUS_I2C1>; 382 dmas = <&dma 44>, <&dma 44>; 383 dma-names = "rx", "tx"; 384 status = "disabled"; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 }; 388 389 i2c2: i2c@2502800 { 390 compatible = "allwinner,sun20i-d1-i2c", 391 "allwinner,sun8i-v536-i2c", 392 "allwinner,sun6i-a31-i2c"; 393 reg = <0x2502800 0x400>; 394 interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&ccu CLK_BUS_I2C2>; 396 resets = <&ccu RST_BUS_I2C2>; 397 dmas = <&dma 45>, <&dma 45>; 398 dma-names = "rx", "tx"; 399 status = "disabled"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 }; 403 404 i2c3: i2c@2502c00 { 405 compatible = "allwinner,sun20i-d1-i2c", 406 "allwinner,sun8i-v536-i2c", 407 "allwinner,sun6i-a31-i2c"; 408 reg = <0x2502c00 0x400>; 409 interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&ccu CLK_BUS_I2C3>; 411 resets = <&ccu RST_BUS_I2C3>; 412 dmas = <&dma 46>, <&dma 46>; 413 dma-names = "rx", "tx"; 414 status = "disabled"; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 }; 418 419 can0: can@2504000 { 420 compatible = "allwinner,sun20i-d1-can"; 421 reg = <0x02504000 0x400>; 422 interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&ccu CLK_BUS_CAN0>; 424 resets = <&ccu RST_BUS_CAN0>; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&can0_pins>; 427 status = "disabled"; 428 }; 429 430 can1: can@2504400 { 431 compatible = "allwinner,sun20i-d1-can"; 432 reg = <0x02504400 0x400>; 433 interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&ccu CLK_BUS_CAN1>; 435 resets = <&ccu RST_BUS_CAN1>; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&can1_pins>; 438 status = "disabled"; 439 }; 440 441 syscon: syscon@3000000 { 442 compatible = "allwinner,sun20i-d1-system-control"; 443 reg = <0x3000000 0x1000>; 444 ranges; 445 #address-cells = <1>; 446 #size-cells = <1>; 447 448 regulators@3000150 { 449 compatible = "allwinner,sun20i-d1-system-ldos"; 450 reg = <0x3000150 0x4>; 451 452 reg_ldoa: ldoa { 453 }; 454 455 reg_ldob: ldob { 456 }; 457 }; 458 }; 459 460 dma: dma-controller@3002000 { 461 compatible = "allwinner,sun20i-d1-dma"; 462 reg = <0x3002000 0x1000>; 463 interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 465 clock-names = "bus", "mbus"; 466 resets = <&ccu RST_BUS_DMA>; 467 dma-channels = <16>; 468 dma-requests = <48>; 469 #dma-cells = <1>; 470 }; 471 472 sid: efuse@3006000 { 473 compatible = "allwinner,sun20i-d1-sid"; 474 reg = <0x3006000 0x1000>; 475 #address-cells = <1>; 476 #size-cells = <1>; 477 }; 478 479 crypto: crypto@3040000 { 480 compatible = "allwinner,sun20i-d1-crypto"; 481 reg = <0x3040000 0x800>; 482 interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&ccu CLK_BUS_CE>, 484 <&ccu CLK_CE>, 485 <&ccu CLK_MBUS_CE>, 486 <&rtc CLK_IOSC>; 487 clock-names = "bus", "mod", "ram", "trng"; 488 resets = <&ccu RST_BUS_CE>; 489 }; 490 491 mbus: dram-controller@3102000 { 492 compatible = "allwinner,sun20i-d1-mbus"; 493 reg = <0x3102000 0x1000>, 494 <0x3103000 0x1000>; 495 reg-names = "mbus", "dram"; 496 interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&ccu CLK_MBUS>, 498 <&ccu CLK_DRAM>, 499 <&ccu CLK_BUS_DRAM>; 500 clock-names = "mbus", "dram", "bus"; 501 dma-ranges = <0 0x40000000 0x80000000>; 502 #address-cells = <1>; 503 #size-cells = <1>; 504 #interconnect-cells = <1>; 505 }; 506 507 mmc0: mmc@4020000 { 508 compatible = "allwinner,sun20i-d1-mmc"; 509 reg = <0x4020000 0x1000>; 510 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 512 clock-names = "ahb", "mmc"; 513 resets = <&ccu RST_BUS_MMC0>; 514 reset-names = "ahb"; 515 cap-sd-highspeed; 516 max-frequency = <150000000>; 517 no-mmc; 518 status = "disabled"; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 }; 522 523 mmc1: mmc@4021000 { 524 compatible = "allwinner,sun20i-d1-mmc"; 525 reg = <0x4021000 0x1000>; 526 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 528 clock-names = "ahb", "mmc"; 529 resets = <&ccu RST_BUS_MMC1>; 530 reset-names = "ahb"; 531 cap-sd-highspeed; 532 max-frequency = <150000000>; 533 no-mmc; 534 status = "disabled"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 }; 538 539 mmc2: mmc@4022000 { 540 compatible = "allwinner,sun20i-d1-emmc", 541 "allwinner,sun50i-a100-emmc"; 542 reg = <0x4022000 0x1000>; 543 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 545 clock-names = "ahb", "mmc"; 546 resets = <&ccu RST_BUS_MMC2>; 547 reset-names = "ahb"; 548 cap-mmc-highspeed; 549 max-frequency = <150000000>; 550 mmc-ddr-1_8v; 551 mmc-ddr-3_3v; 552 no-sd; 553 no-sdio; 554 status = "disabled"; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 }; 558 559 spi0: spi@4025000 { 560 compatible = "allwinner,sun20i-d1-spi", 561 "allwinner,sun50i-r329-spi"; 562 reg = <0x04025000 0x1000>; 563 interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 565 clock-names = "ahb", "mod"; 566 dmas = <&dma 22>, <&dma 22>; 567 dma-names = "rx", "tx"; 568 resets = <&ccu RST_BUS_SPI0>; 569 status = "disabled"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 }; 573 574 spi1: spi@4026000 { 575 compatible = "allwinner,sun20i-d1-spi-dbi", 576 "allwinner,sun50i-r329-spi-dbi", 577 "allwinner,sun50i-r329-spi"; 578 reg = <0x04026000 0x1000>; 579 interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 581 clock-names = "ahb", "mod"; 582 dmas = <&dma 23>, <&dma 23>; 583 dma-names = "rx", "tx"; 584 resets = <&ccu RST_BUS_SPI1>; 585 status = "disabled"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 590 usb_otg: usb@4100000 { 591 compatible = "allwinner,sun20i-d1-musb", 592 "allwinner,sun8i-a33-musb"; 593 reg = <0x4100000 0x400>; 594 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 595 interrupt-names = "mc"; 596 clocks = <&ccu CLK_BUS_OTG>; 597 resets = <&ccu RST_BUS_OTG>; 598 extcon = <&usbphy 0>; 599 phys = <&usbphy 0>; 600 phy-names = "usb"; 601 status = "disabled"; 602 }; 603 604 usbphy: phy@4100400 { 605 compatible = "allwinner,sun20i-d1-usb-phy"; 606 reg = <0x4100400 0x100>, 607 <0x4101800 0x100>, 608 <0x4200800 0x100>; 609 reg-names = "phy_ctrl", 610 "pmu0", 611 "pmu1"; 612 clocks = <&dcxo>, 613 <&dcxo>; 614 clock-names = "usb0_phy", 615 "usb1_phy"; 616 resets = <&ccu RST_USB_PHY0>, 617 <&ccu RST_USB_PHY1>; 618 reset-names = "usb0_reset", 619 "usb1_reset"; 620 status = "disabled"; 621 #phy-cells = <1>; 622 }; 623 624 ehci0: usb@4101000 { 625 compatible = "allwinner,sun20i-d1-ehci", 626 "generic-ehci"; 627 reg = <0x4101000 0x100>; 628 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&ccu CLK_BUS_OHCI0>, 630 <&ccu CLK_BUS_EHCI0>, 631 <&ccu CLK_USB_OHCI0>; 632 resets = <&ccu RST_BUS_OHCI0>, 633 <&ccu RST_BUS_EHCI0>; 634 phys = <&usbphy 0>; 635 phy-names = "usb"; 636 status = "disabled"; 637 }; 638 639 ohci0: usb@4101400 { 640 compatible = "allwinner,sun20i-d1-ohci", 641 "generic-ohci"; 642 reg = <0x4101400 0x100>; 643 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&ccu CLK_BUS_OHCI0>, 645 <&ccu CLK_USB_OHCI0>; 646 resets = <&ccu RST_BUS_OHCI0>; 647 phys = <&usbphy 0>; 648 phy-names = "usb"; 649 status = "disabled"; 650 }; 651 652 ehci1: usb@4200000 { 653 compatible = "allwinner,sun20i-d1-ehci", 654 "generic-ehci"; 655 reg = <0x4200000 0x100>; 656 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&ccu CLK_BUS_OHCI1>, 658 <&ccu CLK_BUS_EHCI1>, 659 <&ccu CLK_USB_OHCI1>; 660 resets = <&ccu RST_BUS_OHCI1>, 661 <&ccu RST_BUS_EHCI1>; 662 phys = <&usbphy 1>; 663 phy-names = "usb"; 664 status = "disabled"; 665 }; 666 667 ohci1: usb@4200400 { 668 compatible = "allwinner,sun20i-d1-ohci", 669 "generic-ohci"; 670 reg = <0x4200400 0x100>; 671 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&ccu CLK_BUS_OHCI1>, 673 <&ccu CLK_USB_OHCI1>; 674 resets = <&ccu RST_BUS_OHCI1>; 675 phys = <&usbphy 1>; 676 phy-names = "usb"; 677 status = "disabled"; 678 }; 679 680 emac: ethernet@4500000 { 681 compatible = "allwinner,sun20i-d1-emac", 682 "allwinner,sun50i-a64-emac"; 683 reg = <0x4500000 0x10000>; 684 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "macirq"; 686 clocks = <&ccu CLK_BUS_EMAC>; 687 clock-names = "stmmaceth"; 688 resets = <&ccu RST_BUS_EMAC>; 689 reset-names = "stmmaceth"; 690 syscon = <&syscon>; 691 status = "disabled"; 692 693 mdio: mdio { 694 compatible = "snps,dwmac-mdio"; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 }; 698 }; 699 700 display_clocks: clock-controller@5000000 { 701 compatible = "allwinner,sun20i-d1-de2-clk", 702 "allwinner,sun50i-h5-de2-clk"; 703 reg = <0x5000000 0x10000>; 704 clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; 705 clock-names = "bus", "mod"; 706 resets = <&ccu RST_BUS_DE>; 707 #clock-cells = <1>; 708 #reset-cells = <1>; 709 }; 710 711 mixer0: mixer@5100000 { 712 compatible = "allwinner,sun20i-d1-de2-mixer-0"; 713 reg = <0x5100000 0x100000>; 714 clocks = <&display_clocks CLK_BUS_MIXER0>, 715 <&display_clocks CLK_MIXER0>; 716 clock-names = "bus", "mod"; 717 resets = <&display_clocks RST_MIXER0>; 718 719 ports { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 723 mixer0_out: port@1 { 724 reg = <1>; 725 726 mixer0_out_tcon_top_mixer0: endpoint { 727 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 728 }; 729 }; 730 }; 731 }; 732 733 mixer1: mixer@5200000 { 734 compatible = "allwinner,sun20i-d1-de2-mixer-1"; 735 reg = <0x5200000 0x100000>; 736 clocks = <&display_clocks CLK_BUS_MIXER1>, 737 <&display_clocks CLK_MIXER1>; 738 clock-names = "bus", "mod"; 739 resets = <&display_clocks RST_MIXER1>; 740 741 ports { 742 #address-cells = <1>; 743 #size-cells = <0>; 744 745 mixer1_out: port@1 { 746 reg = <1>; 747 748 mixer1_out_tcon_top_mixer1: endpoint { 749 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 750 }; 751 }; 752 }; 753 }; 754 755 dsi: dsi@5450000 { 756 compatible = "allwinner,sun20i-d1-mipi-dsi", 757 "allwinner,sun50i-a100-mipi-dsi"; 758 reg = <0x5450000 0x1000>; 759 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&ccu CLK_BUS_MIPI_DSI>, 761 <&tcon_top CLK_TCON_TOP_DSI>; 762 clock-names = "bus", "mod"; 763 resets = <&ccu RST_BUS_MIPI_DSI>; 764 phys = <&dphy>; 765 phy-names = "dphy"; 766 status = "disabled"; 767 768 port { 769 dsi_in_tcon_lcd0: endpoint { 770 remote-endpoint = <&tcon_lcd0_out_dsi>; 771 }; 772 }; 773 }; 774 775 dphy: phy@5451000 { 776 compatible = "allwinner,sun20i-d1-mipi-dphy", 777 "allwinner,sun50i-a100-mipi-dphy"; 778 reg = <0x5451000 0x1000>; 779 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&ccu CLK_BUS_MIPI_DSI>, 781 <&ccu CLK_MIPI_DSI>; 782 clock-names = "bus", "mod"; 783 resets = <&ccu RST_BUS_MIPI_DSI>; 784 #phy-cells = <0>; 785 }; 786 787 tcon_top: tcon-top@5460000 { 788 compatible = "allwinner,sun20i-d1-tcon-top"; 789 reg = <0x5460000 0x1000>; 790 clocks = <&ccu CLK_BUS_DPSS_TOP>, 791 <&ccu CLK_TCON_TV>, 792 <&ccu CLK_TVE>, 793 <&ccu CLK_TCON_LCD0>; 794 clock-names = "bus", "tcon-tv0", "tve0", "dsi"; 795 clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; 796 resets = <&ccu RST_BUS_DPSS_TOP>; 797 #clock-cells = <1>; 798 799 ports { 800 #address-cells = <1>; 801 #size-cells = <0>; 802 803 tcon_top_mixer0_in: port@0 { 804 reg = <0>; 805 806 tcon_top_mixer0_in_mixer0: endpoint { 807 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 808 }; 809 }; 810 811 tcon_top_mixer0_out: port@1 { 812 reg = <1>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 816 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 817 reg = <0>; 818 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; 819 }; 820 821 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 822 reg = <2>; 823 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 824 }; 825 }; 826 827 tcon_top_mixer1_in: port@2 { 828 reg = <2>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 832 tcon_top_mixer1_in_mixer1: endpoint@1 { 833 reg = <1>; 834 remote-endpoint = <&mixer1_out_tcon_top_mixer1>; 835 }; 836 }; 837 838 tcon_top_mixer1_out: port@3 { 839 reg = <3>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 843 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 844 reg = <0>; 845 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; 846 }; 847 848 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 849 reg = <2>; 850 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 851 }; 852 }; 853 854 tcon_top_hdmi_in: port@4 { 855 reg = <4>; 856 857 tcon_top_hdmi_in_tcon_tv0: endpoint { 858 remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; 859 }; 860 }; 861 862 tcon_top_hdmi_out: port@5 { 863 reg = <5>; 864 }; 865 }; 866 }; 867 868 tcon_lcd0: lcd-controller@5461000 { 869 compatible = "allwinner,sun20i-d1-tcon-lcd"; 870 reg = <0x5461000 0x1000>; 871 interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&ccu CLK_BUS_TCON_LCD0>, 873 <&ccu CLK_TCON_LCD0>; 874 clock-names = "ahb", "tcon-ch0"; 875 clock-output-names = "tcon-pixel-clock"; 876 resets = <&ccu RST_BUS_TCON_LCD0>, 877 <&ccu RST_BUS_LVDS0>; 878 reset-names = "lcd", "lvds"; 879 #clock-cells = <0>; 880 881 ports { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 885 tcon_lcd0_in: port@0 { 886 reg = <0>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 890 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { 891 reg = <0>; 892 remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; 893 }; 894 895 tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { 896 reg = <1>; 897 remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; 898 }; 899 }; 900 901 tcon_lcd0_out: port@1 { 902 reg = <1>; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 906 tcon_lcd0_out_dsi: endpoint@1 { 907 reg = <1>; 908 remote-endpoint = <&dsi_in_tcon_lcd0>; 909 }; 910 }; 911 }; 912 }; 913 914 tcon_tv0: lcd-controller@5470000 { 915 compatible = "allwinner,sun20i-d1-tcon-tv"; 916 reg = <0x5470000 0x1000>; 917 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&ccu CLK_BUS_TCON_TV>, 919 <&tcon_top CLK_TCON_TOP_TV0>; 920 clock-names = "ahb", "tcon-ch1"; 921 resets = <&ccu RST_BUS_TCON_TV>; 922 reset-names = "lcd"; 923 924 ports { 925 #address-cells = <1>; 926 #size-cells = <0>; 927 928 tcon_tv0_in: port@0 { 929 reg = <0>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 933 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 934 reg = <0>; 935 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 936 }; 937 938 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 939 reg = <1>; 940 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 941 }; 942 }; 943 944 tcon_tv0_out: port@1 { 945 reg = <1>; 946 947 tcon_tv0_out_tcon_top_hdmi: endpoint { 948 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 949 }; 950 }; 951 }; 952 }; 953 954 ppu: power-controller@7001000 { 955 compatible = "allwinner,sun20i-d1-ppu"; 956 reg = <0x7001000 0x1000>; 957 clocks = <&r_ccu CLK_BUS_R_PPU>; 958 resets = <&r_ccu RST_BUS_R_PPU>; 959 #power-domain-cells = <1>; 960 }; 961 962 r_ccu: clock-controller@7010000 { 963 compatible = "allwinner,sun20i-d1-r-ccu"; 964 reg = <0x7010000 0x400>; 965 clocks = <&dcxo>, 966 <&rtc CLK_OSC32K>, 967 <&rtc CLK_IOSC>, 968 <&ccu CLK_PLL_PERIPH0_DIV3>; 969 clock-names = "hosc", "losc", "iosc", "pll-periph"; 970 #clock-cells = <1>; 971 #reset-cells = <1>; 972 }; 973 974 rtc: rtc@7090000 { 975 compatible = "allwinner,sun20i-d1-rtc", 976 "allwinner,sun50i-r329-rtc"; 977 reg = <0x7090000 0x400>; 978 interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&r_ccu CLK_BUS_R_RTC>, 980 <&dcxo>, 981 <&r_ccu CLK_R_AHB>; 982 clock-names = "bus", "hosc", "ahb"; 983 #clock-cells = <1>; 984 }; 985 }; 986}; 987