1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#define SOC_PERIPHERAL_IRQ(nr) (nr + 16) 5 6#include "sunxi-d1s-t113.dtsi" 7 8/ { 9 cpus { 10 timebase-frequency = <24000000>; 11 #address-cells = <1>; 12 #size-cells = <0>; 13 14 cpu0: cpu@0 { 15 compatible = "thead,c906", "riscv"; 16 device_type = "cpu"; 17 reg = <0>; 18 clocks = <&ccu CLK_RISCV>; 19 d-cache-block-size = <64>; 20 d-cache-sets = <256>; 21 d-cache-size = <32768>; 22 i-cache-block-size = <64>; 23 i-cache-sets = <128>; 24 i-cache-size = <32768>; 25 mmu-type = "riscv,sv39"; 26 operating-points-v2 = <&opp_table_cpu>; 27 riscv,isa = "rv64imafdc"; 28 riscv,isa-base = "rv64i"; 29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 30 "zifencei", "zihpm"; 31 #cooling-cells = <2>; 32 33 cpu0_intc: interrupt-controller { 34 compatible = "riscv,cpu-intc"; 35 interrupt-controller; 36 #interrupt-cells = <1>; 37 }; 38 }; 39 }; 40 41 opp_table_cpu: opp-table-cpu { 42 compatible = "operating-points-v2"; 43 44 opp-408000000 { 45 opp-hz = /bits/ 64 <408000000>; 46 opp-microvolt = <900000 900000 1100000>; 47 }; 48 49 opp-1080000000 { 50 opp-hz = /bits/ 64 <1008000000>; 51 opp-microvolt = <900000 900000 1100000>; 52 }; 53 }; 54 55 soc { 56 interrupt-parent = <&plic>; 57 58 riscv_wdt: watchdog@6011000 { 59 compatible = "allwinner,sun20i-d1-wdt"; 60 reg = <0x6011000 0x20>; 61 interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>; 62 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 63 clock-names = "hosc", "losc"; 64 }; 65 66 plic: interrupt-controller@10000000 { 67 compatible = "allwinner,sun20i-d1-plic", 68 "thead,c900-plic"; 69 reg = <0x10000000 0x4000000>; 70 interrupts-extended = <&cpu0_intc 11>, 71 <&cpu0_intc 9>; 72 interrupt-controller; 73 riscv,ndev = <175>; 74 #address-cells = <0>; 75 #interrupt-cells = <2>; 76 }; 77 }; 78 79 pmu { 80 compatible = "riscv,pmu"; 81 riscv,event-to-mhpmcounters = 82 <0x00003 0x00003 0x00000008>, 83 <0x00004 0x00004 0x00000010>, 84 <0x00005 0x00005 0x00000200>, 85 <0x00006 0x00006 0x00000100>, 86 <0x10000 0x10000 0x00004000>, 87 <0x10001 0x10001 0x00008000>, 88 <0x10002 0x10002 0x00010000>, 89 <0x10003 0x10003 0x00020000>, 90 <0x10019 0x10019 0x00000040>, 91 <0x10021 0x10021 0x00000020>; 92 riscv,event-to-mhpmevent = 93 <0x00003 0x00000000 0x00000001>, 94 <0x00004 0x00000000 0x00000002>, 95 <0x00005 0x00000000 0x00000007>, 96 <0x00006 0x00000000 0x00000006>, 97 <0x10000 0x00000000 0x0000000c>, 98 <0x10001 0x00000000 0x0000000d>, 99 <0x10002 0x00000000 0x0000000e>, 100 <0x10003 0x00000000 0x0000000f>, 101 <0x10019 0x00000000 0x00000004>, 102 <0x10021 0x00000000 0x00000003>; 103 riscv,raw-event-to-mhpmcounters = 104 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, 105 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, 106 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, 107 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, 108 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, 109 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, 110 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, 111 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, 112 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, 113 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, 114 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, 115 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; 116 }; 117}; 118