1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include "sun20i-d1s.dtsi" 5#include "sunxi-d1-t113.dtsi" 6 7/ { 8 soc { 9 lradc: keys@2009800 { 10 compatible = "allwinner,sun20i-d1-lradc", 11 "allwinner,sun50i-r329-lradc"; 12 reg = <0x2009800 0x400>; 13 interrupts = <SOC_PERIPHERAL_IRQ(61) IRQ_TYPE_LEVEL_HIGH>; 14 clocks = <&ccu CLK_BUS_LRADC>; 15 resets = <&ccu RST_BUS_LRADC>; 16 status = "disabled"; 17 }; 18 19 i2s0: i2s@2032000 { 20 compatible = "allwinner,sun20i-d1-i2s", 21 "allwinner,sun50i-r329-i2s"; 22 reg = <0x2032000 0x1000>; 23 interrupts = <SOC_PERIPHERAL_IRQ(26) IRQ_TYPE_LEVEL_HIGH>; 24 clocks = <&ccu CLK_BUS_I2S0>, 25 <&ccu CLK_I2S0>; 26 clock-names = "apb", "mod"; 27 resets = <&ccu RST_BUS_I2S0>; 28 dmas = <&dma 3>, <&dma 3>; 29 dma-names = "rx", "tx"; 30 status = "disabled"; 31 #sound-dai-cells = <0>; 32 }; 33 }; 34}; 35 36&pio { 37 /omit-if-no-ref/ 38 dmic_pb11_d0_pin: dmic-pb11-d0-pin { 39 pins = "PB11"; 40 function = "dmic"; 41 }; 42 43 /omit-if-no-ref/ 44 dmic_pe17_clk_pin: dmic-pe17-clk-pin { 45 pins = "PE17"; 46 function = "dmic"; 47 }; 48 49 /omit-if-no-ref/ 50 i2c0_pb10_pins: i2c0-pb10-pins { 51 pins = "PB10", "PB11"; 52 function = "i2c0"; 53 }; 54 55 /omit-if-no-ref/ 56 i2c2_pb0_pins: i2c2-pb0-pins { 57 pins = "PB0", "PB1"; 58 function = "i2c2"; 59 }; 60 61 /omit-if-no-ref/ 62 uart0_pb8_pins: uart0-pb8-pins { 63 pins = "PB8", "PB9"; 64 function = "uart0"; 65 }; 66}; 67