1menu "CPU errata selection" 2 3config ERRATA_ANDES 4 bool "Andes AX45MP errata" 5 depends on RISCV_ALTERNATIVE && RISCV_SBI 6 help 7 All Andes errata Kconfig depend on this Kconfig. Disabling 8 this Kconfig will disable all Andes errata. Please say "Y" 9 here if your platform uses Andes CPU cores. 10 11 Otherwise, please say "N" here to avoid unnecessary overhead. 12 13config ERRATA_ANDES_CMO 14 bool "Apply Andes cache management errata" 15 depends on ERRATA_ANDES && ARCH_R9A07G043 16 select RISCV_DMA_NONCOHERENT 17 default y 18 help 19 This will apply the cache management errata to handle the 20 non-standard handling on non-coherent operations on Andes cores. 21 22 If you don't know what to do here, say "Y". 23 24config ERRATA_SIFIVE 25 bool "SiFive errata" 26 depends on RISCV_ALTERNATIVE 27 help 28 All SiFive errata Kconfig depend on this Kconfig. Disabling 29 this Kconfig will disable all SiFive errata. Please say "Y" 30 here if your platform uses SiFive CPU cores. 31 32 Otherwise, please say "N" here to avoid unnecessary overhead. 33 34config ERRATA_SIFIVE_CIP_453 35 bool "Apply SiFive errata CIP-453" 36 depends on ERRATA_SIFIVE && 64BIT 37 default y 38 help 39 This will apply the SiFive CIP-453 errata to add sign extension 40 to the $badaddr when exception type is instruction page fault 41 and instruction access fault. 42 43 If you don't know what to do here, say "Y". 44 45config ERRATA_SIFIVE_CIP_1200 46 bool "Apply SiFive errata CIP-1200" 47 depends on ERRATA_SIFIVE && 64BIT 48 default y 49 help 50 This will apply the SiFive CIP-1200 errata to repalce all 51 "sfence.vma addr" with "sfence.vma" to ensure that the addr 52 has been flushed from TLB. 53 54 If you don't know what to do here, say "Y". 55 56config ERRATA_STARFIVE_JH7100 57 bool "StarFive JH7100 support" 58 depends on ARCH_STARFIVE 59 depends on !DMA_DIRECT_REMAP 60 depends on NONPORTABLE 61 select DMA_GLOBAL_POOL 62 select RISCV_DMA_NONCOHERENT 63 select RISCV_NONSTANDARD_CACHE_OPS 64 select SIFIVE_CCACHE 65 default n 66 help 67 The StarFive JH7100 was a test chip for the JH7110 and has 68 caches that are non-coherent with respect to peripheral DMAs. 69 It was designed before the Zicbom extension so needs non-standard 70 cache operations through the SiFive cache controller. 71 72 Say "Y" if you want to support the BeagleV Starlight and/or 73 StarFive VisionFive V1 boards. 74 75config ERRATA_THEAD 76 bool "T-HEAD errata" 77 depends on RISCV_ALTERNATIVE 78 help 79 All T-HEAD errata Kconfig depend on this Kconfig. Disabling 80 this Kconfig will disable all T-HEAD errata. Please say "Y" 81 here if your platform uses T-HEAD CPU cores. 82 83 Otherwise, please say "N" here to avoid unnecessary overhead. 84 85config ERRATA_THEAD_PBMT 86 bool "Apply T-Head memory type errata" 87 depends on ERRATA_THEAD && 64BIT && MMU 88 select RISCV_ALTERNATIVE_EARLY 89 default y 90 help 91 This will apply the memory type errata to handle the non-standard 92 memory type bits in page-table-entries on T-Head SoCs. 93 94 If you don't know what to do here, say "Y". 95 96config ERRATA_THEAD_CMO 97 bool "Apply T-Head cache management errata" 98 depends on ERRATA_THEAD && MMU 99 select DMA_DIRECT_REMAP 100 select RISCV_DMA_NONCOHERENT 101 select RISCV_NONSTANDARD_CACHE_OPS 102 default y 103 help 104 This will apply the cache management errata to handle the 105 non-standard handling on non-coherent operations on T-Head SoCs. 106 107 If you don't know what to do here, say "Y". 108 109config ERRATA_THEAD_PMU 110 bool "Apply T-Head PMU errata" 111 depends on ERRATA_THEAD && RISCV_PMU_SBI 112 default y 113 help 114 The T-Head C9xx cores implement a PMU overflow extension very 115 similar to the core SSCOFPMF extension. 116 117 This will apply the overflow errata to handle the non-standard 118 behaviour via the regular SBI PMU driver and interface. 119 120 If you don't know what to do here, say "Y". 121 122endmenu # "CPU errata selection" 123