1menu "CPU errata selection" 2 3config ERRATA_ANDES 4 bool "Andes AX45MP errata" 5 depends on RISCV_ALTERNATIVE && RISCV_SBI 6 help 7 All Andes errata Kconfig depend on this Kconfig. Disabling 8 this Kconfig will disable all Andes errata. Please say "Y" 9 here if your platform uses Andes CPU cores. 10 11 Otherwise, please say "N" here to avoid unnecessary overhead. 12 13config ERRATA_ANDES_CMO 14 bool "Apply Andes cache management errata" 15 depends on ERRATA_ANDES && ARCH_R9A07G043 16 select RISCV_DMA_NONCOHERENT 17 default y 18 help 19 This will apply the cache management errata to handle the 20 non-standard handling on non-coherent operations on Andes cores. 21 22 If you don't know what to do here, say "Y". 23 24config ERRATA_MIPS 25 bool "MIPS errata" 26 depends on RISCV_ALTERNATIVE 27 help 28 All MIPS errata Kconfig depend on this Kconfig. Disabling 29 this Kconfig will disable all MIPS errata. Please say "Y" 30 here if your platform uses MIPS CPU cores. 31 32 Otherwise, please say "N" here to avoid unnecessary overhead. 33 34config ERRATA_MIPS_P8700_PAUSE_OPCODE 35 bool "Fix the PAUSE Opcode for MIPS P8700" 36 depends on ERRATA_MIPS && 64BIT 37 default n 38 help 39 The RISCV MIPS P8700 uses a different opcode for PAUSE. 40 It is a 'hint' encoding of the SLLI instruction, 41 with rd=0, rs1=0 and imm=5. It will behave as a NOP 42 instruction if no additional behavior beyond that of 43 SLLI is implemented. 44 45 If you are not using the P8700 processor, say n. 46 47config ERRATA_SIFIVE 48 bool "SiFive errata" 49 depends on RISCV_ALTERNATIVE && 64BIT 50 help 51 All SiFive errata Kconfig depend on this Kconfig. Disabling 52 this Kconfig will disable all SiFive errata. Please say "Y" 53 here if your platform uses SiFive CPU cores. 54 55 Otherwise, please say "N" here to avoid unnecessary overhead. 56 57config ERRATA_SIFIVE_CIP_453 58 bool "Apply SiFive errata CIP-453" 59 depends on ERRATA_SIFIVE && 64BIT 60 default y 61 help 62 This will apply the SiFive CIP-453 errata to add sign extension 63 to the $badaddr when exception type is instruction page fault 64 and instruction access fault. 65 66 If you don't know what to do here, say "Y". 67 68config ERRATA_SIFIVE_CIP_1200 69 bool "Apply SiFive errata CIP-1200" 70 depends on ERRATA_SIFIVE && 64BIT 71 default y 72 help 73 This will apply the SiFive CIP-1200 errata to repalce all 74 "sfence.vma addr" with "sfence.vma" to ensure that the addr 75 has been flushed from TLB. 76 77 If you don't know what to do here, say "Y". 78 79config ERRATA_STARFIVE_JH7100 80 bool "StarFive JH7100 support" 81 depends on ARCH_STARFIVE 82 depends on !DMA_DIRECT_REMAP 83 depends on NONPORTABLE 84 select DMA_GLOBAL_POOL 85 select RISCV_DMA_NONCOHERENT 86 select RISCV_NONSTANDARD_CACHE_OPS 87 select CACHEMAINT_FOR_DMA 88 select SIFIVE_CCACHE 89 default n 90 help 91 The StarFive JH7100 was a test chip for the JH7110 and has 92 caches that are non-coherent with respect to peripheral DMAs. 93 It was designed before the Zicbom extension so needs non-standard 94 cache operations through the SiFive cache controller. 95 96 Say "Y" if you want to support the BeagleV Starlight and/or 97 StarFive VisionFive V1 boards. 98 99config ERRATA_SIFIVE_MAL_9092 100 bool "Apply SiFive HLV/HLVX/HSV fence errata" 101 depends on ERRATA_SIFIVE && 64BIT 102 default y 103 help 104 This will apply the SiFive MAL-9092 errata to add fence.rw 105 instructions around all HLV/HLVX/HSV instructions. 106 107 Note: HSTATUS.HU is cleared during KVM initialization. If future 108 changes enable HSTATUS.HU to allow hypervisor instructions in 109 U-mode, additional errata handling may be required. 110 111 If you don't know what to do here, say "Y". 112 113config ERRATA_THEAD 114 bool "T-HEAD errata" 115 depends on RISCV_ALTERNATIVE 116 help 117 All T-HEAD errata Kconfig depend on this Kconfig. Disabling 118 this Kconfig will disable all T-HEAD errata. Please say "Y" 119 here if your platform uses T-HEAD CPU cores. 120 121 Otherwise, please say "N" here to avoid unnecessary overhead. 122 123config ERRATA_THEAD_MAE 124 bool "Apply T-Head's memory attribute extension (XTheadMae) errata" 125 depends on ERRATA_THEAD && 64BIT && MMU 126 select RISCV_ALTERNATIVE_EARLY 127 default y 128 help 129 This will apply the memory attribute extension errata to handle the 130 non-standard PTE utilization on T-Head SoCs (XTheadMae). 131 132 If you don't know what to do here, say "Y". 133 134config ERRATA_THEAD_CMO 135 bool "Apply T-Head cache management errata" 136 depends on ERRATA_THEAD && MMU 137 select DMA_DIRECT_REMAP 138 select RISCV_DMA_NONCOHERENT 139 select RISCV_NONSTANDARD_CACHE_OPS 140 default y 141 help 142 This will apply the cache management errata to handle the 143 non-standard handling on non-coherent operations on T-Head SoCs. 144 145 If you don't know what to do here, say "Y". 146 147config ERRATA_THEAD_PMU 148 bool "Apply T-Head PMU errata" 149 depends on ERRATA_THEAD && RISCV_PMU_SBI 150 default y 151 help 152 The T-Head C9xx cores implement a PMU overflow extension very 153 similar to the core SSCOFPMF extension. 154 155 This will apply the overflow errata to handle the non-standard 156 behaviour via the regular SBI PMU driver and interface. 157 158 If you don't know what to do here, say "Y". 159 160config ERRATA_THEAD_GHOSTWRITE 161 bool "Apply T-Head Ghostwrite errata" 162 depends on ERRATA_THEAD && RISCV_ISA_XTHEADVECTOR 163 default y 164 help 165 The T-Head C9xx cores have a vulnerability in the xtheadvector 166 instruction set. When this errata is enabled, the CPUs will be probed 167 to determine if they are vulnerable and disable xtheadvector. 168 169 If you don't know what to do here, say "Y". 170 171endmenu # "CPU errata selection" 172