1*16216333SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ae06e374SMichael Ellerman /* SPU ELF support for BFD. 3ae06e374SMichael Ellerman 4ae06e374SMichael Ellerman Copyright 2006 Free Software Foundation, Inc. 5ae06e374SMichael Ellerman 6ae06e374SMichael Ellerman This file is part of GDB, GAS, and the GNU binutils. 7ae06e374SMichael Ellerman 8*16216333SThomas Gleixner */ 9ae06e374SMichael Ellerman 10ae06e374SMichael Ellerman 11ae06e374SMichael Ellerman /* These two enums are from rel_apu/common/spu_asm_format.h */ 12ae06e374SMichael Ellerman /* definition of instruction format */ 13ae06e374SMichael Ellerman typedef enum { 14ae06e374SMichael Ellerman RRR, 15ae06e374SMichael Ellerman RI18, 16ae06e374SMichael Ellerman RI16, 17ae06e374SMichael Ellerman RI10, 18ae06e374SMichael Ellerman RI8, 19ae06e374SMichael Ellerman RI7, 20ae06e374SMichael Ellerman RR, 21ae06e374SMichael Ellerman LBT, 22ae06e374SMichael Ellerman LBTI, 23ae06e374SMichael Ellerman IDATA, 24ae06e374SMichael Ellerman UNKNOWN_IFORMAT 25ae06e374SMichael Ellerman } spu_iformat; 26ae06e374SMichael Ellerman 27ae06e374SMichael Ellerman /* These values describe assembly instruction arguments. They indicate 28ae06e374SMichael Ellerman * how to encode, range checking and which relocation to use. */ 29ae06e374SMichael Ellerman typedef enum { 30ae06e374SMichael Ellerman A_T, /* register at pos 0 */ 31ae06e374SMichael Ellerman A_A, /* register at pos 7 */ 32ae06e374SMichael Ellerman A_B, /* register at pos 14 */ 33ae06e374SMichael Ellerman A_C, /* register at pos 21 */ 34ae06e374SMichael Ellerman A_S, /* special purpose register at pos 7 */ 35ae06e374SMichael Ellerman A_H, /* channel register at pos 7 */ 36ae06e374SMichael Ellerman A_P, /* parenthesis, this has to separate regs from immediates */ 37ae06e374SMichael Ellerman A_S3, 38ae06e374SMichael Ellerman A_S6, 39ae06e374SMichael Ellerman A_S7N, 40ae06e374SMichael Ellerman A_S7, 41ae06e374SMichael Ellerman A_U7A, 42ae06e374SMichael Ellerman A_U7B, 43ae06e374SMichael Ellerman A_S10B, 44ae06e374SMichael Ellerman A_S10, 45ae06e374SMichael Ellerman A_S11, 46ae06e374SMichael Ellerman A_S11I, 47ae06e374SMichael Ellerman A_S14, 48ae06e374SMichael Ellerman A_S16, 49ae06e374SMichael Ellerman A_S18, 50ae06e374SMichael Ellerman A_R18, 51ae06e374SMichael Ellerman A_U3, 52ae06e374SMichael Ellerman A_U5, 53ae06e374SMichael Ellerman A_U6, 54ae06e374SMichael Ellerman A_U7, 55ae06e374SMichael Ellerman A_U14, 56ae06e374SMichael Ellerman A_X16, 57ae06e374SMichael Ellerman A_U18, 58ae06e374SMichael Ellerman A_MAX 59ae06e374SMichael Ellerman } spu_aformat; 60ae06e374SMichael Ellerman 61ae06e374SMichael Ellerman enum spu_insns { 62ae06e374SMichael Ellerman #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ 63ae06e374SMichael Ellerman TAG, 64ae06e374SMichael Ellerman #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ 65ae06e374SMichael Ellerman TAG, 66ae06e374SMichael Ellerman #include "spu-insns.h" 67ae06e374SMichael Ellerman #undef APUOP 68ae06e374SMichael Ellerman #undef APUOPFB 69ae06e374SMichael Ellerman M_SPU_MAX 70ae06e374SMichael Ellerman }; 71ae06e374SMichael Ellerman 72ae06e374SMichael Ellerman struct spu_opcode 73ae06e374SMichael Ellerman { 74ae06e374SMichael Ellerman spu_iformat insn_type; 75ae06e374SMichael Ellerman unsigned int opcode; 76ae06e374SMichael Ellerman char *mnemonic; 77ae06e374SMichael Ellerman int arg[5]; 78ae06e374SMichael Ellerman }; 79ae06e374SMichael Ellerman 80ae06e374SMichael Ellerman #define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) 81ae06e374SMichael Ellerman #define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) 82ae06e374SMichael Ellerman 83ae06e374SMichael Ellerman #define DECODE_INSN_RT(insn) (insn & 0x7f) 84ae06e374SMichael Ellerman #define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) 85ae06e374SMichael Ellerman #define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f) 86ae06e374SMichael Ellerman #define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f) 87ae06e374SMichael Ellerman 88ae06e374SMichael Ellerman #define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14) 89ae06e374SMichael Ellerman #define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14) 90ae06e374SMichael Ellerman 91ae06e374SMichael Ellerman /* For branching, immediate loads, hbr and lqa/stqa. */ 92ae06e374SMichael Ellerman #define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7) 93ae06e374SMichael Ellerman #define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7) 94ae06e374SMichael Ellerman 95ae06e374SMichael Ellerman /* for stop */ 96ae06e374SMichael Ellerman #define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0) 97ae06e374SMichael Ellerman 98ae06e374SMichael Ellerman /* For ila */ 99ae06e374SMichael Ellerman #define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7) 100ae06e374SMichael Ellerman #define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7) 101ae06e374SMichael Ellerman 102ae06e374SMichael Ellerman /* For rotate and shift and generate control mask */ 103ae06e374SMichael Ellerman #define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14) 104ae06e374SMichael Ellerman #define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14) 105ae06e374SMichael Ellerman 106ae06e374SMichael Ellerman /* For float <-> int conversion */ 107ae06e374SMichael Ellerman #define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14) 108ae06e374SMichael Ellerman #define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14) 109ae06e374SMichael Ellerman 110ae06e374SMichael Ellerman /* For hbr */ 111ae06e374SMichael Ellerman #define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) 112ae06e374SMichael Ellerman #define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) 113ae06e374SMichael Ellerman #define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) 114ae06e374SMichael Ellerman #define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) 115ae06e374SMichael Ellerman 116