xref: /linux/arch/powerpc/xmon/spu-opc.c (revision 3839a5943977674d224cca541fd0914b942aa466)
1ae06e374SMichael Ellerman /* SPU opcode list
2ae06e374SMichael Ellerman 
3ae06e374SMichael Ellerman    Copyright 2006 Free Software Foundation, Inc.
4ae06e374SMichael Ellerman 
5ae06e374SMichael Ellerman    This file is part of GDB, GAS, and the GNU binutils.
6ae06e374SMichael Ellerman 
7ae06e374SMichael Ellerman    This program is free software; you can redistribute it and/or modify
8ae06e374SMichael Ellerman    it under the terms of the GNU General Public License as published by
9ae06e374SMichael Ellerman    the Free Software Foundation; either version 2 of the License, or
10ae06e374SMichael Ellerman    (at your option) any later version.
11ae06e374SMichael Ellerman 
12ae06e374SMichael Ellerman    This program is distributed in the hope that it will be useful,
13ae06e374SMichael Ellerman    but WITHOUT ANY WARRANTY; without even the implied warranty of
14ae06e374SMichael Ellerman    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15ae06e374SMichael Ellerman    GNU General Public License for more details.
16ae06e374SMichael Ellerman 
17ae06e374SMichael Ellerman    You should have received a copy of the GNU General Public License along
18ae06e374SMichael Ellerman    with this program; if not, write to the Free Software Foundation, Inc.,
19ae06e374SMichael Ellerman    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
20ae06e374SMichael Ellerman 
21*3839a594SAhmed S. Darwish #include <linux/kernel.h>
22ae06e374SMichael Ellerman #include "spu.h"
23ae06e374SMichael Ellerman 
24ae06e374SMichael Ellerman /* This file holds the Spu opcode table */
25ae06e374SMichael Ellerman 
26ae06e374SMichael Ellerman 
27ae06e374SMichael Ellerman /*
28ae06e374SMichael Ellerman    Example contents of spu-insn.h
29ae06e374SMichael Ellerman       id_tag	mode	mode	type	opcode	mnemonic	asmtype	    dependency		FPU	L/S?	branch?	instruction
30ae06e374SMichael Ellerman                 QUAD	WORD                                               (0,RC,RB,RA,RT)    latency
31ae06e374SMichael Ellerman    APUOP(M_LQD,	1,	0,	RI9,	0x1f8,	"lqd",		ASM_RI9IDX,	00012,		FXU,	1,	0)	Load Quadword d-form
32ae06e374SMichael Ellerman  */
33ae06e374SMichael Ellerman 
34ae06e374SMichael Ellerman const struct spu_opcode spu_opcodes[] = {
35ae06e374SMichael Ellerman #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
36ae06e374SMichael Ellerman 	{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
37ae06e374SMichael Ellerman #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
38ae06e374SMichael Ellerman 	{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
39ae06e374SMichael Ellerman #include "spu-insns.h"
40ae06e374SMichael Ellerman #undef APUOP
41ae06e374SMichael Ellerman #undef APUOPFB
42ae06e374SMichael Ellerman };
43ae06e374SMichael Ellerman 
44*3839a594SAhmed S. Darwish const int spu_num_opcodes = ARRAY_SIZE(spu_opcodes);
45