1 /* 2 * Copyright 2016,2017 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #define pr_fmt(fmt) "xive: " fmt 11 12 #include <linux/types.h> 13 #include <linux/irq.h> 14 #include <linux/smp.h> 15 #include <linux/interrupt.h> 16 #include <linux/init.h> 17 #include <linux/of.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 #include <linux/cpumask.h> 21 #include <linux/mm.h> 22 #include <linux/delay.h> 23 #include <linux/libfdt.h> 24 25 #include <asm/prom.h> 26 #include <asm/io.h> 27 #include <asm/smp.h> 28 #include <asm/irq.h> 29 #include <asm/errno.h> 30 #include <asm/xive.h> 31 #include <asm/xive-regs.h> 32 #include <asm/hvcall.h> 33 34 #include "xive-internal.h" 35 36 static u32 xive_queue_shift; 37 38 struct xive_irq_bitmap { 39 unsigned long *bitmap; 40 unsigned int base; 41 unsigned int count; 42 spinlock_t lock; 43 struct list_head list; 44 }; 45 46 static LIST_HEAD(xive_irq_bitmaps); 47 48 static int xive_irq_bitmap_add(int base, int count) 49 { 50 struct xive_irq_bitmap *xibm; 51 52 xibm = kzalloc(sizeof(*xibm), GFP_ATOMIC); 53 if (!xibm) 54 return -ENOMEM; 55 56 spin_lock_init(&xibm->lock); 57 xibm->base = base; 58 xibm->count = count; 59 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL); 60 list_add(&xibm->list, &xive_irq_bitmaps); 61 62 pr_info("Using IRQ range [%x-%x]", xibm->base, 63 xibm->base + xibm->count - 1); 64 return 0; 65 } 66 67 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm) 68 { 69 int irq; 70 71 irq = find_first_zero_bit(xibm->bitmap, xibm->count); 72 if (irq != xibm->count) { 73 set_bit(irq, xibm->bitmap); 74 irq += xibm->base; 75 } else { 76 irq = -ENOMEM; 77 } 78 79 return irq; 80 } 81 82 static int xive_irq_bitmap_alloc(void) 83 { 84 struct xive_irq_bitmap *xibm; 85 unsigned long flags; 86 int irq = -ENOENT; 87 88 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 89 spin_lock_irqsave(&xibm->lock, flags); 90 irq = __xive_irq_bitmap_alloc(xibm); 91 spin_unlock_irqrestore(&xibm->lock, flags); 92 if (irq >= 0) 93 break; 94 } 95 return irq; 96 } 97 98 static void xive_irq_bitmap_free(int irq) 99 { 100 unsigned long flags; 101 struct xive_irq_bitmap *xibm; 102 103 list_for_each_entry(xibm, &xive_irq_bitmaps, list) { 104 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) { 105 spin_lock_irqsave(&xibm->lock, flags); 106 clear_bit(irq - xibm->base, xibm->bitmap); 107 spin_unlock_irqrestore(&xibm->lock, flags); 108 break; 109 } 110 } 111 } 112 113 114 /* Based on the similar routines in RTAS */ 115 static unsigned int plpar_busy_delay_time(long rc) 116 { 117 unsigned int ms = 0; 118 119 if (H_IS_LONG_BUSY(rc)) { 120 ms = get_longbusy_msecs(rc); 121 } else if (rc == H_BUSY) { 122 ms = 10; /* seems appropriate for XIVE hcalls */ 123 } 124 125 return ms; 126 } 127 128 static unsigned int plpar_busy_delay(int rc) 129 { 130 unsigned int ms; 131 132 ms = plpar_busy_delay_time(rc); 133 if (ms) 134 mdelay(ms); 135 136 return ms; 137 } 138 139 /* 140 * Note: this call has a partition wide scope and can take a while to 141 * complete. If it returns H_LONG_BUSY_* it should be retried 142 * periodically. 143 */ 144 static long plpar_int_reset(unsigned long flags) 145 { 146 long rc; 147 148 do { 149 rc = plpar_hcall_norets(H_INT_RESET, flags); 150 } while (plpar_busy_delay(rc)); 151 152 if (rc) 153 pr_err("H_INT_RESET failed %ld\n", rc); 154 155 return rc; 156 } 157 158 static long plpar_int_get_source_info(unsigned long flags, 159 unsigned long lisn, 160 unsigned long *src_flags, 161 unsigned long *eoi_page, 162 unsigned long *trig_page, 163 unsigned long *esb_shift) 164 { 165 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 166 long rc; 167 168 do { 169 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn); 170 } while (plpar_busy_delay(rc)); 171 172 if (rc) { 173 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc); 174 return rc; 175 } 176 177 *src_flags = retbuf[0]; 178 *eoi_page = retbuf[1]; 179 *trig_page = retbuf[2]; 180 *esb_shift = retbuf[3]; 181 182 pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n", 183 retbuf[0], retbuf[1], retbuf[2], retbuf[3]); 184 185 return 0; 186 } 187 188 #define XIVE_SRC_SET_EISN (1ull << (63 - 62)) 189 #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */ 190 191 static long plpar_int_set_source_config(unsigned long flags, 192 unsigned long lisn, 193 unsigned long target, 194 unsigned long prio, 195 unsigned long sw_irq) 196 { 197 long rc; 198 199 200 pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n", 201 flags, lisn, target, prio, sw_irq); 202 203 204 do { 205 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn, 206 target, prio, sw_irq); 207 } while (plpar_busy_delay(rc)); 208 209 if (rc) { 210 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n", 211 lisn, target, prio, rc); 212 return rc; 213 } 214 215 return 0; 216 } 217 218 static long plpar_int_get_queue_info(unsigned long flags, 219 unsigned long target, 220 unsigned long priority, 221 unsigned long *esn_page, 222 unsigned long *esn_size) 223 { 224 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 225 long rc; 226 227 do { 228 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, 229 priority); 230 } while (plpar_busy_delay(rc)); 231 232 if (rc) { 233 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n", 234 target, priority, rc); 235 return rc; 236 } 237 238 *esn_page = retbuf[0]; 239 *esn_size = retbuf[1]; 240 241 pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n", 242 retbuf[0], retbuf[1]); 243 244 return 0; 245 } 246 247 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63)) 248 249 static long plpar_int_set_queue_config(unsigned long flags, 250 unsigned long target, 251 unsigned long priority, 252 unsigned long qpage, 253 unsigned long qsize) 254 { 255 long rc; 256 257 pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n", 258 flags, target, priority, qpage, qsize); 259 260 do { 261 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target, 262 priority, qpage, qsize); 263 } while (plpar_busy_delay(rc)); 264 265 if (rc) { 266 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n", 267 target, priority, qpage, rc); 268 return rc; 269 } 270 271 return 0; 272 } 273 274 static long plpar_int_sync(unsigned long flags, unsigned long lisn) 275 { 276 long rc; 277 278 do { 279 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn); 280 } while (plpar_busy_delay(rc)); 281 282 if (rc) { 283 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc); 284 return rc; 285 } 286 287 return 0; 288 } 289 290 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63)) 291 292 static long plpar_int_esb(unsigned long flags, 293 unsigned long lisn, 294 unsigned long offset, 295 unsigned long in_data, 296 unsigned long *out_data) 297 { 298 unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 299 long rc; 300 301 pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n", 302 flags, lisn, offset, in_data); 303 304 do { 305 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, 306 in_data); 307 } while (plpar_busy_delay(rc)); 308 309 if (rc) { 310 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n", 311 lisn, offset, rc); 312 return rc; 313 } 314 315 *out_data = retbuf[0]; 316 317 return 0; 318 } 319 320 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write) 321 { 322 unsigned long read_data; 323 long rc; 324 325 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0, 326 lisn, offset, data, &read_data); 327 if (rc) 328 return -1; 329 330 return write ? 0 : read_data; 331 } 332 333 #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) 334 #define XIVE_SRC_LSI (1ull << (63 - 61)) 335 #define XIVE_SRC_TRIGGER (1ull << (63 - 62)) 336 #define XIVE_SRC_STORE_EOI (1ull << (63 - 63)) 337 338 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 339 { 340 long rc; 341 unsigned long flags; 342 unsigned long eoi_page; 343 unsigned long trig_page; 344 unsigned long esb_shift; 345 346 memset(data, 0, sizeof(*data)); 347 348 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page, 349 &esb_shift); 350 if (rc) 351 return -EINVAL; 352 353 if (flags & XIVE_SRC_H_INT_ESB) 354 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB; 355 if (flags & XIVE_SRC_STORE_EOI) 356 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 357 if (flags & XIVE_SRC_LSI) 358 data->flags |= XIVE_IRQ_FLAG_LSI; 359 data->eoi_page = eoi_page; 360 data->esb_shift = esb_shift; 361 data->trig_page = trig_page; 362 363 /* 364 * No chip-id for the sPAPR backend. This has an impact how we 365 * pick a target. See xive_pick_irq_target(). 366 */ 367 data->src_chip = XIVE_INVALID_CHIP_ID; 368 369 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 370 if (!data->eoi_mmio) { 371 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 372 return -ENOMEM; 373 } 374 375 data->hw_irq = hw_irq; 376 377 /* Full function page supports trigger */ 378 if (flags & XIVE_SRC_TRIGGER) { 379 data->trig_mmio = data->eoi_mmio; 380 return 0; 381 } 382 383 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 384 if (!data->trig_mmio) { 385 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 386 return -ENOMEM; 387 } 388 return 0; 389 } 390 391 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 392 { 393 long rc; 394 395 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target, 396 prio, sw_irq); 397 398 return rc == 0 ? 0 : -ENXIO; 399 } 400 401 /* This can be called multiple time to change a queue configuration */ 402 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio, 403 __be32 *qpage, u32 order) 404 { 405 s64 rc = 0; 406 unsigned long esn_page; 407 unsigned long esn_size; 408 u64 flags, qpage_phys; 409 410 /* If there's an actual queue page, clean it */ 411 if (order) { 412 if (WARN_ON(!qpage)) 413 return -EINVAL; 414 qpage_phys = __pa(qpage); 415 } else { 416 qpage_phys = 0; 417 } 418 419 /* Initialize the rest of the fields */ 420 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 421 q->idx = 0; 422 q->toggle = 0; 423 424 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size); 425 if (rc) { 426 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc, 427 target, prio); 428 rc = -EIO; 429 goto fail; 430 } 431 432 /* TODO: add support for the notification page */ 433 q->eoi_phys = esn_page; 434 435 /* Default is to always notify */ 436 flags = XIVE_EQ_ALWAYS_NOTIFY; 437 438 /* Configure and enable the queue in HW */ 439 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order); 440 if (rc) { 441 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc, 442 target, prio); 443 rc = -EIO; 444 } else { 445 q->qpage = qpage; 446 } 447 fail: 448 return rc; 449 } 450 451 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc, 452 u8 prio) 453 { 454 struct xive_q *q = &xc->queue[prio]; 455 __be32 *qpage; 456 457 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 458 if (IS_ERR(qpage)) 459 return PTR_ERR(qpage); 460 461 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu), 462 q, prio, qpage, xive_queue_shift); 463 } 464 465 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, 466 u8 prio) 467 { 468 struct xive_q *q = &xc->queue[prio]; 469 unsigned int alloc_order; 470 long rc; 471 int hw_cpu = get_hard_smp_processor_id(cpu); 472 473 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0); 474 if (rc) 475 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc, 476 hw_cpu, prio); 477 478 alloc_order = xive_alloc_order(xive_queue_shift); 479 free_pages((unsigned long)q->qpage, alloc_order); 480 q->qpage = NULL; 481 } 482 483 static bool xive_spapr_match(struct device_node *node) 484 { 485 /* Ignore cascaded controllers for the moment */ 486 return 1; 487 } 488 489 #ifdef CONFIG_SMP 490 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc) 491 { 492 int irq = xive_irq_bitmap_alloc(); 493 494 if (irq < 0) { 495 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 496 return -ENXIO; 497 } 498 499 xc->hw_ipi = irq; 500 return 0; 501 } 502 503 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc) 504 { 505 if (!xc->hw_ipi) 506 return; 507 508 xive_irq_bitmap_free(xc->hw_ipi); 509 xc->hw_ipi = 0; 510 } 511 #endif /* CONFIG_SMP */ 512 513 static void xive_spapr_shutdown(void) 514 { 515 plpar_int_reset(0); 516 } 517 518 /* 519 * Perform an "ack" cycle on the current thread. Grab the pending 520 * active priorities and update the CPPR to the most favored one. 521 */ 522 static void xive_spapr_update_pending(struct xive_cpu *xc) 523 { 524 u8 nsr, cppr; 525 u16 ack; 526 527 /* 528 * Perform the "Acknowledge O/S to Register" cycle. 529 * 530 * Let's speedup the access to the TIMA using the raw I/O 531 * accessor as we don't need the synchronisation routine of 532 * the higher level ones 533 */ 534 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG)); 535 536 /* Synchronize subsequent queue accesses */ 537 mb(); 538 539 /* 540 * Grab the CPPR and the "NSR" field which indicates the source 541 * of the interrupt (if any) 542 */ 543 cppr = ack & 0xff; 544 nsr = ack >> 8; 545 546 if (nsr & TM_QW1_NSR_EO) { 547 if (cppr == 0xff) 548 return; 549 /* Mark the priority pending */ 550 xc->pending_prio |= 1 << cppr; 551 552 /* 553 * A new interrupt should never have a CPPR less favored 554 * than our current one. 555 */ 556 if (cppr >= xc->cppr) 557 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 558 smp_processor_id(), cppr, xc->cppr); 559 560 /* Update our idea of what the CPPR is */ 561 xc->cppr = cppr; 562 } 563 } 564 565 static void xive_spapr_eoi(u32 hw_irq) 566 { 567 /* Not used */; 568 } 569 570 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 571 { 572 /* Only some debug on the TIMA settings */ 573 pr_debug("(HW value: %08x %08x %08x)\n", 574 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), 575 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), 576 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); 577 } 578 579 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 580 { 581 /* Nothing to do */; 582 } 583 584 static void xive_spapr_sync_source(u32 hw_irq) 585 { 586 /* Specs are unclear on what this is doing */ 587 plpar_int_sync(0, hw_irq); 588 } 589 590 static const struct xive_ops xive_spapr_ops = { 591 .populate_irq_data = xive_spapr_populate_irq_data, 592 .configure_irq = xive_spapr_configure_irq, 593 .setup_queue = xive_spapr_setup_queue, 594 .cleanup_queue = xive_spapr_cleanup_queue, 595 .match = xive_spapr_match, 596 .shutdown = xive_spapr_shutdown, 597 .update_pending = xive_spapr_update_pending, 598 .eoi = xive_spapr_eoi, 599 .setup_cpu = xive_spapr_setup_cpu, 600 .teardown_cpu = xive_spapr_teardown_cpu, 601 .sync_source = xive_spapr_sync_source, 602 .esb_rw = xive_spapr_esb_rw, 603 #ifdef CONFIG_SMP 604 .get_ipi = xive_spapr_get_ipi, 605 .put_ipi = xive_spapr_put_ipi, 606 #endif /* CONFIG_SMP */ 607 .name = "spapr", 608 }; 609 610 /* 611 * get max priority from "/ibm,plat-res-int-priorities" 612 */ 613 static bool xive_get_max_prio(u8 *max_prio) 614 { 615 struct device_node *rootdn; 616 const __be32 *reg; 617 u32 len; 618 int prio, found; 619 620 rootdn = of_find_node_by_path("/"); 621 if (!rootdn) { 622 pr_err("not root node found !\n"); 623 return false; 624 } 625 626 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len); 627 if (!reg) { 628 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n"); 629 return false; 630 } 631 632 if (len % (2 * sizeof(u32)) != 0) { 633 pr_err("invalid 'ibm,plat-res-int-priorities' property\n"); 634 return false; 635 } 636 637 /* HW supports priorities in the range [0-7] and 0xFF is a 638 * wildcard priority used to mask. We scan the ranges reserved 639 * by the hypervisor to find the lowest priority we can use. 640 */ 641 found = 0xFF; 642 for (prio = 0; prio < 8; prio++) { 643 int reserved = 0; 644 int i; 645 646 for (i = 0; i < len / (2 * sizeof(u32)); i++) { 647 int base = be32_to_cpu(reg[2 * i]); 648 int range = be32_to_cpu(reg[2 * i + 1]); 649 650 if (prio >= base && prio < base + range) 651 reserved++; 652 } 653 654 if (!reserved) 655 found = prio; 656 } 657 658 if (found == 0xFF) { 659 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n"); 660 return false; 661 } 662 663 *max_prio = found; 664 return true; 665 } 666 667 static const u8 *get_vec5_feature(unsigned int index) 668 { 669 unsigned long root, chosen; 670 int size; 671 const u8 *vec5; 672 673 root = of_get_flat_dt_root(); 674 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 675 if (chosen == -FDT_ERR_NOTFOUND) 676 return NULL; 677 678 vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size); 679 if (!vec5) 680 return NULL; 681 682 if (size <= index) 683 return NULL; 684 685 return vec5 + index; 686 } 687 688 static bool xive_spapr_disabled(void) 689 { 690 const u8 *vec5_xive; 691 692 vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT)); 693 if (vec5_xive) { 694 u8 val; 695 696 val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT); 697 switch (val) { 698 case OV5_FEAT(OV5_XIVE_EITHER): 699 case OV5_FEAT(OV5_XIVE_LEGACY): 700 break; 701 case OV5_FEAT(OV5_XIVE_EXPLOIT): 702 /* Hypervisor only supports XIVE */ 703 if (xive_cmdline_disabled) 704 pr_warn("WARNING: Ignoring cmdline option xive=off\n"); 705 return false; 706 default: 707 pr_warn("%s: Unknown xive support option: 0x%x\n", 708 __func__, val); 709 break; 710 } 711 } 712 713 return xive_cmdline_disabled; 714 } 715 716 bool __init xive_spapr_init(void) 717 { 718 struct device_node *np; 719 struct resource r; 720 void __iomem *tima; 721 struct property *prop; 722 u8 max_prio; 723 u32 val; 724 u32 len; 725 const __be32 *reg; 726 int i; 727 728 if (xive_spapr_disabled()) 729 return false; 730 731 pr_devel("%s()\n", __func__); 732 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe"); 733 if (!np) { 734 pr_devel("not found !\n"); 735 return false; 736 } 737 pr_devel("Found %s\n", np->full_name); 738 739 /* Resource 1 is the OS ring TIMA */ 740 if (of_address_to_resource(np, 1, &r)) { 741 pr_err("Failed to get thread mgmnt area resource\n"); 742 return false; 743 } 744 tima = ioremap(r.start, resource_size(&r)); 745 if (!tima) { 746 pr_err("Failed to map thread mgmnt area\n"); 747 return false; 748 } 749 750 if (!xive_get_max_prio(&max_prio)) 751 return false; 752 753 /* Feed the IRQ number allocator with the ranges given in the DT */ 754 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len); 755 if (!reg) { 756 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n"); 757 return false; 758 } 759 760 if (len % (2 * sizeof(u32)) != 0) { 761 pr_err("invalid 'ibm,xive-lisn-ranges' property\n"); 762 return false; 763 } 764 765 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) 766 xive_irq_bitmap_add(be32_to_cpu(reg[0]), 767 be32_to_cpu(reg[1])); 768 769 /* Iterate the EQ sizes and pick one */ 770 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) { 771 xive_queue_shift = val; 772 if (val == PAGE_SHIFT) 773 break; 774 } 775 776 /* Initialize XIVE core with our backend */ 777 if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio)) 778 return false; 779 780 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 781 return true; 782 } 783