1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 6 #define pr_fmt(fmt) "xive: " fmt 7 8 #include <linux/types.h> 9 #include <linux/irq.h> 10 #include <linux/debugfs.h> 11 #include <linux/smp.h> 12 #include <linux/interrupt.h> 13 #include <linux/seq_file.h> 14 #include <linux/init.h> 15 #include <linux/of.h> 16 #include <linux/slab.h> 17 #include <linux/spinlock.h> 18 #include <linux/delay.h> 19 #include <linux/cpumask.h> 20 #include <linux/mm.h> 21 22 #include <asm/prom.h> 23 #include <asm/io.h> 24 #include <asm/smp.h> 25 #include <asm/irq.h> 26 #include <asm/errno.h> 27 #include <asm/xive.h> 28 #include <asm/xive-regs.h> 29 #include <asm/opal.h> 30 #include <asm/kvm_ppc.h> 31 32 #include "xive-internal.h" 33 34 35 static u32 xive_provision_size; 36 static u32 *xive_provision_chips; 37 static u32 xive_provision_chip_count; 38 static u32 xive_queue_shift; 39 static u32 xive_pool_vps = XIVE_INVALID_VP; 40 static struct kmem_cache *xive_provision_cache; 41 static bool xive_has_single_esc; 42 43 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 44 { 45 __be64 flags, eoi_page, trig_page; 46 __be32 esb_shift, src_chip; 47 u64 opal_flags; 48 s64 rc; 49 50 memset(data, 0, sizeof(*data)); 51 52 rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page, 53 &esb_shift, &src_chip); 54 if (rc) { 55 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n", 56 hw_irq, rc); 57 return -EINVAL; 58 } 59 60 opal_flags = be64_to_cpu(flags); 61 if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI) 62 data->flags |= XIVE_IRQ_FLAG_STORE_EOI; 63 if (opal_flags & OPAL_XIVE_IRQ_LSI) 64 data->flags |= XIVE_IRQ_FLAG_LSI; 65 if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG) 66 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG; 67 if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW) 68 data->flags |= XIVE_IRQ_FLAG_MASK_FW; 69 if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW) 70 data->flags |= XIVE_IRQ_FLAG_EOI_FW; 71 data->eoi_page = be64_to_cpu(eoi_page); 72 data->trig_page = be64_to_cpu(trig_page); 73 data->esb_shift = be32_to_cpu(esb_shift); 74 data->src_chip = be32_to_cpu(src_chip); 75 76 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); 77 if (!data->eoi_mmio) { 78 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); 79 return -ENOMEM; 80 } 81 82 data->hw_irq = hw_irq; 83 84 if (!data->trig_page) 85 return 0; 86 if (data->trig_page == data->eoi_page) { 87 data->trig_mmio = data->eoi_mmio; 88 return 0; 89 } 90 91 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); 92 if (!data->trig_mmio) { 93 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); 94 return -ENOMEM; 95 } 96 return 0; 97 } 98 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data); 99 100 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) 101 { 102 s64 rc; 103 104 for (;;) { 105 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); 106 if (rc != OPAL_BUSY) 107 break; 108 msleep(OPAL_BUSY_DELAY_MS); 109 } 110 return rc == 0 ? 0 : -ENXIO; 111 } 112 EXPORT_SYMBOL_GPL(xive_native_configure_irq); 113 114 static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, 115 u32 *sw_irq) 116 { 117 s64 rc; 118 __be64 vp; 119 __be32 lirq; 120 121 rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq); 122 123 *target = be64_to_cpu(vp); 124 *sw_irq = be32_to_cpu(lirq); 125 126 return rc == 0 ? 0 : -ENXIO; 127 } 128 129 /* This can be called multiple time to change a queue configuration */ 130 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 131 __be32 *qpage, u32 order, bool can_escalate) 132 { 133 s64 rc = 0; 134 __be64 qeoi_page_be; 135 __be32 esc_irq_be; 136 u64 flags, qpage_phys; 137 138 /* If there's an actual queue page, clean it */ 139 if (order) { 140 if (WARN_ON(!qpage)) 141 return -EINVAL; 142 qpage_phys = __pa(qpage); 143 } else 144 qpage_phys = 0; 145 146 /* Initialize the rest of the fields */ 147 q->msk = order ? ((1u << (order - 2)) - 1) : 0; 148 q->idx = 0; 149 q->toggle = 0; 150 151 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, 152 &qeoi_page_be, 153 &esc_irq_be, 154 NULL); 155 if (rc) { 156 pr_err("Error %lld getting queue info prio %d\n", rc, prio); 157 rc = -EIO; 158 goto fail; 159 } 160 q->eoi_phys = be64_to_cpu(qeoi_page_be); 161 162 /* Default flags */ 163 flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED; 164 165 /* Escalation needed ? */ 166 if (can_escalate) { 167 q->esc_irq = be32_to_cpu(esc_irq_be); 168 flags |= OPAL_XIVE_EQ_ESCALATE; 169 } 170 171 /* Configure and enable the queue in HW */ 172 for (;;) { 173 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); 174 if (rc != OPAL_BUSY) 175 break; 176 msleep(OPAL_BUSY_DELAY_MS); 177 } 178 if (rc) { 179 pr_err("Error %lld setting queue for prio %d\n", rc, prio); 180 rc = -EIO; 181 } else { 182 /* 183 * KVM code requires all of the above to be visible before 184 * q->qpage is set due to how it manages IPI EOIs 185 */ 186 wmb(); 187 q->qpage = qpage; 188 } 189 fail: 190 return rc; 191 } 192 EXPORT_SYMBOL_GPL(xive_native_configure_queue); 193 194 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 195 { 196 s64 rc; 197 198 /* Disable the queue in HW */ 199 for (;;) { 200 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); 201 if (rc != OPAL_BUSY) 202 break; 203 msleep(OPAL_BUSY_DELAY_MS); 204 } 205 if (rc) 206 pr_err("Error %lld disabling queue for prio %d\n", rc, prio); 207 } 208 209 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) 210 { 211 __xive_native_disable_queue(vp_id, q, prio); 212 } 213 EXPORT_SYMBOL_GPL(xive_native_disable_queue); 214 215 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 216 { 217 struct xive_q *q = &xc->queue[prio]; 218 __be32 *qpage; 219 220 qpage = xive_queue_page_alloc(cpu, xive_queue_shift); 221 if (IS_ERR(qpage)) 222 return PTR_ERR(qpage); 223 224 return xive_native_configure_queue(get_hard_smp_processor_id(cpu), 225 q, prio, qpage, xive_queue_shift, false); 226 } 227 228 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) 229 { 230 struct xive_q *q = &xc->queue[prio]; 231 unsigned int alloc_order; 232 233 /* 234 * We use the variant with no iounmap as this is called on exec 235 * from an IPI and iounmap isn't safe 236 */ 237 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio); 238 alloc_order = xive_alloc_order(xive_queue_shift); 239 free_pages((unsigned long)q->qpage, alloc_order); 240 q->qpage = NULL; 241 } 242 243 static bool xive_native_match(struct device_node *node) 244 { 245 return of_device_is_compatible(node, "ibm,opal-xive-vc"); 246 } 247 248 #ifdef CONFIG_SMP 249 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) 250 { 251 s64 irq; 252 253 /* Allocate an IPI and populate info about it */ 254 for (;;) { 255 irq = opal_xive_allocate_irq(xc->chip_id); 256 if (irq == OPAL_BUSY) { 257 msleep(OPAL_BUSY_DELAY_MS); 258 continue; 259 } 260 if (irq < 0) { 261 pr_err("Failed to allocate IPI on CPU %d\n", cpu); 262 return -ENXIO; 263 } 264 xc->hw_ipi = irq; 265 break; 266 } 267 return 0; 268 } 269 #endif /* CONFIG_SMP */ 270 271 u32 xive_native_alloc_irq(void) 272 { 273 s64 rc; 274 275 for (;;) { 276 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP); 277 if (rc != OPAL_BUSY) 278 break; 279 msleep(OPAL_BUSY_DELAY_MS); 280 } 281 if (rc < 0) 282 return 0; 283 return rc; 284 } 285 EXPORT_SYMBOL_GPL(xive_native_alloc_irq); 286 287 void xive_native_free_irq(u32 irq) 288 { 289 for (;;) { 290 s64 rc = opal_xive_free_irq(irq); 291 if (rc != OPAL_BUSY) 292 break; 293 msleep(OPAL_BUSY_DELAY_MS); 294 } 295 } 296 EXPORT_SYMBOL_GPL(xive_native_free_irq); 297 298 #ifdef CONFIG_SMP 299 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) 300 { 301 s64 rc; 302 303 /* Free the IPI */ 304 if (!xc->hw_ipi) 305 return; 306 for (;;) { 307 rc = opal_xive_free_irq(xc->hw_ipi); 308 if (rc == OPAL_BUSY) { 309 msleep(OPAL_BUSY_DELAY_MS); 310 continue; 311 } 312 xc->hw_ipi = 0; 313 break; 314 } 315 } 316 #endif /* CONFIG_SMP */ 317 318 static void xive_native_shutdown(void) 319 { 320 /* Switch the XIVE to emulation mode */ 321 opal_xive_reset(OPAL_XIVE_MODE_EMU); 322 } 323 324 /* 325 * Perform an "ack" cycle on the current thread, thus 326 * grabbing the pending active priorities and updating 327 * the CPPR to the most favored one. 328 */ 329 static void xive_native_update_pending(struct xive_cpu *xc) 330 { 331 u8 he, cppr; 332 u16 ack; 333 334 /* Perform the acknowledge hypervisor to register cycle */ 335 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG)); 336 337 /* Synchronize subsequent queue accesses */ 338 mb(); 339 340 /* 341 * Grab the CPPR and the "HE" field which indicates the source 342 * of the hypervisor interrupt (if any) 343 */ 344 cppr = ack & 0xff; 345 he = (ack >> 8) >> 6; 346 switch(he) { 347 case TM_QW3_NSR_HE_NONE: /* Nothing to see here */ 348 break; 349 case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */ 350 if (cppr == 0xff) 351 return; 352 /* Mark the priority pending */ 353 xc->pending_prio |= 1 << cppr; 354 355 /* 356 * A new interrupt should never have a CPPR less favored 357 * than our current one. 358 */ 359 if (cppr >= xc->cppr) 360 pr_err("CPU %d odd ack CPPR, got %d at %d\n", 361 smp_processor_id(), cppr, xc->cppr); 362 363 /* Update our idea of what the CPPR is */ 364 xc->cppr = cppr; 365 break; 366 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */ 367 case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */ 368 pr_err("CPU %d got unexpected interrupt type HE=%d\n", 369 smp_processor_id(), he); 370 return; 371 } 372 } 373 374 static void xive_native_eoi(u32 hw_irq) 375 { 376 /* 377 * Not normally used except if specific interrupts need 378 * a workaround on EOI. 379 */ 380 opal_int_eoi(hw_irq); 381 } 382 383 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) 384 { 385 s64 rc; 386 u32 vp; 387 __be64 vp_cam_be; 388 u64 vp_cam; 389 390 if (xive_pool_vps == XIVE_INVALID_VP) 391 return; 392 393 /* Check if pool VP already active, if it is, pull it */ 394 if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP) 395 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 396 397 /* Enable the pool VP */ 398 vp = xive_pool_vps + cpu; 399 for (;;) { 400 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); 401 if (rc != OPAL_BUSY) 402 break; 403 msleep(OPAL_BUSY_DELAY_MS); 404 } 405 if (rc) { 406 pr_err("Failed to enable pool VP on CPU %d\n", cpu); 407 return; 408 } 409 410 /* Grab it's CAM value */ 411 rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL); 412 if (rc) { 413 pr_err("Failed to get pool VP info CPU %d\n", cpu); 414 return; 415 } 416 vp_cam = be64_to_cpu(vp_cam_be); 417 418 /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */ 419 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff); 420 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam); 421 } 422 423 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) 424 { 425 s64 rc; 426 u32 vp; 427 428 if (xive_pool_vps == XIVE_INVALID_VP) 429 return; 430 431 /* Pull the pool VP from the CPU */ 432 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); 433 434 /* Disable it */ 435 vp = xive_pool_vps + cpu; 436 for (;;) { 437 rc = opal_xive_set_vp_info(vp, 0, 0); 438 if (rc != OPAL_BUSY) 439 break; 440 msleep(OPAL_BUSY_DELAY_MS); 441 } 442 } 443 444 void xive_native_sync_source(u32 hw_irq) 445 { 446 opal_xive_sync(XIVE_SYNC_EAS, hw_irq); 447 } 448 EXPORT_SYMBOL_GPL(xive_native_sync_source); 449 450 void xive_native_sync_queue(u32 hw_irq) 451 { 452 opal_xive_sync(XIVE_SYNC_QUEUE, hw_irq); 453 } 454 EXPORT_SYMBOL_GPL(xive_native_sync_queue); 455 456 static const struct xive_ops xive_native_ops = { 457 .populate_irq_data = xive_native_populate_irq_data, 458 .configure_irq = xive_native_configure_irq, 459 .get_irq_config = xive_native_get_irq_config, 460 .setup_queue = xive_native_setup_queue, 461 .cleanup_queue = xive_native_cleanup_queue, 462 .match = xive_native_match, 463 .shutdown = xive_native_shutdown, 464 .update_pending = xive_native_update_pending, 465 .eoi = xive_native_eoi, 466 .setup_cpu = xive_native_setup_cpu, 467 .teardown_cpu = xive_native_teardown_cpu, 468 .sync_source = xive_native_sync_source, 469 #ifdef CONFIG_SMP 470 .get_ipi = xive_native_get_ipi, 471 .put_ipi = xive_native_put_ipi, 472 #endif /* CONFIG_SMP */ 473 .name = "native", 474 }; 475 476 static bool xive_parse_provisioning(struct device_node *np) 477 { 478 int rc; 479 480 if (of_property_read_u32(np, "ibm,xive-provision-page-size", 481 &xive_provision_size) < 0) 482 return true; 483 rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4); 484 if (rc < 0) { 485 pr_err("Error %d getting provision chips array\n", rc); 486 return false; 487 } 488 xive_provision_chip_count = rc; 489 if (rc == 0) 490 return true; 491 492 xive_provision_chips = kcalloc(4, xive_provision_chip_count, 493 GFP_KERNEL); 494 if (WARN_ON(!xive_provision_chips)) 495 return false; 496 497 rc = of_property_read_u32_array(np, "ibm,xive-provision-chips", 498 xive_provision_chips, 499 xive_provision_chip_count); 500 if (rc < 0) { 501 pr_err("Error %d reading provision chips array\n", rc); 502 return false; 503 } 504 505 xive_provision_cache = kmem_cache_create("xive-provision", 506 xive_provision_size, 507 xive_provision_size, 508 0, NULL); 509 if (!xive_provision_cache) { 510 pr_err("Failed to allocate provision cache\n"); 511 return false; 512 } 513 return true; 514 } 515 516 static void xive_native_setup_pools(void) 517 { 518 /* Allocate a pool big enough */ 519 pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids); 520 521 xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids); 522 if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP)) 523 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n"); 524 525 pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n", 526 xive_pool_vps, nr_cpu_ids); 527 } 528 529 u32 xive_native_default_eq_shift(void) 530 { 531 return xive_queue_shift; 532 } 533 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift); 534 535 unsigned long xive_tima_os; 536 EXPORT_SYMBOL_GPL(xive_tima_os); 537 538 bool __init xive_native_init(void) 539 { 540 struct device_node *np; 541 struct resource r; 542 void __iomem *tima; 543 struct property *prop; 544 u8 max_prio = 7; 545 const __be32 *p; 546 u32 val, cpu; 547 s64 rc; 548 549 if (xive_cmdline_disabled) 550 return false; 551 552 pr_devel("xive_native_init()\n"); 553 np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe"); 554 if (!np) { 555 pr_devel("not found !\n"); 556 return false; 557 } 558 pr_devel("Found %pOF\n", np); 559 560 /* Resource 1 is HV window */ 561 if (of_address_to_resource(np, 1, &r)) { 562 pr_err("Failed to get thread mgmnt area resource\n"); 563 return false; 564 } 565 tima = ioremap(r.start, resource_size(&r)); 566 if (!tima) { 567 pr_err("Failed to map thread mgmnt area\n"); 568 return false; 569 } 570 571 /* Read number of priorities */ 572 if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0) 573 max_prio = val - 1; 574 575 /* Iterate the EQ sizes and pick one */ 576 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) { 577 xive_queue_shift = val; 578 if (val == PAGE_SHIFT) 579 break; 580 } 581 582 /* Do we support single escalation */ 583 if (of_get_property(np, "single-escalation-support", NULL) != NULL) 584 xive_has_single_esc = true; 585 586 /* Configure Thread Management areas for KVM */ 587 for_each_possible_cpu(cpu) 588 kvmppc_set_xive_tima(cpu, r.start, tima); 589 590 /* Resource 2 is OS window */ 591 if (of_address_to_resource(np, 2, &r)) { 592 pr_err("Failed to get thread mgmnt area resource\n"); 593 return false; 594 } 595 596 xive_tima_os = r.start; 597 598 /* Grab size of provisionning pages */ 599 xive_parse_provisioning(np); 600 601 /* Switch the XIVE to exploitation mode */ 602 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL); 603 if (rc) { 604 pr_err("Switch to exploitation mode failed with error %lld\n", rc); 605 return false; 606 } 607 608 /* Setup some dummy HV pool VPs */ 609 xive_native_setup_pools(); 610 611 /* Initialize XIVE core with our backend */ 612 if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS, 613 max_prio)) { 614 opal_xive_reset(OPAL_XIVE_MODE_EMU); 615 return false; 616 } 617 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 618 return true; 619 } 620 621 static bool xive_native_provision_pages(void) 622 { 623 u32 i; 624 void *p; 625 626 for (i = 0; i < xive_provision_chip_count; i++) { 627 u32 chip = xive_provision_chips[i]; 628 629 /* 630 * XXX TODO: Try to make the allocation local to the node where 631 * the chip resides. 632 */ 633 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL); 634 if (!p) { 635 pr_err("Failed to allocate provisioning page\n"); 636 return false; 637 } 638 opal_xive_donate_page(chip, __pa(p)); 639 } 640 return true; 641 } 642 643 u32 xive_native_alloc_vp_block(u32 max_vcpus) 644 { 645 s64 rc; 646 u32 order; 647 648 order = fls(max_vcpus) - 1; 649 if (max_vcpus > (1 << order)) 650 order++; 651 652 pr_debug("VP block alloc, for max VCPUs %d use order %d\n", 653 max_vcpus, order); 654 655 for (;;) { 656 rc = opal_xive_alloc_vp_block(order); 657 switch (rc) { 658 case OPAL_BUSY: 659 msleep(OPAL_BUSY_DELAY_MS); 660 break; 661 case OPAL_XIVE_PROVISIONING: 662 if (!xive_native_provision_pages()) 663 return XIVE_INVALID_VP; 664 break; 665 default: 666 if (rc < 0) { 667 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n", 668 order, rc); 669 return XIVE_INVALID_VP; 670 } 671 return rc; 672 } 673 } 674 } 675 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block); 676 677 void xive_native_free_vp_block(u32 vp_base) 678 { 679 s64 rc; 680 681 if (vp_base == XIVE_INVALID_VP) 682 return; 683 684 rc = opal_xive_free_vp_block(vp_base); 685 if (rc < 0) 686 pr_warn("OPAL error %lld freeing VP block\n", rc); 687 } 688 EXPORT_SYMBOL_GPL(xive_native_free_vp_block); 689 690 int xive_native_enable_vp(u32 vp_id, bool single_escalation) 691 { 692 s64 rc; 693 u64 flags = OPAL_XIVE_VP_ENABLED; 694 695 if (single_escalation) 696 flags |= OPAL_XIVE_VP_SINGLE_ESCALATION; 697 for (;;) { 698 rc = opal_xive_set_vp_info(vp_id, flags, 0); 699 if (rc != OPAL_BUSY) 700 break; 701 msleep(OPAL_BUSY_DELAY_MS); 702 } 703 return rc ? -EIO : 0; 704 } 705 EXPORT_SYMBOL_GPL(xive_native_enable_vp); 706 707 int xive_native_disable_vp(u32 vp_id) 708 { 709 s64 rc; 710 711 for (;;) { 712 rc = opal_xive_set_vp_info(vp_id, 0, 0); 713 if (rc != OPAL_BUSY) 714 break; 715 msleep(OPAL_BUSY_DELAY_MS); 716 } 717 return rc ? -EIO : 0; 718 } 719 EXPORT_SYMBOL_GPL(xive_native_disable_vp); 720 721 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id) 722 { 723 __be64 vp_cam_be; 724 __be32 vp_chip_id_be; 725 s64 rc; 726 727 rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be); 728 if (rc) 729 return -EIO; 730 *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu; 731 *out_chip_id = be32_to_cpu(vp_chip_id_be); 732 733 return 0; 734 } 735 EXPORT_SYMBOL_GPL(xive_native_get_vp_info); 736 737 bool xive_native_has_single_escalation(void) 738 { 739 return xive_has_single_esc; 740 } 741 EXPORT_SYMBOL_GPL(xive_native_has_single_escalation); 742 743 int xive_native_get_queue_info(u32 vp_id, u32 prio, 744 u64 *out_qpage, 745 u64 *out_qsize, 746 u64 *out_qeoi_page, 747 u32 *out_escalate_irq, 748 u64 *out_qflags) 749 { 750 __be64 qpage; 751 __be64 qsize; 752 __be64 qeoi_page; 753 __be32 escalate_irq; 754 __be64 qflags; 755 s64 rc; 756 757 rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize, 758 &qeoi_page, &escalate_irq, &qflags); 759 if (rc) { 760 pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n", 761 vp_id, prio, rc); 762 return -EIO; 763 } 764 765 if (out_qpage) 766 *out_qpage = be64_to_cpu(qpage); 767 if (out_qsize) 768 *out_qsize = be32_to_cpu(qsize); 769 if (out_qeoi_page) 770 *out_qeoi_page = be64_to_cpu(qeoi_page); 771 if (out_escalate_irq) 772 *out_escalate_irq = be32_to_cpu(escalate_irq); 773 if (out_qflags) 774 *out_qflags = be64_to_cpu(qflags); 775 776 return 0; 777 } 778 EXPORT_SYMBOL_GPL(xive_native_get_queue_info); 779 780 int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex) 781 { 782 __be32 opal_qtoggle; 783 __be32 opal_qindex; 784 s64 rc; 785 786 rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle, 787 &opal_qindex); 788 if (rc) { 789 pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n", 790 vp_id, prio, rc); 791 return -EIO; 792 } 793 794 if (qtoggle) 795 *qtoggle = be32_to_cpu(opal_qtoggle); 796 if (qindex) 797 *qindex = be32_to_cpu(opal_qindex); 798 799 return 0; 800 } 801 EXPORT_SYMBOL_GPL(xive_native_get_queue_state); 802 803 int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex) 804 { 805 s64 rc; 806 807 rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex); 808 if (rc) { 809 pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n", 810 vp_id, prio, rc); 811 return -EIO; 812 } 813 814 return 0; 815 } 816 EXPORT_SYMBOL_GPL(xive_native_set_queue_state); 817 818 int xive_native_get_vp_state(u32 vp_id, u64 *out_state) 819 { 820 __be64 state; 821 s64 rc; 822 823 rc = opal_xive_get_vp_state(vp_id, &state); 824 if (rc) { 825 pr_err("OPAL failed to get vp state for VCPU %d : %lld\n", 826 vp_id, rc); 827 return -EIO; 828 } 829 830 if (out_state) 831 *out_state = be64_to_cpu(state); 832 return 0; 833 } 834 EXPORT_SYMBOL_GPL(xive_native_get_vp_state); 835