1 /* 2 * Copyright 2016 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 #include <linux/types.h> 10 #include <linux/kernel.h> 11 #include <linux/irq.h> 12 #include <linux/smp.h> 13 #include <linux/interrupt.h> 14 #include <linux/cpu.h> 15 #include <linux/of.h> 16 17 #include <asm/smp.h> 18 #include <asm/irq.h> 19 #include <asm/errno.h> 20 #include <asm/xics.h> 21 #include <asm/io.h> 22 #include <asm/opal.h> 23 #include <asm/kvm_ppc.h> 24 25 static void icp_opal_teardown_cpu(void) 26 { 27 int hw_cpu = hard_smp_processor_id(); 28 29 /* Clear any pending IPI */ 30 opal_int_set_mfrr(hw_cpu, 0xff); 31 } 32 33 static void icp_opal_flush_ipi(void) 34 { 35 /* 36 * We take the ipi irq but and never return so we need to EOI the IPI, 37 * but want to leave our priority 0. 38 * 39 * Should we check all the other interrupts too? 40 * Should we be flagging idle loop instead? 41 * Or creating some task to be scheduled? 42 */ 43 if (opal_int_eoi((0x00 << 24) | XICS_IPI) > 0) 44 force_external_irq_replay(); 45 } 46 47 static unsigned int icp_opal_get_xirr(void) 48 { 49 unsigned int kvm_xirr; 50 __be32 hw_xirr; 51 int64_t rc; 52 53 /* Handle an interrupt latched by KVM first */ 54 kvm_xirr = kvmppc_get_xics_latch(); 55 if (kvm_xirr) 56 return kvm_xirr; 57 58 /* Then ask OPAL */ 59 rc = opal_int_get_xirr(&hw_xirr, false); 60 if (rc < 0) 61 return 0; 62 return be32_to_cpu(hw_xirr); 63 } 64 65 static unsigned int icp_opal_get_irq(void) 66 { 67 unsigned int xirr; 68 unsigned int vec; 69 unsigned int irq; 70 71 xirr = icp_opal_get_xirr(); 72 vec = xirr & 0x00ffffff; 73 if (vec == XICS_IRQ_SPURIOUS) 74 return 0; 75 76 irq = irq_find_mapping(xics_host, vec); 77 if (likely(irq)) { 78 xics_push_cppr(vec); 79 return irq; 80 } 81 82 /* We don't have a linux mapping, so have rtas mask it. */ 83 xics_mask_unknown_vec(vec); 84 85 /* We might learn about it later, so EOI it */ 86 if (opal_int_eoi(xirr) > 0) 87 force_external_irq_replay(); 88 89 return 0; 90 } 91 92 static void icp_opal_set_cpu_priority(unsigned char cppr) 93 { 94 /* 95 * Here be dragons. The caller has asked to allow only IPI's and not 96 * external interrupts. But OPAL XIVE doesn't support that. So instead 97 * of allowing no interrupts allow all. That's still not right, but 98 * currently the only caller who does this is xics_migrate_irqs_away() 99 * and it works in that case. 100 */ 101 if (cppr >= DEFAULT_PRIORITY) 102 cppr = LOWEST_PRIORITY; 103 104 xics_set_base_cppr(cppr); 105 opal_int_set_cppr(cppr); 106 iosync(); 107 } 108 109 static void icp_opal_eoi(struct irq_data *d) 110 { 111 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 112 int64_t rc; 113 114 iosync(); 115 rc = opal_int_eoi((xics_pop_cppr() << 24) | hw_irq); 116 117 /* 118 * EOI tells us whether there are more interrupts to fetch. 119 * 120 * Some HW implementations might not be able to send us another 121 * external interrupt in that case, so we force a replay. 122 */ 123 if (rc > 0) 124 force_external_irq_replay(); 125 } 126 127 #ifdef CONFIG_SMP 128 129 static void icp_opal_cause_ipi(int cpu, unsigned long data) 130 { 131 int hw_cpu = get_hard_smp_processor_id(cpu); 132 133 kvmppc_set_host_ipi(cpu, 1); 134 opal_int_set_mfrr(hw_cpu, IPI_PRIORITY); 135 } 136 137 static irqreturn_t icp_opal_ipi_action(int irq, void *dev_id) 138 { 139 int cpu = smp_processor_id(); 140 141 kvmppc_set_host_ipi(cpu, 0); 142 opal_int_set_mfrr(get_hard_smp_processor_id(cpu), 0xff); 143 144 return smp_ipi_demux(); 145 } 146 147 /* 148 * Called when an interrupt is received on an off-line CPU to 149 * clear the interrupt, so that the CPU can go back to nap mode. 150 */ 151 void icp_opal_flush_interrupt(void) 152 { 153 unsigned int xirr; 154 unsigned int vec; 155 156 do { 157 xirr = icp_opal_get_xirr(); 158 vec = xirr & 0x00ffffff; 159 if (vec == XICS_IRQ_SPURIOUS) 160 break; 161 if (vec == XICS_IPI) { 162 /* Clear pending IPI */ 163 int cpu = smp_processor_id(); 164 kvmppc_set_host_ipi(cpu, 0); 165 opal_int_set_mfrr(get_hard_smp_processor_id(cpu), 0xff); 166 } else { 167 pr_err("XICS: hw interrupt 0x%x to offline cpu, " 168 "disabling\n", vec); 169 xics_mask_unknown_vec(vec); 170 } 171 172 /* EOI the interrupt */ 173 } while (opal_int_eoi(xirr) > 0); 174 } 175 176 #endif /* CONFIG_SMP */ 177 178 static const struct icp_ops icp_opal_ops = { 179 .get_irq = icp_opal_get_irq, 180 .eoi = icp_opal_eoi, 181 .set_priority = icp_opal_set_cpu_priority, 182 .teardown_cpu = icp_opal_teardown_cpu, 183 .flush_ipi = icp_opal_flush_ipi, 184 #ifdef CONFIG_SMP 185 .ipi_action = icp_opal_ipi_action, 186 .cause_ipi = icp_opal_cause_ipi, 187 #endif 188 }; 189 190 int icp_opal_init(void) 191 { 192 struct device_node *np; 193 194 np = of_find_compatible_node(NULL, NULL, "ibm,opal-intc"); 195 if (!np) 196 return -ENODEV; 197 198 icp_ops = &icp_opal_ops; 199 200 printk("XICS: Using OPAL ICP fallbacks\n"); 201 202 return 0; 203 } 204 205