1 /* 2 * arch/powerpc/kernel/mpic.c 3 * 4 * Driver for interrupt controllers following the OpenPIC standard, the 5 * common implementation beeing IBM's MPIC. This driver also can deal 6 * with various broken implementations of this HW. 7 * 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file COPYING in the main directory of this archive 12 * for more details. 13 */ 14 15 #undef DEBUG 16 #undef DEBUG_IPI 17 #undef DEBUG_IRQ 18 #undef DEBUG_LOW 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/irq.h> 24 #include <linux/smp.h> 25 #include <linux/interrupt.h> 26 #include <linux/bootmem.h> 27 #include <linux/spinlock.h> 28 #include <linux/pci.h> 29 30 #include <asm/ptrace.h> 31 #include <asm/signal.h> 32 #include <asm/io.h> 33 #include <asm/pgtable.h> 34 #include <asm/irq.h> 35 #include <asm/machdep.h> 36 #include <asm/mpic.h> 37 #include <asm/smp.h> 38 39 #include "mpic.h" 40 41 #ifdef DEBUG 42 #define DBG(fmt...) printk(fmt) 43 #else 44 #define DBG(fmt...) 45 #endif 46 47 static struct mpic *mpics; 48 static struct mpic *mpic_primary; 49 static DEFINE_SPINLOCK(mpic_lock); 50 51 #ifdef CONFIG_PPC32 /* XXX for now */ 52 #ifdef CONFIG_IRQ_ALL_CPUS 53 #define distribute_irqs (1) 54 #else 55 #define distribute_irqs (0) 56 #endif 57 #endif 58 59 #ifdef CONFIG_MPIC_WEIRD 60 static u32 mpic_infos[][MPIC_IDX_END] = { 61 [0] = { /* Original OpenPIC compatible MPIC */ 62 MPIC_GREG_BASE, 63 MPIC_GREG_FEATURE_0, 64 MPIC_GREG_GLOBAL_CONF_0, 65 MPIC_GREG_VENDOR_ID, 66 MPIC_GREG_IPI_VECTOR_PRI_0, 67 MPIC_GREG_IPI_STRIDE, 68 MPIC_GREG_SPURIOUS, 69 MPIC_GREG_TIMER_FREQ, 70 71 MPIC_TIMER_BASE, 72 MPIC_TIMER_STRIDE, 73 MPIC_TIMER_CURRENT_CNT, 74 MPIC_TIMER_BASE_CNT, 75 MPIC_TIMER_VECTOR_PRI, 76 MPIC_TIMER_DESTINATION, 77 78 MPIC_CPU_BASE, 79 MPIC_CPU_STRIDE, 80 MPIC_CPU_IPI_DISPATCH_0, 81 MPIC_CPU_IPI_DISPATCH_STRIDE, 82 MPIC_CPU_CURRENT_TASK_PRI, 83 MPIC_CPU_WHOAMI, 84 MPIC_CPU_INTACK, 85 MPIC_CPU_EOI, 86 MPIC_CPU_MCACK, 87 88 MPIC_IRQ_BASE, 89 MPIC_IRQ_STRIDE, 90 MPIC_IRQ_VECTOR_PRI, 91 MPIC_VECPRI_VECTOR_MASK, 92 MPIC_VECPRI_POLARITY_POSITIVE, 93 MPIC_VECPRI_POLARITY_NEGATIVE, 94 MPIC_VECPRI_SENSE_LEVEL, 95 MPIC_VECPRI_SENSE_EDGE, 96 MPIC_VECPRI_POLARITY_MASK, 97 MPIC_VECPRI_SENSE_MASK, 98 MPIC_IRQ_DESTINATION 99 }, 100 [1] = { /* Tsi108/109 PIC */ 101 TSI108_GREG_BASE, 102 TSI108_GREG_FEATURE_0, 103 TSI108_GREG_GLOBAL_CONF_0, 104 TSI108_GREG_VENDOR_ID, 105 TSI108_GREG_IPI_VECTOR_PRI_0, 106 TSI108_GREG_IPI_STRIDE, 107 TSI108_GREG_SPURIOUS, 108 TSI108_GREG_TIMER_FREQ, 109 110 TSI108_TIMER_BASE, 111 TSI108_TIMER_STRIDE, 112 TSI108_TIMER_CURRENT_CNT, 113 TSI108_TIMER_BASE_CNT, 114 TSI108_TIMER_VECTOR_PRI, 115 TSI108_TIMER_DESTINATION, 116 117 TSI108_CPU_BASE, 118 TSI108_CPU_STRIDE, 119 TSI108_CPU_IPI_DISPATCH_0, 120 TSI108_CPU_IPI_DISPATCH_STRIDE, 121 TSI108_CPU_CURRENT_TASK_PRI, 122 TSI108_CPU_WHOAMI, 123 TSI108_CPU_INTACK, 124 TSI108_CPU_EOI, 125 TSI108_CPU_MCACK, 126 127 TSI108_IRQ_BASE, 128 TSI108_IRQ_STRIDE, 129 TSI108_IRQ_VECTOR_PRI, 130 TSI108_VECPRI_VECTOR_MASK, 131 TSI108_VECPRI_POLARITY_POSITIVE, 132 TSI108_VECPRI_POLARITY_NEGATIVE, 133 TSI108_VECPRI_SENSE_LEVEL, 134 TSI108_VECPRI_SENSE_EDGE, 135 TSI108_VECPRI_POLARITY_MASK, 136 TSI108_VECPRI_SENSE_MASK, 137 TSI108_IRQ_DESTINATION 138 }, 139 }; 140 141 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 142 143 #else /* CONFIG_MPIC_WEIRD */ 144 145 #define MPIC_INFO(name) MPIC_##name 146 147 #endif /* CONFIG_MPIC_WEIRD */ 148 149 /* 150 * Register accessor functions 151 */ 152 153 154 static inline u32 _mpic_read(enum mpic_reg_type type, 155 struct mpic_reg_bank *rb, 156 unsigned int reg) 157 { 158 switch(type) { 159 #ifdef CONFIG_PPC_DCR 160 case mpic_access_dcr: 161 return dcr_read(rb->dhost, reg); 162 #endif 163 case mpic_access_mmio_be: 164 return in_be32(rb->base + (reg >> 2)); 165 case mpic_access_mmio_le: 166 default: 167 return in_le32(rb->base + (reg >> 2)); 168 } 169 } 170 171 static inline void _mpic_write(enum mpic_reg_type type, 172 struct mpic_reg_bank *rb, 173 unsigned int reg, u32 value) 174 { 175 switch(type) { 176 #ifdef CONFIG_PPC_DCR 177 case mpic_access_dcr: 178 dcr_write(rb->dhost, reg, value); 179 break; 180 #endif 181 case mpic_access_mmio_be: 182 out_be32(rb->base + (reg >> 2), value); 183 break; 184 case mpic_access_mmio_le: 185 default: 186 out_le32(rb->base + (reg >> 2), value); 187 break; 188 } 189 } 190 191 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 192 { 193 enum mpic_reg_type type = mpic->reg_type; 194 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 195 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 196 197 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 198 type = mpic_access_mmio_be; 199 return _mpic_read(type, &mpic->gregs, offset); 200 } 201 202 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 203 { 204 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 205 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 206 207 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 208 } 209 210 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 211 { 212 unsigned int cpu = 0; 213 214 if (mpic->flags & MPIC_PRIMARY) 215 cpu = hard_smp_processor_id(); 216 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 217 } 218 219 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 220 { 221 unsigned int cpu = 0; 222 223 if (mpic->flags & MPIC_PRIMARY) 224 cpu = hard_smp_processor_id(); 225 226 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 227 } 228 229 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 230 { 231 unsigned int isu = src_no >> mpic->isu_shift; 232 unsigned int idx = src_no & mpic->isu_mask; 233 234 #ifdef CONFIG_MPIC_BROKEN_REGREAD 235 if (reg == 0) 236 return mpic->isu_reg0_shadow[idx]; 237 else 238 #endif 239 return _mpic_read(mpic->reg_type, &mpic->isus[isu], 240 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 241 } 242 243 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 244 unsigned int reg, u32 value) 245 { 246 unsigned int isu = src_no >> mpic->isu_shift; 247 unsigned int idx = src_no & mpic->isu_mask; 248 249 _mpic_write(mpic->reg_type, &mpic->isus[isu], 250 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 251 252 #ifdef CONFIG_MPIC_BROKEN_REGREAD 253 if (reg == 0) 254 mpic->isu_reg0_shadow[idx] = value; 255 #endif 256 } 257 258 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 259 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 260 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 261 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 262 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 263 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 264 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 265 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 266 267 268 /* 269 * Low level utility functions 270 */ 271 272 273 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, 274 struct mpic_reg_bank *rb, unsigned int offset, 275 unsigned int size) 276 { 277 rb->base = ioremap(phys_addr + offset, size); 278 BUG_ON(rb->base == NULL); 279 } 280 281 #ifdef CONFIG_PPC_DCR 282 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, 283 unsigned int offset, unsigned int size) 284 { 285 const u32 *dbasep; 286 287 dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); 288 289 rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); 290 BUG_ON(!DCR_MAP_OK(rb->dhost)); 291 } 292 293 static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, 294 struct mpic_reg_bank *rb, unsigned int offset, 295 unsigned int size) 296 { 297 if (mpic->flags & MPIC_USES_DCR) 298 _mpic_map_dcr(mpic, rb, offset, size); 299 else 300 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 301 } 302 #else /* CONFIG_PPC_DCR */ 303 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 304 #endif /* !CONFIG_PPC_DCR */ 305 306 307 308 /* Check if we have one of those nice broken MPICs with a flipped endian on 309 * reads from IPI registers 310 */ 311 static void __init mpic_test_broken_ipi(struct mpic *mpic) 312 { 313 u32 r; 314 315 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 316 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 317 318 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 319 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 320 mpic->flags |= MPIC_BROKEN_IPI; 321 } 322 } 323 324 #ifdef CONFIG_MPIC_U3_HT_IRQS 325 326 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 327 * to force the edge setting on the MPIC and do the ack workaround. 328 */ 329 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 330 { 331 if (source >= 128 || !mpic->fixups) 332 return 0; 333 return mpic->fixups[source].base != NULL; 334 } 335 336 337 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 338 { 339 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 340 341 if (fixup->applebase) { 342 unsigned int soff = (fixup->index >> 3) & ~3; 343 unsigned int mask = 1U << (fixup->index & 0x1f); 344 writel(mask, fixup->applebase + soff); 345 } else { 346 spin_lock(&mpic->fixup_lock); 347 writeb(0x11 + 2 * fixup->index, fixup->base + 2); 348 writel(fixup->data, fixup->base + 4); 349 spin_unlock(&mpic->fixup_lock); 350 } 351 } 352 353 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 354 unsigned int irqflags) 355 { 356 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 357 unsigned long flags; 358 u32 tmp; 359 360 if (fixup->base == NULL) 361 return; 362 363 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 364 source, irqflags, fixup->index); 365 spin_lock_irqsave(&mpic->fixup_lock, flags); 366 /* Enable and configure */ 367 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 368 tmp = readl(fixup->base + 4); 369 tmp &= ~(0x23U); 370 if (irqflags & IRQ_LEVEL) 371 tmp |= 0x22; 372 writel(tmp, fixup->base + 4); 373 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 374 375 #ifdef CONFIG_PM 376 /* use the lowest bit inverted to the actual HW, 377 * set if this fixup was enabled, clear otherwise */ 378 mpic->save_data[source].fixup_data = tmp | 1; 379 #endif 380 } 381 382 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 383 unsigned int irqflags) 384 { 385 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 386 unsigned long flags; 387 u32 tmp; 388 389 if (fixup->base == NULL) 390 return; 391 392 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 393 394 /* Disable */ 395 spin_lock_irqsave(&mpic->fixup_lock, flags); 396 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 397 tmp = readl(fixup->base + 4); 398 tmp |= 1; 399 writel(tmp, fixup->base + 4); 400 spin_unlock_irqrestore(&mpic->fixup_lock, flags); 401 402 #ifdef CONFIG_PM 403 /* use the lowest bit inverted to the actual HW, 404 * set if this fixup was enabled, clear otherwise */ 405 mpic->save_data[source].fixup_data = tmp & ~1; 406 #endif 407 } 408 409 #ifdef CONFIG_PCI_MSI 410 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 411 unsigned int devfn) 412 { 413 u8 __iomem *base; 414 u8 pos, flags; 415 u64 addr = 0; 416 417 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 418 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 419 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 420 if (id == PCI_CAP_ID_HT) { 421 id = readb(devbase + pos + 3); 422 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 423 break; 424 } 425 } 426 427 if (pos == 0) 428 return; 429 430 base = devbase + pos; 431 432 flags = readb(base + HT_MSI_FLAGS); 433 if (!(flags & HT_MSI_FLAGS_FIXED)) { 434 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 435 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 436 } 437 438 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", 439 PCI_SLOT(devfn), PCI_FUNC(devfn), 440 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 441 442 if (!(flags & HT_MSI_FLAGS_ENABLE)) 443 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 444 } 445 #else 446 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 447 unsigned int devfn) 448 { 449 return; 450 } 451 #endif 452 453 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 454 unsigned int devfn, u32 vdid) 455 { 456 int i, irq, n; 457 u8 __iomem *base; 458 u32 tmp; 459 u8 pos; 460 461 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 462 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 463 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 464 if (id == PCI_CAP_ID_HT) { 465 id = readb(devbase + pos + 3); 466 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 467 break; 468 } 469 } 470 if (pos == 0) 471 return; 472 473 base = devbase + pos; 474 writeb(0x01, base + 2); 475 n = (readl(base + 4) >> 16) & 0xff; 476 477 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 478 " has %d irqs\n", 479 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 480 481 for (i = 0; i <= n; i++) { 482 writeb(0x10 + 2 * i, base + 2); 483 tmp = readl(base + 4); 484 irq = (tmp >> 16) & 0xff; 485 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 486 /* mask it , will be unmasked later */ 487 tmp |= 0x1; 488 writel(tmp, base + 4); 489 mpic->fixups[irq].index = i; 490 mpic->fixups[irq].base = base; 491 /* Apple HT PIC has a non-standard way of doing EOIs */ 492 if ((vdid & 0xffff) == 0x106b) 493 mpic->fixups[irq].applebase = devbase + 0x60; 494 else 495 mpic->fixups[irq].applebase = NULL; 496 writeb(0x11 + 2 * i, base + 2); 497 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 498 } 499 } 500 501 502 static void __init mpic_scan_ht_pics(struct mpic *mpic) 503 { 504 unsigned int devfn; 505 u8 __iomem *cfgspace; 506 507 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 508 509 /* Allocate fixups array */ 510 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); 511 BUG_ON(mpic->fixups == NULL); 512 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); 513 514 /* Init spinlock */ 515 spin_lock_init(&mpic->fixup_lock); 516 517 /* Map U3 config space. We assume all IO-APICs are on the primary bus 518 * so we only need to map 64kB. 519 */ 520 cfgspace = ioremap(0xf2000000, 0x10000); 521 BUG_ON(cfgspace == NULL); 522 523 /* Now we scan all slots. We do a very quick scan, we read the header 524 * type, vendor ID and device ID only, that's plenty enough 525 */ 526 for (devfn = 0; devfn < 0x100; devfn++) { 527 u8 __iomem *devbase = cfgspace + (devfn << 8); 528 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 529 u32 l = readl(devbase + PCI_VENDOR_ID); 530 u16 s; 531 532 DBG("devfn %x, l: %x\n", devfn, l); 533 534 /* If no device, skip */ 535 if (l == 0xffffffff || l == 0x00000000 || 536 l == 0x0000ffff || l == 0xffff0000) 537 goto next; 538 /* Check if is supports capability lists */ 539 s = readw(devbase + PCI_STATUS); 540 if (!(s & PCI_STATUS_CAP_LIST)) 541 goto next; 542 543 mpic_scan_ht_pic(mpic, devbase, devfn, l); 544 mpic_scan_ht_msi(mpic, devbase, devfn); 545 546 next: 547 /* next device, if function 0 */ 548 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 549 devfn += 7; 550 } 551 } 552 553 #else /* CONFIG_MPIC_U3_HT_IRQS */ 554 555 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 556 { 557 return 0; 558 } 559 560 static void __init mpic_scan_ht_pics(struct mpic *mpic) 561 { 562 } 563 564 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 565 566 #ifdef CONFIG_SMP 567 static int irq_choose_cpu(unsigned int virt_irq) 568 { 569 cpumask_t mask; 570 int cpuid; 571 572 cpumask_copy(&mask, irq_desc[virt_irq].affinity); 573 if (cpus_equal(mask, CPU_MASK_ALL)) { 574 static int irq_rover; 575 static DEFINE_SPINLOCK(irq_rover_lock); 576 unsigned long flags; 577 578 /* Round-robin distribution... */ 579 do_round_robin: 580 spin_lock_irqsave(&irq_rover_lock, flags); 581 582 while (!cpu_online(irq_rover)) { 583 if (++irq_rover >= NR_CPUS) 584 irq_rover = 0; 585 } 586 cpuid = irq_rover; 587 do { 588 if (++irq_rover >= NR_CPUS) 589 irq_rover = 0; 590 } while (!cpu_online(irq_rover)); 591 592 spin_unlock_irqrestore(&irq_rover_lock, flags); 593 } else { 594 cpumask_t tmp; 595 596 cpus_and(tmp, cpu_online_map, mask); 597 598 if (cpus_empty(tmp)) 599 goto do_round_robin; 600 601 cpuid = first_cpu(tmp); 602 } 603 604 return get_hard_smp_processor_id(cpuid); 605 } 606 #else 607 static int irq_choose_cpu(unsigned int virt_irq) 608 { 609 return hard_smp_processor_id(); 610 } 611 #endif 612 613 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 614 615 /* Find an mpic associated with a given linux interrupt */ 616 static struct mpic *mpic_find(unsigned int irq) 617 { 618 if (irq < NUM_ISA_INTERRUPTS) 619 return NULL; 620 621 return irq_desc[irq].chip_data; 622 } 623 624 /* Determine if the linux irq is an IPI */ 625 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) 626 { 627 unsigned int src = mpic_irq_to_hw(irq); 628 629 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); 630 } 631 632 633 /* Convert a cpu mask from logical to physical cpu numbers. */ 634 static inline u32 mpic_physmask(u32 cpumask) 635 { 636 int i; 637 u32 mask = 0; 638 639 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 640 mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 641 return mask; 642 } 643 644 #ifdef CONFIG_SMP 645 /* Get the mpic structure from the IPI number */ 646 static inline struct mpic * mpic_from_ipi(unsigned int ipi) 647 { 648 return irq_desc[ipi].chip_data; 649 } 650 #endif 651 652 /* Get the mpic structure from the irq number */ 653 static inline struct mpic * mpic_from_irq(unsigned int irq) 654 { 655 return irq_desc[irq].chip_data; 656 } 657 658 /* Send an EOI */ 659 static inline void mpic_eoi(struct mpic *mpic) 660 { 661 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 662 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 663 } 664 665 /* 666 * Linux descriptor level callbacks 667 */ 668 669 670 void mpic_unmask_irq(unsigned int irq) 671 { 672 unsigned int loops = 100000; 673 struct mpic *mpic = mpic_from_irq(irq); 674 unsigned int src = mpic_irq_to_hw(irq); 675 676 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 677 678 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 679 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 680 ~MPIC_VECPRI_MASK); 681 /* make sure mask gets to controller before we return to user */ 682 do { 683 if (!loops--) { 684 printk(KERN_ERR "mpic_enable_irq timeout\n"); 685 break; 686 } 687 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 688 } 689 690 void mpic_mask_irq(unsigned int irq) 691 { 692 unsigned int loops = 100000; 693 struct mpic *mpic = mpic_from_irq(irq); 694 unsigned int src = mpic_irq_to_hw(irq); 695 696 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 697 698 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 699 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 700 MPIC_VECPRI_MASK); 701 702 /* make sure mask gets to controller before we return to user */ 703 do { 704 if (!loops--) { 705 printk(KERN_ERR "mpic_enable_irq timeout\n"); 706 break; 707 } 708 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 709 } 710 711 void mpic_end_irq(unsigned int irq) 712 { 713 struct mpic *mpic = mpic_from_irq(irq); 714 715 #ifdef DEBUG_IRQ 716 DBG("%s: end_irq: %d\n", mpic->name, irq); 717 #endif 718 /* We always EOI on end_irq() even for edge interrupts since that 719 * should only lower the priority, the MPIC should have properly 720 * latched another edge interrupt coming in anyway 721 */ 722 723 mpic_eoi(mpic); 724 } 725 726 #ifdef CONFIG_MPIC_U3_HT_IRQS 727 728 static void mpic_unmask_ht_irq(unsigned int irq) 729 { 730 struct mpic *mpic = mpic_from_irq(irq); 731 unsigned int src = mpic_irq_to_hw(irq); 732 733 mpic_unmask_irq(irq); 734 735 if (irq_desc[irq].status & IRQ_LEVEL) 736 mpic_ht_end_irq(mpic, src); 737 } 738 739 static unsigned int mpic_startup_ht_irq(unsigned int irq) 740 { 741 struct mpic *mpic = mpic_from_irq(irq); 742 unsigned int src = mpic_irq_to_hw(irq); 743 744 mpic_unmask_irq(irq); 745 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); 746 747 return 0; 748 } 749 750 static void mpic_shutdown_ht_irq(unsigned int irq) 751 { 752 struct mpic *mpic = mpic_from_irq(irq); 753 unsigned int src = mpic_irq_to_hw(irq); 754 755 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); 756 mpic_mask_irq(irq); 757 } 758 759 static void mpic_end_ht_irq(unsigned int irq) 760 { 761 struct mpic *mpic = mpic_from_irq(irq); 762 unsigned int src = mpic_irq_to_hw(irq); 763 764 #ifdef DEBUG_IRQ 765 DBG("%s: end_irq: %d\n", mpic->name, irq); 766 #endif 767 /* We always EOI on end_irq() even for edge interrupts since that 768 * should only lower the priority, the MPIC should have properly 769 * latched another edge interrupt coming in anyway 770 */ 771 772 if (irq_desc[irq].status & IRQ_LEVEL) 773 mpic_ht_end_irq(mpic, src); 774 mpic_eoi(mpic); 775 } 776 #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 777 778 #ifdef CONFIG_SMP 779 780 static void mpic_unmask_ipi(unsigned int irq) 781 { 782 struct mpic *mpic = mpic_from_ipi(irq); 783 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 784 785 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 786 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 787 } 788 789 static void mpic_mask_ipi(unsigned int irq) 790 { 791 /* NEVER disable an IPI... that's just plain wrong! */ 792 } 793 794 static void mpic_end_ipi(unsigned int irq) 795 { 796 struct mpic *mpic = mpic_from_ipi(irq); 797 798 /* 799 * IPIs are marked IRQ_PER_CPU. This has the side effect of 800 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 801 * applying to them. We EOI them late to avoid re-entering. 802 * We mark IPI's with IRQF_DISABLED as they must run with 803 * irqs disabled. 804 */ 805 mpic_eoi(mpic); 806 } 807 808 #endif /* CONFIG_SMP */ 809 810 int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) 811 { 812 struct mpic *mpic = mpic_from_irq(irq); 813 unsigned int src = mpic_irq_to_hw(irq); 814 815 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { 816 int cpuid = irq_choose_cpu(irq); 817 818 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 819 } else { 820 cpumask_t tmp; 821 822 cpumask_and(&tmp, cpumask, cpu_online_mask); 823 824 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 825 mpic_physmask(cpus_addr(tmp)[0])); 826 } 827 828 return 0; 829 } 830 831 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 832 { 833 /* Now convert sense value */ 834 switch(type & IRQ_TYPE_SENSE_MASK) { 835 case IRQ_TYPE_EDGE_RISING: 836 return MPIC_INFO(VECPRI_SENSE_EDGE) | 837 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 838 case IRQ_TYPE_EDGE_FALLING: 839 case IRQ_TYPE_EDGE_BOTH: 840 return MPIC_INFO(VECPRI_SENSE_EDGE) | 841 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 842 case IRQ_TYPE_LEVEL_HIGH: 843 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 844 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 845 case IRQ_TYPE_LEVEL_LOW: 846 default: 847 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 848 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 849 } 850 } 851 852 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 853 { 854 struct mpic *mpic = mpic_from_irq(virq); 855 unsigned int src = mpic_irq_to_hw(virq); 856 struct irq_desc *desc = get_irq_desc(virq); 857 unsigned int vecpri, vold, vnew; 858 859 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 860 mpic, virq, src, flow_type); 861 862 if (src >= mpic->irq_count) 863 return -EINVAL; 864 865 if (flow_type == IRQ_TYPE_NONE) 866 if (mpic->senses && src < mpic->senses_count) 867 flow_type = mpic->senses[src]; 868 if (flow_type == IRQ_TYPE_NONE) 869 flow_type = IRQ_TYPE_LEVEL_LOW; 870 871 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 872 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 873 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 874 desc->status |= IRQ_LEVEL; 875 876 if (mpic_is_ht_interrupt(mpic, src)) 877 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 878 MPIC_VECPRI_SENSE_EDGE; 879 else 880 vecpri = mpic_type_to_vecpri(mpic, flow_type); 881 882 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 883 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 884 MPIC_INFO(VECPRI_SENSE_MASK)); 885 vnew |= vecpri; 886 if (vold != vnew) 887 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 888 889 return 0; 890 } 891 892 void mpic_set_vector(unsigned int virq, unsigned int vector) 893 { 894 struct mpic *mpic = mpic_from_irq(virq); 895 unsigned int src = mpic_irq_to_hw(virq); 896 unsigned int vecpri; 897 898 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", 899 mpic, virq, src, vector); 900 901 if (src >= mpic->irq_count) 902 return; 903 904 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 905 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); 906 vecpri |= vector; 907 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 908 } 909 910 static struct irq_chip mpic_irq_chip = { 911 .mask = mpic_mask_irq, 912 .unmask = mpic_unmask_irq, 913 .eoi = mpic_end_irq, 914 .set_type = mpic_set_irq_type, 915 }; 916 917 #ifdef CONFIG_SMP 918 static struct irq_chip mpic_ipi_chip = { 919 .mask = mpic_mask_ipi, 920 .unmask = mpic_unmask_ipi, 921 .eoi = mpic_end_ipi, 922 }; 923 #endif /* CONFIG_SMP */ 924 925 #ifdef CONFIG_MPIC_U3_HT_IRQS 926 static struct irq_chip mpic_irq_ht_chip = { 927 .startup = mpic_startup_ht_irq, 928 .shutdown = mpic_shutdown_ht_irq, 929 .mask = mpic_mask_irq, 930 .unmask = mpic_unmask_ht_irq, 931 .eoi = mpic_end_ht_irq, 932 .set_type = mpic_set_irq_type, 933 }; 934 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 935 936 937 static int mpic_host_match(struct irq_host *h, struct device_node *node) 938 { 939 /* Exact match, unless mpic node is NULL */ 940 return h->of_node == NULL || h->of_node == node; 941 } 942 943 static int mpic_host_map(struct irq_host *h, unsigned int virq, 944 irq_hw_number_t hw) 945 { 946 struct mpic *mpic = h->host_data; 947 struct irq_chip *chip; 948 949 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 950 951 if (hw == mpic->spurious_vec) 952 return -EINVAL; 953 if (mpic->protected && test_bit(hw, mpic->protected)) 954 return -EINVAL; 955 956 #ifdef CONFIG_SMP 957 else if (hw >= mpic->ipi_vecs[0]) { 958 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 959 960 DBG("mpic: mapping as IPI\n"); 961 set_irq_chip_data(virq, mpic); 962 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 963 handle_percpu_irq); 964 return 0; 965 } 966 #endif /* CONFIG_SMP */ 967 968 if (hw >= mpic->irq_count) 969 return -EINVAL; 970 971 mpic_msi_reserve_hwirq(mpic, hw); 972 973 /* Default chip */ 974 chip = &mpic->hc_irq; 975 976 #ifdef CONFIG_MPIC_U3_HT_IRQS 977 /* Check for HT interrupts, override vecpri */ 978 if (mpic_is_ht_interrupt(mpic, hw)) 979 chip = &mpic->hc_ht_irq; 980 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 981 982 DBG("mpic: mapping to irq chip @%p\n", chip); 983 984 set_irq_chip_data(virq, mpic); 985 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 986 987 /* Set default irq type */ 988 set_irq_type(virq, IRQ_TYPE_NONE); 989 990 return 0; 991 } 992 993 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 994 u32 *intspec, unsigned int intsize, 995 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 996 997 { 998 static unsigned char map_mpic_senses[4] = { 999 IRQ_TYPE_EDGE_RISING, 1000 IRQ_TYPE_LEVEL_LOW, 1001 IRQ_TYPE_LEVEL_HIGH, 1002 IRQ_TYPE_EDGE_FALLING, 1003 }; 1004 1005 *out_hwirq = intspec[0]; 1006 if (intsize > 1) { 1007 u32 mask = 0x3; 1008 1009 /* Apple invented a new race of encoding on machines with 1010 * an HT APIC. They encode, among others, the index within 1011 * the HT APIC. We don't care about it here since thankfully, 1012 * it appears that they have the APIC already properly 1013 * configured, and thus our current fixup code that reads the 1014 * APIC config works fine. However, we still need to mask out 1015 * bits in the specifier to make sure we only get bit 0 which 1016 * is the level/edge bit (the only sense bit exposed by Apple), 1017 * as their bit 1 means something else. 1018 */ 1019 if (machine_is(powermac)) 1020 mask = 0x1; 1021 *out_flags = map_mpic_senses[intspec[1] & mask]; 1022 } else 1023 *out_flags = IRQ_TYPE_NONE; 1024 1025 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 1026 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 1027 1028 return 0; 1029 } 1030 1031 static struct irq_host_ops mpic_host_ops = { 1032 .match = mpic_host_match, 1033 .map = mpic_host_map, 1034 .xlate = mpic_host_xlate, 1035 }; 1036 1037 /* 1038 * Exported functions 1039 */ 1040 1041 struct mpic * __init mpic_alloc(struct device_node *node, 1042 phys_addr_t phys_addr, 1043 unsigned int flags, 1044 unsigned int isu_size, 1045 unsigned int irq_count, 1046 const char *name) 1047 { 1048 struct mpic *mpic; 1049 u32 greg_feature; 1050 const char *vers; 1051 int i; 1052 int intvec_top; 1053 u64 paddr = phys_addr; 1054 1055 mpic = alloc_bootmem(sizeof(struct mpic)); 1056 if (mpic == NULL) 1057 return NULL; 1058 1059 memset(mpic, 0, sizeof(struct mpic)); 1060 mpic->name = name; 1061 1062 mpic->hc_irq = mpic_irq_chip; 1063 mpic->hc_irq.typename = name; 1064 if (flags & MPIC_PRIMARY) 1065 mpic->hc_irq.set_affinity = mpic_set_affinity; 1066 #ifdef CONFIG_MPIC_U3_HT_IRQS 1067 mpic->hc_ht_irq = mpic_irq_ht_chip; 1068 mpic->hc_ht_irq.typename = name; 1069 if (flags & MPIC_PRIMARY) 1070 mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 1071 #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1072 1073 #ifdef CONFIG_SMP 1074 mpic->hc_ipi = mpic_ipi_chip; 1075 mpic->hc_ipi.typename = name; 1076 #endif /* CONFIG_SMP */ 1077 1078 mpic->flags = flags; 1079 mpic->isu_size = isu_size; 1080 mpic->irq_count = irq_count; 1081 mpic->num_sources = 0; /* so far */ 1082 1083 if (flags & MPIC_LARGE_VECTORS) 1084 intvec_top = 2047; 1085 else 1086 intvec_top = 255; 1087 1088 mpic->timer_vecs[0] = intvec_top - 8; 1089 mpic->timer_vecs[1] = intvec_top - 7; 1090 mpic->timer_vecs[2] = intvec_top - 6; 1091 mpic->timer_vecs[3] = intvec_top - 5; 1092 mpic->ipi_vecs[0] = intvec_top - 4; 1093 mpic->ipi_vecs[1] = intvec_top - 3; 1094 mpic->ipi_vecs[2] = intvec_top - 2; 1095 mpic->ipi_vecs[3] = intvec_top - 1; 1096 mpic->spurious_vec = intvec_top; 1097 1098 /* Check for "big-endian" in device-tree */ 1099 if (node && of_get_property(node, "big-endian", NULL) != NULL) 1100 mpic->flags |= MPIC_BIG_ENDIAN; 1101 1102 /* Look for protected sources */ 1103 if (node) { 1104 int psize; 1105 unsigned int bits, mapsize; 1106 const u32 *psrc = 1107 of_get_property(node, "protected-sources", &psize); 1108 if (psrc) { 1109 psize /= 4; 1110 bits = intvec_top + 1; 1111 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); 1112 mpic->protected = alloc_bootmem(mapsize); 1113 BUG_ON(mpic->protected == NULL); 1114 memset(mpic->protected, 0, mapsize); 1115 for (i = 0; i < psize; i++) { 1116 if (psrc[i] > intvec_top) 1117 continue; 1118 __set_bit(psrc[i], mpic->protected); 1119 } 1120 } 1121 } 1122 1123 #ifdef CONFIG_MPIC_WEIRD 1124 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 1125 #endif 1126 1127 /* default register type */ 1128 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 1129 mpic_access_mmio_be : mpic_access_mmio_le; 1130 1131 /* If no physical address is passed in, a device-node is mandatory */ 1132 BUG_ON(paddr == 0 && node == NULL); 1133 1134 /* If no physical address passed in, check if it's dcr based */ 1135 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { 1136 #ifdef CONFIG_PPC_DCR 1137 mpic->flags |= MPIC_USES_DCR; 1138 mpic->reg_type = mpic_access_dcr; 1139 #else 1140 BUG(); 1141 #endif /* CONFIG_PPC_DCR */ 1142 } 1143 1144 /* If the MPIC is not DCR based, and no physical address was passed 1145 * in, try to obtain one 1146 */ 1147 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1148 const u32 *reg = of_get_property(node, "reg", NULL); 1149 BUG_ON(reg == NULL); 1150 paddr = of_translate_address(node, reg); 1151 BUG_ON(paddr == OF_BAD_ADDR); 1152 } 1153 1154 /* Map the global registers */ 1155 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1156 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1157 1158 /* Reset */ 1159 if (flags & MPIC_WANTS_RESET) { 1160 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1161 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1162 | MPIC_GREG_GCONF_RESET); 1163 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1164 & MPIC_GREG_GCONF_RESET) 1165 mb(); 1166 } 1167 1168 /* CoreInt */ 1169 if (flags & MPIC_ENABLE_COREINT) 1170 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1171 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1172 | MPIC_GREG_GCONF_COREINT); 1173 1174 if (flags & MPIC_ENABLE_MCK) 1175 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1176 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1177 | MPIC_GREG_GCONF_MCK); 1178 1179 /* Read feature register, calculate num CPUs and, for non-ISU 1180 * MPICs, num sources as well. On ISU MPICs, sources are counted 1181 * as ISUs are added 1182 */ 1183 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1184 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) 1185 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 1186 if (isu_size == 0) { 1187 if (flags & MPIC_BROKEN_FRR_NIRQS) 1188 mpic->num_sources = mpic->irq_count; 1189 else 1190 mpic->num_sources = 1191 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) 1192 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 1193 } 1194 1195 /* Map the per-CPU registers */ 1196 for (i = 0; i < mpic->num_cpus; i++) { 1197 mpic_map(mpic, paddr, &mpic->cpuregs[i], 1198 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1199 0x1000); 1200 } 1201 1202 /* Initialize main ISU if none provided */ 1203 if (mpic->isu_size == 0) { 1204 mpic->isu_size = mpic->num_sources; 1205 mpic_map(mpic, paddr, &mpic->isus[0], 1206 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1207 } 1208 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1209 mpic->isu_mask = (1 << mpic->isu_shift) - 1; 1210 1211 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1212 isu_size ? isu_size : mpic->num_sources, 1213 &mpic_host_ops, 1214 flags & MPIC_LARGE_VECTORS ? 2048 : 256); 1215 if (mpic->irqhost == NULL) 1216 return NULL; 1217 1218 mpic->irqhost->host_data = mpic; 1219 1220 /* Display version */ 1221 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { 1222 case 1: 1223 vers = "1.0"; 1224 break; 1225 case 2: 1226 vers = "1.2"; 1227 break; 1228 case 3: 1229 vers = "1.3"; 1230 break; 1231 default: 1232 vers = "<unknown>"; 1233 break; 1234 } 1235 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1236 " max %d CPUs\n", 1237 name, vers, (unsigned long long)paddr, mpic->num_cpus); 1238 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1239 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 1240 1241 mpic->next = mpics; 1242 mpics = mpic; 1243 1244 if (flags & MPIC_PRIMARY) { 1245 mpic_primary = mpic; 1246 irq_set_default_host(mpic->irqhost); 1247 } 1248 1249 return mpic; 1250 } 1251 1252 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1253 phys_addr_t paddr) 1254 { 1255 unsigned int isu_first = isu_num * mpic->isu_size; 1256 1257 BUG_ON(isu_num >= MPIC_MAX_ISU); 1258 1259 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, 1260 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1261 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1262 mpic->num_sources = isu_first + mpic->isu_size; 1263 } 1264 1265 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 1266 { 1267 mpic->senses = senses; 1268 mpic->senses_count = count; 1269 } 1270 1271 void __init mpic_init(struct mpic *mpic) 1272 { 1273 int i; 1274 int cpu; 1275 1276 BUG_ON(mpic->num_sources == 0); 1277 1278 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1279 1280 /* Set current processor priority to max */ 1281 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1282 1283 /* Initialize timers: just disable them all */ 1284 for (i = 0; i < 4; i++) { 1285 mpic_write(mpic->tmregs, 1286 i * MPIC_INFO(TIMER_STRIDE) + 1287 MPIC_INFO(TIMER_DESTINATION), 0); 1288 mpic_write(mpic->tmregs, 1289 i * MPIC_INFO(TIMER_STRIDE) + 1290 MPIC_INFO(TIMER_VECTOR_PRI), 1291 MPIC_VECPRI_MASK | 1292 (mpic->timer_vecs[0] + i)); 1293 } 1294 1295 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 1296 mpic_test_broken_ipi(mpic); 1297 for (i = 0; i < 4; i++) { 1298 mpic_ipi_write(i, 1299 MPIC_VECPRI_MASK | 1300 (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 1301 (mpic->ipi_vecs[0] + i)); 1302 } 1303 1304 /* Initialize interrupt sources */ 1305 if (mpic->irq_count == 0) 1306 mpic->irq_count = mpic->num_sources; 1307 1308 /* Do the HT PIC fixups on U3 broken mpic */ 1309 DBG("MPIC flags: %x\n", mpic->flags); 1310 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { 1311 mpic_scan_ht_pics(mpic); 1312 mpic_u3msi_init(mpic); 1313 } 1314 1315 mpic_pasemi_msi_init(mpic); 1316 1317 if (mpic->flags & MPIC_PRIMARY) 1318 cpu = hard_smp_processor_id(); 1319 else 1320 cpu = 0; 1321 1322 for (i = 0; i < mpic->num_sources; i++) { 1323 /* start with vector = source number, and masked */ 1324 u32 vecpri = MPIC_VECPRI_MASK | i | 1325 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1326 1327 /* check if protected */ 1328 if (mpic->protected && test_bit(i, mpic->protected)) 1329 continue; 1330 /* init hw */ 1331 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1332 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); 1333 } 1334 1335 /* Init spurious vector */ 1336 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 1337 1338 /* Disable 8259 passthrough, if supported */ 1339 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 1340 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1341 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1342 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1343 1344 if (mpic->flags & MPIC_NO_BIAS) 1345 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1346 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1347 | MPIC_GREG_GCONF_NO_BIAS); 1348 1349 /* Set current processor priority to 0 */ 1350 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1351 1352 #ifdef CONFIG_PM 1353 /* allocate memory to save mpic state */ 1354 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save)); 1355 BUG_ON(mpic->save_data == NULL); 1356 #endif 1357 } 1358 1359 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1360 { 1361 u32 v; 1362 1363 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1364 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1365 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1366 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1367 } 1368 1369 void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1370 { 1371 unsigned long flags; 1372 u32 v; 1373 1374 spin_lock_irqsave(&mpic_lock, flags); 1375 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1376 if (enable) 1377 v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1378 else 1379 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1380 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1381 spin_unlock_irqrestore(&mpic_lock, flags); 1382 } 1383 1384 void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 1385 { 1386 struct mpic *mpic = mpic_find(irq); 1387 unsigned int src = mpic_irq_to_hw(irq); 1388 unsigned long flags; 1389 u32 reg; 1390 1391 if (!mpic) 1392 return; 1393 1394 spin_lock_irqsave(&mpic_lock, flags); 1395 if (mpic_is_ipi(mpic, irq)) { 1396 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1397 ~MPIC_VECPRI_PRIORITY_MASK; 1398 mpic_ipi_write(src - mpic->ipi_vecs[0], 1399 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1400 } else { 1401 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1402 & ~MPIC_VECPRI_PRIORITY_MASK; 1403 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 1404 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1405 } 1406 spin_unlock_irqrestore(&mpic_lock, flags); 1407 } 1408 1409 void mpic_setup_this_cpu(void) 1410 { 1411 #ifdef CONFIG_SMP 1412 struct mpic *mpic = mpic_primary; 1413 unsigned long flags; 1414 u32 msk = 1 << hard_smp_processor_id(); 1415 unsigned int i; 1416 1417 BUG_ON(mpic == NULL); 1418 1419 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1420 1421 spin_lock_irqsave(&mpic_lock, flags); 1422 1423 /* let the mpic know we want intrs. default affinity is 0xffffffff 1424 * until changed via /proc. That's how it's done on x86. If we want 1425 * it differently, then we should make sure we also change the default 1426 * values of irq_desc[].affinity in irq.c. 1427 */ 1428 if (distribute_irqs) { 1429 for (i = 0; i < mpic->num_sources ; i++) 1430 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1431 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 1432 } 1433 1434 /* Set current processor priority to 0 */ 1435 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 1436 1437 spin_unlock_irqrestore(&mpic_lock, flags); 1438 #endif /* CONFIG_SMP */ 1439 } 1440 1441 int mpic_cpu_get_priority(void) 1442 { 1443 struct mpic *mpic = mpic_primary; 1444 1445 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 1446 } 1447 1448 void mpic_cpu_set_priority(int prio) 1449 { 1450 struct mpic *mpic = mpic_primary; 1451 1452 prio &= MPIC_CPU_TASKPRI_MASK; 1453 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 1454 } 1455 1456 void mpic_teardown_this_cpu(int secondary) 1457 { 1458 struct mpic *mpic = mpic_primary; 1459 unsigned long flags; 1460 u32 msk = 1 << hard_smp_processor_id(); 1461 unsigned int i; 1462 1463 BUG_ON(mpic == NULL); 1464 1465 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1466 spin_lock_irqsave(&mpic_lock, flags); 1467 1468 /* let the mpic know we don't want intrs. */ 1469 for (i = 0; i < mpic->num_sources ; i++) 1470 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1471 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 1472 1473 /* Set current processor priority to max */ 1474 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1475 /* We need to EOI the IPI since not all platforms reset the MPIC 1476 * on boot and new interrupts wouldn't get delivered otherwise. 1477 */ 1478 mpic_eoi(mpic); 1479 1480 spin_unlock_irqrestore(&mpic_lock, flags); 1481 } 1482 1483 1484 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 1485 { 1486 struct mpic *mpic = mpic_primary; 1487 1488 BUG_ON(mpic == NULL); 1489 1490 #ifdef DEBUG_IPI 1491 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1492 #endif 1493 1494 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 1495 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 1496 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1497 } 1498 1499 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) 1500 { 1501 u32 src; 1502 1503 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); 1504 #ifdef DEBUG_LOW 1505 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); 1506 #endif 1507 if (unlikely(src == mpic->spurious_vec)) { 1508 if (mpic->flags & MPIC_SPV_EOI) 1509 mpic_eoi(mpic); 1510 return NO_IRQ; 1511 } 1512 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1513 if (printk_ratelimit()) 1514 printk(KERN_WARNING "%s: Got protected source %d !\n", 1515 mpic->name, (int)src); 1516 mpic_eoi(mpic); 1517 return NO_IRQ; 1518 } 1519 1520 return irq_linear_revmap(mpic->irqhost, src); 1521 } 1522 1523 unsigned int mpic_get_one_irq(struct mpic *mpic) 1524 { 1525 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); 1526 } 1527 1528 unsigned int mpic_get_irq(void) 1529 { 1530 struct mpic *mpic = mpic_primary; 1531 1532 BUG_ON(mpic == NULL); 1533 1534 return mpic_get_one_irq(mpic); 1535 } 1536 1537 unsigned int mpic_get_coreint_irq(void) 1538 { 1539 #ifdef CONFIG_BOOKE 1540 struct mpic *mpic = mpic_primary; 1541 u32 src; 1542 1543 BUG_ON(mpic == NULL); 1544 1545 src = mfspr(SPRN_EPR); 1546 1547 if (unlikely(src == mpic->spurious_vec)) { 1548 if (mpic->flags & MPIC_SPV_EOI) 1549 mpic_eoi(mpic); 1550 return NO_IRQ; 1551 } 1552 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1553 if (printk_ratelimit()) 1554 printk(KERN_WARNING "%s: Got protected source %d !\n", 1555 mpic->name, (int)src); 1556 return NO_IRQ; 1557 } 1558 1559 return irq_linear_revmap(mpic->irqhost, src); 1560 #else 1561 return NO_IRQ; 1562 #endif 1563 } 1564 1565 unsigned int mpic_get_mcirq(void) 1566 { 1567 struct mpic *mpic = mpic_primary; 1568 1569 BUG_ON(mpic == NULL); 1570 1571 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); 1572 } 1573 1574 #ifdef CONFIG_SMP 1575 void mpic_request_ipis(void) 1576 { 1577 struct mpic *mpic = mpic_primary; 1578 int i; 1579 BUG_ON(mpic == NULL); 1580 1581 printk(KERN_INFO "mpic: requesting IPIs ... \n"); 1582 1583 for (i = 0; i < 4; i++) { 1584 unsigned int vipi = irq_create_mapping(mpic->irqhost, 1585 mpic->ipi_vecs[0] + i); 1586 if (vipi == NO_IRQ) { 1587 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); 1588 continue; 1589 } 1590 smp_request_message_ipi(vipi, i); 1591 } 1592 } 1593 1594 void smp_mpic_message_pass(int target, int msg) 1595 { 1596 /* make sure we're sending something that translates to an IPI */ 1597 if ((unsigned int)msg > 3) { 1598 printk("SMP %d: smp_message_pass: unknown msg %d\n", 1599 smp_processor_id(), msg); 1600 return; 1601 } 1602 switch (target) { 1603 case MSG_ALL: 1604 mpic_send_ipi(msg, 0xffffffff); 1605 break; 1606 case MSG_ALL_BUT_SELF: 1607 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); 1608 break; 1609 default: 1610 mpic_send_ipi(msg, 1 << target); 1611 break; 1612 } 1613 } 1614 1615 int __init smp_mpic_probe(void) 1616 { 1617 int nr_cpus; 1618 1619 DBG("smp_mpic_probe()...\n"); 1620 1621 nr_cpus = cpus_weight(cpu_possible_map); 1622 1623 DBG("nr_cpus: %d\n", nr_cpus); 1624 1625 if (nr_cpus > 1) 1626 mpic_request_ipis(); 1627 1628 return nr_cpus; 1629 } 1630 1631 void __devinit smp_mpic_setup_cpu(int cpu) 1632 { 1633 mpic_setup_this_cpu(); 1634 } 1635 #endif /* CONFIG_SMP */ 1636 1637 #ifdef CONFIG_PM 1638 static int mpic_suspend(struct sys_device *dev, pm_message_t state) 1639 { 1640 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1641 int i; 1642 1643 for (i = 0; i < mpic->num_sources; i++) { 1644 mpic->save_data[i].vecprio = 1645 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 1646 mpic->save_data[i].dest = 1647 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 1648 } 1649 1650 return 0; 1651 } 1652 1653 static int mpic_resume(struct sys_device *dev) 1654 { 1655 struct mpic *mpic = container_of(dev, struct mpic, sysdev); 1656 int i; 1657 1658 for (i = 0; i < mpic->num_sources; i++) { 1659 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 1660 mpic->save_data[i].vecprio); 1661 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1662 mpic->save_data[i].dest); 1663 1664 #ifdef CONFIG_MPIC_U3_HT_IRQS 1665 { 1666 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 1667 1668 if (fixup->base) { 1669 /* we use the lowest bit in an inverted meaning */ 1670 if ((mpic->save_data[i].fixup_data & 1) == 0) 1671 continue; 1672 1673 /* Enable and configure */ 1674 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 1675 1676 writel(mpic->save_data[i].fixup_data & ~1, 1677 fixup->base + 4); 1678 } 1679 } 1680 #endif 1681 } /* end for loop */ 1682 1683 return 0; 1684 } 1685 #endif 1686 1687 static struct sysdev_class mpic_sysclass = { 1688 #ifdef CONFIG_PM 1689 .resume = mpic_resume, 1690 .suspend = mpic_suspend, 1691 #endif 1692 .name = "mpic", 1693 }; 1694 1695 static int mpic_init_sys(void) 1696 { 1697 struct mpic *mpic = mpics; 1698 int error, id = 0; 1699 1700 error = sysdev_class_register(&mpic_sysclass); 1701 1702 while (mpic && !error) { 1703 mpic->sysdev.cls = &mpic_sysclass; 1704 mpic->sysdev.id = id++; 1705 error = sysdev_register(&mpic->sysdev); 1706 mpic = mpic->next; 1707 } 1708 return error; 1709 } 1710 1711 device_initcall(mpic_init_sys); 1712