114cf11afSPaul Mackerras /* 214cf11afSPaul Mackerras * arch/powerpc/kernel/mpic.c 314cf11afSPaul Mackerras * 414cf11afSPaul Mackerras * Driver for interrupt controllers following the OpenPIC standard, the 514cf11afSPaul Mackerras * common implementation beeing IBM's MPIC. This driver also can deal 614cf11afSPaul Mackerras * with various broken implementations of this HW. 714cf11afSPaul Mackerras * 814cf11afSPaul Mackerras * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 914cf11afSPaul Mackerras * 1014cf11afSPaul Mackerras * This file is subject to the terms and conditions of the GNU General Public 1114cf11afSPaul Mackerras * License. See the file COPYING in the main directory of this archive 1214cf11afSPaul Mackerras * for more details. 1314cf11afSPaul Mackerras */ 1414cf11afSPaul Mackerras 1514cf11afSPaul Mackerras #undef DEBUG 161beb6a7dSBenjamin Herrenschmidt #undef DEBUG_IPI 171beb6a7dSBenjamin Herrenschmidt #undef DEBUG_IRQ 181beb6a7dSBenjamin Herrenschmidt #undef DEBUG_LOW 1914cf11afSPaul Mackerras 2014cf11afSPaul Mackerras #include <linux/types.h> 2114cf11afSPaul Mackerras #include <linux/kernel.h> 2214cf11afSPaul Mackerras #include <linux/init.h> 2314cf11afSPaul Mackerras #include <linux/irq.h> 2414cf11afSPaul Mackerras #include <linux/smp.h> 2514cf11afSPaul Mackerras #include <linux/interrupt.h> 2614cf11afSPaul Mackerras #include <linux/bootmem.h> 2714cf11afSPaul Mackerras #include <linux/spinlock.h> 2814cf11afSPaul Mackerras #include <linux/pci.h> 2914cf11afSPaul Mackerras 3014cf11afSPaul Mackerras #include <asm/ptrace.h> 3114cf11afSPaul Mackerras #include <asm/signal.h> 3214cf11afSPaul Mackerras #include <asm/io.h> 3314cf11afSPaul Mackerras #include <asm/pgtable.h> 3414cf11afSPaul Mackerras #include <asm/irq.h> 3514cf11afSPaul Mackerras #include <asm/machdep.h> 3614cf11afSPaul Mackerras #include <asm/mpic.h> 3714cf11afSPaul Mackerras #include <asm/smp.h> 3814cf11afSPaul Mackerras 39a7de7c74SMichael Ellerman #include "mpic.h" 40a7de7c74SMichael Ellerman 4114cf11afSPaul Mackerras #ifdef DEBUG 4214cf11afSPaul Mackerras #define DBG(fmt...) printk(fmt) 4314cf11afSPaul Mackerras #else 4414cf11afSPaul Mackerras #define DBG(fmt...) 4514cf11afSPaul Mackerras #endif 4614cf11afSPaul Mackerras 4714cf11afSPaul Mackerras static struct mpic *mpics; 4814cf11afSPaul Mackerras static struct mpic *mpic_primary; 4914cf11afSPaul Mackerras static DEFINE_SPINLOCK(mpic_lock); 5014cf11afSPaul Mackerras 51c0c0d996SPaul Mackerras #ifdef CONFIG_PPC32 /* XXX for now */ 52e40c7f02SAndy Whitcroft #ifdef CONFIG_IRQ_ALL_CPUS 53e40c7f02SAndy Whitcroft #define distribute_irqs (1) 54e40c7f02SAndy Whitcroft #else 55e40c7f02SAndy Whitcroft #define distribute_irqs (0) 56e40c7f02SAndy Whitcroft #endif 57c0c0d996SPaul Mackerras #endif 5814cf11afSPaul Mackerras 597233593bSZang Roy-r61911 #ifdef CONFIG_MPIC_WEIRD 607233593bSZang Roy-r61911 static u32 mpic_infos[][MPIC_IDX_END] = { 617233593bSZang Roy-r61911 [0] = { /* Original OpenPIC compatible MPIC */ 627233593bSZang Roy-r61911 MPIC_GREG_BASE, 637233593bSZang Roy-r61911 MPIC_GREG_FEATURE_0, 647233593bSZang Roy-r61911 MPIC_GREG_GLOBAL_CONF_0, 657233593bSZang Roy-r61911 MPIC_GREG_VENDOR_ID, 667233593bSZang Roy-r61911 MPIC_GREG_IPI_VECTOR_PRI_0, 677233593bSZang Roy-r61911 MPIC_GREG_IPI_STRIDE, 687233593bSZang Roy-r61911 MPIC_GREG_SPURIOUS, 697233593bSZang Roy-r61911 MPIC_GREG_TIMER_FREQ, 707233593bSZang Roy-r61911 717233593bSZang Roy-r61911 MPIC_TIMER_BASE, 727233593bSZang Roy-r61911 MPIC_TIMER_STRIDE, 737233593bSZang Roy-r61911 MPIC_TIMER_CURRENT_CNT, 747233593bSZang Roy-r61911 MPIC_TIMER_BASE_CNT, 757233593bSZang Roy-r61911 MPIC_TIMER_VECTOR_PRI, 767233593bSZang Roy-r61911 MPIC_TIMER_DESTINATION, 777233593bSZang Roy-r61911 787233593bSZang Roy-r61911 MPIC_CPU_BASE, 797233593bSZang Roy-r61911 MPIC_CPU_STRIDE, 807233593bSZang Roy-r61911 MPIC_CPU_IPI_DISPATCH_0, 817233593bSZang Roy-r61911 MPIC_CPU_IPI_DISPATCH_STRIDE, 827233593bSZang Roy-r61911 MPIC_CPU_CURRENT_TASK_PRI, 837233593bSZang Roy-r61911 MPIC_CPU_WHOAMI, 847233593bSZang Roy-r61911 MPIC_CPU_INTACK, 857233593bSZang Roy-r61911 MPIC_CPU_EOI, 86f365355eSOlof Johansson MPIC_CPU_MCACK, 877233593bSZang Roy-r61911 887233593bSZang Roy-r61911 MPIC_IRQ_BASE, 897233593bSZang Roy-r61911 MPIC_IRQ_STRIDE, 907233593bSZang Roy-r61911 MPIC_IRQ_VECTOR_PRI, 917233593bSZang Roy-r61911 MPIC_VECPRI_VECTOR_MASK, 927233593bSZang Roy-r61911 MPIC_VECPRI_POLARITY_POSITIVE, 937233593bSZang Roy-r61911 MPIC_VECPRI_POLARITY_NEGATIVE, 947233593bSZang Roy-r61911 MPIC_VECPRI_SENSE_LEVEL, 957233593bSZang Roy-r61911 MPIC_VECPRI_SENSE_EDGE, 967233593bSZang Roy-r61911 MPIC_VECPRI_POLARITY_MASK, 977233593bSZang Roy-r61911 MPIC_VECPRI_SENSE_MASK, 987233593bSZang Roy-r61911 MPIC_IRQ_DESTINATION 997233593bSZang Roy-r61911 }, 1007233593bSZang Roy-r61911 [1] = { /* Tsi108/109 PIC */ 1017233593bSZang Roy-r61911 TSI108_GREG_BASE, 1027233593bSZang Roy-r61911 TSI108_GREG_FEATURE_0, 1037233593bSZang Roy-r61911 TSI108_GREG_GLOBAL_CONF_0, 1047233593bSZang Roy-r61911 TSI108_GREG_VENDOR_ID, 1057233593bSZang Roy-r61911 TSI108_GREG_IPI_VECTOR_PRI_0, 1067233593bSZang Roy-r61911 TSI108_GREG_IPI_STRIDE, 1077233593bSZang Roy-r61911 TSI108_GREG_SPURIOUS, 1087233593bSZang Roy-r61911 TSI108_GREG_TIMER_FREQ, 1097233593bSZang Roy-r61911 1107233593bSZang Roy-r61911 TSI108_TIMER_BASE, 1117233593bSZang Roy-r61911 TSI108_TIMER_STRIDE, 1127233593bSZang Roy-r61911 TSI108_TIMER_CURRENT_CNT, 1137233593bSZang Roy-r61911 TSI108_TIMER_BASE_CNT, 1147233593bSZang Roy-r61911 TSI108_TIMER_VECTOR_PRI, 1157233593bSZang Roy-r61911 TSI108_TIMER_DESTINATION, 1167233593bSZang Roy-r61911 1177233593bSZang Roy-r61911 TSI108_CPU_BASE, 1187233593bSZang Roy-r61911 TSI108_CPU_STRIDE, 1197233593bSZang Roy-r61911 TSI108_CPU_IPI_DISPATCH_0, 1207233593bSZang Roy-r61911 TSI108_CPU_IPI_DISPATCH_STRIDE, 1217233593bSZang Roy-r61911 TSI108_CPU_CURRENT_TASK_PRI, 1227233593bSZang Roy-r61911 TSI108_CPU_WHOAMI, 1237233593bSZang Roy-r61911 TSI108_CPU_INTACK, 1247233593bSZang Roy-r61911 TSI108_CPU_EOI, 125f365355eSOlof Johansson TSI108_CPU_MCACK, 1267233593bSZang Roy-r61911 1277233593bSZang Roy-r61911 TSI108_IRQ_BASE, 1287233593bSZang Roy-r61911 TSI108_IRQ_STRIDE, 1297233593bSZang Roy-r61911 TSI108_IRQ_VECTOR_PRI, 1307233593bSZang Roy-r61911 TSI108_VECPRI_VECTOR_MASK, 1317233593bSZang Roy-r61911 TSI108_VECPRI_POLARITY_POSITIVE, 1327233593bSZang Roy-r61911 TSI108_VECPRI_POLARITY_NEGATIVE, 1337233593bSZang Roy-r61911 TSI108_VECPRI_SENSE_LEVEL, 1347233593bSZang Roy-r61911 TSI108_VECPRI_SENSE_EDGE, 1357233593bSZang Roy-r61911 TSI108_VECPRI_POLARITY_MASK, 1367233593bSZang Roy-r61911 TSI108_VECPRI_SENSE_MASK, 1377233593bSZang Roy-r61911 TSI108_IRQ_DESTINATION 1387233593bSZang Roy-r61911 }, 1397233593bSZang Roy-r61911 }; 1407233593bSZang Roy-r61911 1417233593bSZang Roy-r61911 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 1427233593bSZang Roy-r61911 1437233593bSZang Roy-r61911 #else /* CONFIG_MPIC_WEIRD */ 1447233593bSZang Roy-r61911 1457233593bSZang Roy-r61911 #define MPIC_INFO(name) MPIC_##name 1467233593bSZang Roy-r61911 1477233593bSZang Roy-r61911 #endif /* CONFIG_MPIC_WEIRD */ 1487233593bSZang Roy-r61911 14914cf11afSPaul Mackerras /* 15014cf11afSPaul Mackerras * Register accessor functions 15114cf11afSPaul Mackerras */ 15214cf11afSPaul Mackerras 15314cf11afSPaul Mackerras 154fbf0274eSBenjamin Herrenschmidt static inline u32 _mpic_read(enum mpic_reg_type type, 155fbf0274eSBenjamin Herrenschmidt struct mpic_reg_bank *rb, 15614cf11afSPaul Mackerras unsigned int reg) 15714cf11afSPaul Mackerras { 158fbf0274eSBenjamin Herrenschmidt switch(type) { 159fbf0274eSBenjamin Herrenschmidt #ifdef CONFIG_PPC_DCR 160fbf0274eSBenjamin Herrenschmidt case mpic_access_dcr: 16183f34df4SMichael Ellerman return dcr_read(rb->dhost, reg); 162fbf0274eSBenjamin Herrenschmidt #endif 163fbf0274eSBenjamin Herrenschmidt case mpic_access_mmio_be: 164fbf0274eSBenjamin Herrenschmidt return in_be32(rb->base + (reg >> 2)); 165fbf0274eSBenjamin Herrenschmidt case mpic_access_mmio_le: 166fbf0274eSBenjamin Herrenschmidt default: 167fbf0274eSBenjamin Herrenschmidt return in_le32(rb->base + (reg >> 2)); 168fbf0274eSBenjamin Herrenschmidt } 16914cf11afSPaul Mackerras } 17014cf11afSPaul Mackerras 171fbf0274eSBenjamin Herrenschmidt static inline void _mpic_write(enum mpic_reg_type type, 172fbf0274eSBenjamin Herrenschmidt struct mpic_reg_bank *rb, 17314cf11afSPaul Mackerras unsigned int reg, u32 value) 17414cf11afSPaul Mackerras { 175fbf0274eSBenjamin Herrenschmidt switch(type) { 176fbf0274eSBenjamin Herrenschmidt #ifdef CONFIG_PPC_DCR 177fbf0274eSBenjamin Herrenschmidt case mpic_access_dcr: 178*d9d1063dSJohannes Berg dcr_write(rb->dhost, reg, value); 179*d9d1063dSJohannes Berg break; 180fbf0274eSBenjamin Herrenschmidt #endif 181fbf0274eSBenjamin Herrenschmidt case mpic_access_mmio_be: 182*d9d1063dSJohannes Berg out_be32(rb->base + (reg >> 2), value); 183*d9d1063dSJohannes Berg break; 184fbf0274eSBenjamin Herrenschmidt case mpic_access_mmio_le: 185fbf0274eSBenjamin Herrenschmidt default: 186*d9d1063dSJohannes Berg out_le32(rb->base + (reg >> 2), value); 187*d9d1063dSJohannes Berg break; 188fbf0274eSBenjamin Herrenschmidt } 18914cf11afSPaul Mackerras } 19014cf11afSPaul Mackerras 19114cf11afSPaul Mackerras static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 19214cf11afSPaul Mackerras { 193fbf0274eSBenjamin Herrenschmidt enum mpic_reg_type type = mpic->reg_type; 1947233593bSZang Roy-r61911 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 1957233593bSZang Roy-r61911 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 19614cf11afSPaul Mackerras 197fbf0274eSBenjamin Herrenschmidt if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 198fbf0274eSBenjamin Herrenschmidt type = mpic_access_mmio_be; 199fbf0274eSBenjamin Herrenschmidt return _mpic_read(type, &mpic->gregs, offset); 20014cf11afSPaul Mackerras } 20114cf11afSPaul Mackerras 20214cf11afSPaul Mackerras static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 20314cf11afSPaul Mackerras { 2047233593bSZang Roy-r61911 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 2057233593bSZang Roy-r61911 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 20614cf11afSPaul Mackerras 207fbf0274eSBenjamin Herrenschmidt _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 20814cf11afSPaul Mackerras } 20914cf11afSPaul Mackerras 21014cf11afSPaul Mackerras static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 21114cf11afSPaul Mackerras { 21214cf11afSPaul Mackerras unsigned int cpu = 0; 21314cf11afSPaul Mackerras 21414cf11afSPaul Mackerras if (mpic->flags & MPIC_PRIMARY) 21514cf11afSPaul Mackerras cpu = hard_smp_processor_id(); 216fbf0274eSBenjamin Herrenschmidt return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 21714cf11afSPaul Mackerras } 21814cf11afSPaul Mackerras 21914cf11afSPaul Mackerras static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 22014cf11afSPaul Mackerras { 22114cf11afSPaul Mackerras unsigned int cpu = 0; 22214cf11afSPaul Mackerras 22314cf11afSPaul Mackerras if (mpic->flags & MPIC_PRIMARY) 22414cf11afSPaul Mackerras cpu = hard_smp_processor_id(); 22514cf11afSPaul Mackerras 226fbf0274eSBenjamin Herrenschmidt _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 22714cf11afSPaul Mackerras } 22814cf11afSPaul Mackerras 22914cf11afSPaul Mackerras static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 23014cf11afSPaul Mackerras { 23114cf11afSPaul Mackerras unsigned int isu = src_no >> mpic->isu_shift; 23214cf11afSPaul Mackerras unsigned int idx = src_no & mpic->isu_mask; 23314cf11afSPaul Mackerras 2340d72ba93SOlof Johansson #ifdef CONFIG_MPIC_BROKEN_REGREAD 2350d72ba93SOlof Johansson if (reg == 0) 2360d72ba93SOlof Johansson return mpic->isu_reg0_shadow[idx]; 2370d72ba93SOlof Johansson else 2380d72ba93SOlof Johansson #endif 239fbf0274eSBenjamin Herrenschmidt return _mpic_read(mpic->reg_type, &mpic->isus[isu], 2407233593bSZang Roy-r61911 reg + (idx * MPIC_INFO(IRQ_STRIDE))); 24114cf11afSPaul Mackerras } 24214cf11afSPaul Mackerras 24314cf11afSPaul Mackerras static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 24414cf11afSPaul Mackerras unsigned int reg, u32 value) 24514cf11afSPaul Mackerras { 24614cf11afSPaul Mackerras unsigned int isu = src_no >> mpic->isu_shift; 24714cf11afSPaul Mackerras unsigned int idx = src_no & mpic->isu_mask; 24814cf11afSPaul Mackerras 249fbf0274eSBenjamin Herrenschmidt _mpic_write(mpic->reg_type, &mpic->isus[isu], 2507233593bSZang Roy-r61911 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 2510d72ba93SOlof Johansson 2520d72ba93SOlof Johansson #ifdef CONFIG_MPIC_BROKEN_REGREAD 2530d72ba93SOlof Johansson if (reg == 0) 2540d72ba93SOlof Johansson mpic->isu_reg0_shadow[idx] = value; 2550d72ba93SOlof Johansson #endif 25614cf11afSPaul Mackerras } 25714cf11afSPaul Mackerras 258fbf0274eSBenjamin Herrenschmidt #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 259fbf0274eSBenjamin Herrenschmidt #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 26014cf11afSPaul Mackerras #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 26114cf11afSPaul Mackerras #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 26214cf11afSPaul Mackerras #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 26314cf11afSPaul Mackerras #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 26414cf11afSPaul Mackerras #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 26514cf11afSPaul Mackerras #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 26614cf11afSPaul Mackerras 26714cf11afSPaul Mackerras 26814cf11afSPaul Mackerras /* 26914cf11afSPaul Mackerras * Low level utility functions 27014cf11afSPaul Mackerras */ 27114cf11afSPaul Mackerras 27214cf11afSPaul Mackerras 273c51a3fdcSBecky Bruce static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, 274fbf0274eSBenjamin Herrenschmidt struct mpic_reg_bank *rb, unsigned int offset, 275fbf0274eSBenjamin Herrenschmidt unsigned int size) 276fbf0274eSBenjamin Herrenschmidt { 277fbf0274eSBenjamin Herrenschmidt rb->base = ioremap(phys_addr + offset, size); 278fbf0274eSBenjamin Herrenschmidt BUG_ON(rb->base == NULL); 279fbf0274eSBenjamin Herrenschmidt } 280fbf0274eSBenjamin Herrenschmidt 281fbf0274eSBenjamin Herrenschmidt #ifdef CONFIG_PPC_DCR 282fbf0274eSBenjamin Herrenschmidt static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, 283fbf0274eSBenjamin Herrenschmidt unsigned int offset, unsigned int size) 284fbf0274eSBenjamin Herrenschmidt { 2850411a5e2SMichael Ellerman const u32 *dbasep; 2860411a5e2SMichael Ellerman 2870411a5e2SMichael Ellerman dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); 2880411a5e2SMichael Ellerman 2890411a5e2SMichael Ellerman rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); 290fbf0274eSBenjamin Herrenschmidt BUG_ON(!DCR_MAP_OK(rb->dhost)); 291fbf0274eSBenjamin Herrenschmidt } 292fbf0274eSBenjamin Herrenschmidt 293c51a3fdcSBecky Bruce static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, 294fbf0274eSBenjamin Herrenschmidt struct mpic_reg_bank *rb, unsigned int offset, 295fbf0274eSBenjamin Herrenschmidt unsigned int size) 296fbf0274eSBenjamin Herrenschmidt { 297fbf0274eSBenjamin Herrenschmidt if (mpic->flags & MPIC_USES_DCR) 298fbf0274eSBenjamin Herrenschmidt _mpic_map_dcr(mpic, rb, offset, size); 299fbf0274eSBenjamin Herrenschmidt else 300fbf0274eSBenjamin Herrenschmidt _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 301fbf0274eSBenjamin Herrenschmidt } 302fbf0274eSBenjamin Herrenschmidt #else /* CONFIG_PPC_DCR */ 303fbf0274eSBenjamin Herrenschmidt #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 304fbf0274eSBenjamin Herrenschmidt #endif /* !CONFIG_PPC_DCR */ 305fbf0274eSBenjamin Herrenschmidt 306fbf0274eSBenjamin Herrenschmidt 30714cf11afSPaul Mackerras 30814cf11afSPaul Mackerras /* Check if we have one of those nice broken MPICs with a flipped endian on 30914cf11afSPaul Mackerras * reads from IPI registers 31014cf11afSPaul Mackerras */ 31114cf11afSPaul Mackerras static void __init mpic_test_broken_ipi(struct mpic *mpic) 31214cf11afSPaul Mackerras { 31314cf11afSPaul Mackerras u32 r; 31414cf11afSPaul Mackerras 3157233593bSZang Roy-r61911 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 3167233593bSZang Roy-r61911 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 31714cf11afSPaul Mackerras 31814cf11afSPaul Mackerras if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 31914cf11afSPaul Mackerras printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 32014cf11afSPaul Mackerras mpic->flags |= MPIC_BROKEN_IPI; 32114cf11afSPaul Mackerras } 32214cf11afSPaul Mackerras } 32314cf11afSPaul Mackerras 3246cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 32514cf11afSPaul Mackerras 32614cf11afSPaul Mackerras /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 32714cf11afSPaul Mackerras * to force the edge setting on the MPIC and do the ack workaround. 32814cf11afSPaul Mackerras */ 3291beb6a7dSBenjamin Herrenschmidt static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 33014cf11afSPaul Mackerras { 3311beb6a7dSBenjamin Herrenschmidt if (source >= 128 || !mpic->fixups) 33214cf11afSPaul Mackerras return 0; 3331beb6a7dSBenjamin Herrenschmidt return mpic->fixups[source].base != NULL; 33414cf11afSPaul Mackerras } 33514cf11afSPaul Mackerras 336c4b22f26SSegher Boessenkool 3371beb6a7dSBenjamin Herrenschmidt static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 33814cf11afSPaul Mackerras { 3391beb6a7dSBenjamin Herrenschmidt struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 34014cf11afSPaul Mackerras 3411beb6a7dSBenjamin Herrenschmidt if (fixup->applebase) { 3421beb6a7dSBenjamin Herrenschmidt unsigned int soff = (fixup->index >> 3) & ~3; 3431beb6a7dSBenjamin Herrenschmidt unsigned int mask = 1U << (fixup->index & 0x1f); 3441beb6a7dSBenjamin Herrenschmidt writel(mask, fixup->applebase + soff); 3451beb6a7dSBenjamin Herrenschmidt } else { 34614cf11afSPaul Mackerras spin_lock(&mpic->fixup_lock); 3471beb6a7dSBenjamin Herrenschmidt writeb(0x11 + 2 * fixup->index, fixup->base + 2); 348c4b22f26SSegher Boessenkool writel(fixup->data, fixup->base + 4); 34914cf11afSPaul Mackerras spin_unlock(&mpic->fixup_lock); 35014cf11afSPaul Mackerras } 3511beb6a7dSBenjamin Herrenschmidt } 35214cf11afSPaul Mackerras 3531beb6a7dSBenjamin Herrenschmidt static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 3541beb6a7dSBenjamin Herrenschmidt unsigned int irqflags) 3551beb6a7dSBenjamin Herrenschmidt { 3561beb6a7dSBenjamin Herrenschmidt struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 3571beb6a7dSBenjamin Herrenschmidt unsigned long flags; 3581beb6a7dSBenjamin Herrenschmidt u32 tmp; 35914cf11afSPaul Mackerras 3601beb6a7dSBenjamin Herrenschmidt if (fixup->base == NULL) 3611beb6a7dSBenjamin Herrenschmidt return; 3621beb6a7dSBenjamin Herrenschmidt 36306fe98e6SBenjamin Herrenschmidt DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 3641beb6a7dSBenjamin Herrenschmidt source, irqflags, fixup->index); 3651beb6a7dSBenjamin Herrenschmidt spin_lock_irqsave(&mpic->fixup_lock, flags); 3661beb6a7dSBenjamin Herrenschmidt /* Enable and configure */ 3671beb6a7dSBenjamin Herrenschmidt writeb(0x10 + 2 * fixup->index, fixup->base + 2); 3681beb6a7dSBenjamin Herrenschmidt tmp = readl(fixup->base + 4); 3691beb6a7dSBenjamin Herrenschmidt tmp &= ~(0x23U); 3701beb6a7dSBenjamin Herrenschmidt if (irqflags & IRQ_LEVEL) 3711beb6a7dSBenjamin Herrenschmidt tmp |= 0x22; 3721beb6a7dSBenjamin Herrenschmidt writel(tmp, fixup->base + 4); 3731beb6a7dSBenjamin Herrenschmidt spin_unlock_irqrestore(&mpic->fixup_lock, flags); 3743669e930SJohannes Berg 3753669e930SJohannes Berg #ifdef CONFIG_PM 3763669e930SJohannes Berg /* use the lowest bit inverted to the actual HW, 3773669e930SJohannes Berg * set if this fixup was enabled, clear otherwise */ 3783669e930SJohannes Berg mpic->save_data[source].fixup_data = tmp | 1; 3793669e930SJohannes Berg #endif 3801beb6a7dSBenjamin Herrenschmidt } 3811beb6a7dSBenjamin Herrenschmidt 3821beb6a7dSBenjamin Herrenschmidt static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 3831beb6a7dSBenjamin Herrenschmidt unsigned int irqflags) 3841beb6a7dSBenjamin Herrenschmidt { 3851beb6a7dSBenjamin Herrenschmidt struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 3861beb6a7dSBenjamin Herrenschmidt unsigned long flags; 3871beb6a7dSBenjamin Herrenschmidt u32 tmp; 3881beb6a7dSBenjamin Herrenschmidt 3891beb6a7dSBenjamin Herrenschmidt if (fixup->base == NULL) 3901beb6a7dSBenjamin Herrenschmidt return; 3911beb6a7dSBenjamin Herrenschmidt 39206fe98e6SBenjamin Herrenschmidt DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 3931beb6a7dSBenjamin Herrenschmidt 3941beb6a7dSBenjamin Herrenschmidt /* Disable */ 3951beb6a7dSBenjamin Herrenschmidt spin_lock_irqsave(&mpic->fixup_lock, flags); 3961beb6a7dSBenjamin Herrenschmidt writeb(0x10 + 2 * fixup->index, fixup->base + 2); 3971beb6a7dSBenjamin Herrenschmidt tmp = readl(fixup->base + 4); 39872b13819SSegher Boessenkool tmp |= 1; 3991beb6a7dSBenjamin Herrenschmidt writel(tmp, fixup->base + 4); 4001beb6a7dSBenjamin Herrenschmidt spin_unlock_irqrestore(&mpic->fixup_lock, flags); 4013669e930SJohannes Berg 4023669e930SJohannes Berg #ifdef CONFIG_PM 4033669e930SJohannes Berg /* use the lowest bit inverted to the actual HW, 4043669e930SJohannes Berg * set if this fixup was enabled, clear otherwise */ 4053669e930SJohannes Berg mpic->save_data[source].fixup_data = tmp & ~1; 4063669e930SJohannes Berg #endif 4071beb6a7dSBenjamin Herrenschmidt } 4081beb6a7dSBenjamin Herrenschmidt 409812fd1fdSMichael Ellerman #ifdef CONFIG_PCI_MSI 410812fd1fdSMichael Ellerman static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 411812fd1fdSMichael Ellerman unsigned int devfn) 412812fd1fdSMichael Ellerman { 413812fd1fdSMichael Ellerman u8 __iomem *base; 414812fd1fdSMichael Ellerman u8 pos, flags; 415812fd1fdSMichael Ellerman u64 addr = 0; 416812fd1fdSMichael Ellerman 417812fd1fdSMichael Ellerman for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 418812fd1fdSMichael Ellerman pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 419812fd1fdSMichael Ellerman u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 420812fd1fdSMichael Ellerman if (id == PCI_CAP_ID_HT) { 421812fd1fdSMichael Ellerman id = readb(devbase + pos + 3); 422812fd1fdSMichael Ellerman if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 423812fd1fdSMichael Ellerman break; 424812fd1fdSMichael Ellerman } 425812fd1fdSMichael Ellerman } 426812fd1fdSMichael Ellerman 427812fd1fdSMichael Ellerman if (pos == 0) 428812fd1fdSMichael Ellerman return; 429812fd1fdSMichael Ellerman 430812fd1fdSMichael Ellerman base = devbase + pos; 431812fd1fdSMichael Ellerman 432812fd1fdSMichael Ellerman flags = readb(base + HT_MSI_FLAGS); 433812fd1fdSMichael Ellerman if (!(flags & HT_MSI_FLAGS_FIXED)) { 434812fd1fdSMichael Ellerman addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 435812fd1fdSMichael Ellerman addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 436812fd1fdSMichael Ellerman } 437812fd1fdSMichael Ellerman 438812fd1fdSMichael Ellerman printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n", 439812fd1fdSMichael Ellerman PCI_SLOT(devfn), PCI_FUNC(devfn), 440812fd1fdSMichael Ellerman flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 441812fd1fdSMichael Ellerman 442812fd1fdSMichael Ellerman if (!(flags & HT_MSI_FLAGS_ENABLE)) 443812fd1fdSMichael Ellerman writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 444812fd1fdSMichael Ellerman } 445812fd1fdSMichael Ellerman #else 446812fd1fdSMichael Ellerman static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 447812fd1fdSMichael Ellerman unsigned int devfn) 448812fd1fdSMichael Ellerman { 449812fd1fdSMichael Ellerman return; 450812fd1fdSMichael Ellerman } 451812fd1fdSMichael Ellerman #endif 452812fd1fdSMichael Ellerman 4531beb6a7dSBenjamin Herrenschmidt static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 4541beb6a7dSBenjamin Herrenschmidt unsigned int devfn, u32 vdid) 45514cf11afSPaul Mackerras { 456c4b22f26SSegher Boessenkool int i, irq, n; 4571beb6a7dSBenjamin Herrenschmidt u8 __iomem *base; 45814cf11afSPaul Mackerras u32 tmp; 459c4b22f26SSegher Boessenkool u8 pos; 46014cf11afSPaul Mackerras 4611beb6a7dSBenjamin Herrenschmidt for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 4621beb6a7dSBenjamin Herrenschmidt pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 4631beb6a7dSBenjamin Herrenschmidt u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 46446ff3463SBrice Goglin if (id == PCI_CAP_ID_HT) { 465c4b22f26SSegher Boessenkool id = readb(devbase + pos + 3); 466beb7cc82SMichael Ellerman if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 467c4b22f26SSegher Boessenkool break; 468c4b22f26SSegher Boessenkool } 469c4b22f26SSegher Boessenkool } 470c4b22f26SSegher Boessenkool if (pos == 0) 471c4b22f26SSegher Boessenkool return; 472c4b22f26SSegher Boessenkool 4731beb6a7dSBenjamin Herrenschmidt base = devbase + pos; 4741beb6a7dSBenjamin Herrenschmidt writeb(0x01, base + 2); 4751beb6a7dSBenjamin Herrenschmidt n = (readl(base + 4) >> 16) & 0xff; 476c4b22f26SSegher Boessenkool 4771beb6a7dSBenjamin Herrenschmidt printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 4781beb6a7dSBenjamin Herrenschmidt " has %d irqs\n", 4791beb6a7dSBenjamin Herrenschmidt devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 480c4b22f26SSegher Boessenkool 481c4b22f26SSegher Boessenkool for (i = 0; i <= n; i++) { 4821beb6a7dSBenjamin Herrenschmidt writeb(0x10 + 2 * i, base + 2); 4831beb6a7dSBenjamin Herrenschmidt tmp = readl(base + 4); 48414cf11afSPaul Mackerras irq = (tmp >> 16) & 0xff; 4851beb6a7dSBenjamin Herrenschmidt DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 4861beb6a7dSBenjamin Herrenschmidt /* mask it , will be unmasked later */ 4871beb6a7dSBenjamin Herrenschmidt tmp |= 0x1; 4881beb6a7dSBenjamin Herrenschmidt writel(tmp, base + 4); 4891beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].index = i; 4901beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].base = base; 4911beb6a7dSBenjamin Herrenschmidt /* Apple HT PIC has a non-standard way of doing EOIs */ 4921beb6a7dSBenjamin Herrenschmidt if ((vdid & 0xffff) == 0x106b) 4931beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].applebase = devbase + 0x60; 4941beb6a7dSBenjamin Herrenschmidt else 4951beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].applebase = NULL; 4961beb6a7dSBenjamin Herrenschmidt writeb(0x11 + 2 * i, base + 2); 4971beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 49814cf11afSPaul Mackerras } 49914cf11afSPaul Mackerras } 50014cf11afSPaul Mackerras 50114cf11afSPaul Mackerras 5021beb6a7dSBenjamin Herrenschmidt static void __init mpic_scan_ht_pics(struct mpic *mpic) 50314cf11afSPaul Mackerras { 50414cf11afSPaul Mackerras unsigned int devfn; 50514cf11afSPaul Mackerras u8 __iomem *cfgspace; 50614cf11afSPaul Mackerras 5071beb6a7dSBenjamin Herrenschmidt printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 50814cf11afSPaul Mackerras 50914cf11afSPaul Mackerras /* Allocate fixups array */ 51014cf11afSPaul Mackerras mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); 51114cf11afSPaul Mackerras BUG_ON(mpic->fixups == NULL); 51214cf11afSPaul Mackerras memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); 51314cf11afSPaul Mackerras 51414cf11afSPaul Mackerras /* Init spinlock */ 51514cf11afSPaul Mackerras spin_lock_init(&mpic->fixup_lock); 51614cf11afSPaul Mackerras 517c4b22f26SSegher Boessenkool /* Map U3 config space. We assume all IO-APICs are on the primary bus 518c4b22f26SSegher Boessenkool * so we only need to map 64kB. 51914cf11afSPaul Mackerras */ 520c4b22f26SSegher Boessenkool cfgspace = ioremap(0xf2000000, 0x10000); 52114cf11afSPaul Mackerras BUG_ON(cfgspace == NULL); 52214cf11afSPaul Mackerras 5231beb6a7dSBenjamin Herrenschmidt /* Now we scan all slots. We do a very quick scan, we read the header 5241beb6a7dSBenjamin Herrenschmidt * type, vendor ID and device ID only, that's plenty enough 52514cf11afSPaul Mackerras */ 526c4b22f26SSegher Boessenkool for (devfn = 0; devfn < 0x100; devfn++) { 52714cf11afSPaul Mackerras u8 __iomem *devbase = cfgspace + (devfn << 8); 52814cf11afSPaul Mackerras u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 52914cf11afSPaul Mackerras u32 l = readl(devbase + PCI_VENDOR_ID); 5301beb6a7dSBenjamin Herrenschmidt u16 s; 53114cf11afSPaul Mackerras 53214cf11afSPaul Mackerras DBG("devfn %x, l: %x\n", devfn, l); 53314cf11afSPaul Mackerras 53414cf11afSPaul Mackerras /* If no device, skip */ 53514cf11afSPaul Mackerras if (l == 0xffffffff || l == 0x00000000 || 53614cf11afSPaul Mackerras l == 0x0000ffff || l == 0xffff0000) 53714cf11afSPaul Mackerras goto next; 5381beb6a7dSBenjamin Herrenschmidt /* Check if is supports capability lists */ 5391beb6a7dSBenjamin Herrenschmidt s = readw(devbase + PCI_STATUS); 5401beb6a7dSBenjamin Herrenschmidt if (!(s & PCI_STATUS_CAP_LIST)) 5411beb6a7dSBenjamin Herrenschmidt goto next; 54214cf11afSPaul Mackerras 5431beb6a7dSBenjamin Herrenschmidt mpic_scan_ht_pic(mpic, devbase, devfn, l); 544812fd1fdSMichael Ellerman mpic_scan_ht_msi(mpic, devbase, devfn); 54514cf11afSPaul Mackerras 54614cf11afSPaul Mackerras next: 54714cf11afSPaul Mackerras /* next device, if function 0 */ 548c4b22f26SSegher Boessenkool if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 54914cf11afSPaul Mackerras devfn += 7; 55014cf11afSPaul Mackerras } 55114cf11afSPaul Mackerras } 55214cf11afSPaul Mackerras 5536cfef5b2SMichael Ellerman #else /* CONFIG_MPIC_U3_HT_IRQS */ 5546e99e458SBenjamin Herrenschmidt 5556e99e458SBenjamin Herrenschmidt static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 5566e99e458SBenjamin Herrenschmidt { 5576e99e458SBenjamin Herrenschmidt return 0; 5586e99e458SBenjamin Herrenschmidt } 5596e99e458SBenjamin Herrenschmidt 5606e99e458SBenjamin Herrenschmidt static void __init mpic_scan_ht_pics(struct mpic *mpic) 5616e99e458SBenjamin Herrenschmidt { 5626e99e458SBenjamin Herrenschmidt } 5636e99e458SBenjamin Herrenschmidt 5646cfef5b2SMichael Ellerman #endif /* CONFIG_MPIC_U3_HT_IRQS */ 56514cf11afSPaul Mackerras 56614cf11afSPaul Mackerras 5670ebfff14SBenjamin Herrenschmidt #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 5680ebfff14SBenjamin Herrenschmidt 56914cf11afSPaul Mackerras /* Find an mpic associated with a given linux interrupt */ 57014cf11afSPaul Mackerras static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) 57114cf11afSPaul Mackerras { 5720ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 5737df2457dSOlof Johansson struct mpic *mpic; 57414cf11afSPaul Mackerras 5750ebfff14SBenjamin Herrenschmidt if (irq < NUM_ISA_INTERRUPTS) 57614cf11afSPaul Mackerras return NULL; 5770ebfff14SBenjamin Herrenschmidt 5787df2457dSOlof Johansson mpic = irq_desc[irq].chip_data; 5797df2457dSOlof Johansson 5807df2457dSOlof Johansson if (is_ipi) 5817df2457dSOlof Johansson *is_ipi = (src >= mpic->ipi_vecs[0] && 5827df2457dSOlof Johansson src <= mpic->ipi_vecs[3]); 5837df2457dSOlof Johansson 5847df2457dSOlof Johansson return mpic; 58514cf11afSPaul Mackerras } 58614cf11afSPaul Mackerras 58714cf11afSPaul Mackerras /* Convert a cpu mask from logical to physical cpu numbers. */ 58814cf11afSPaul Mackerras static inline u32 mpic_physmask(u32 cpumask) 58914cf11afSPaul Mackerras { 59014cf11afSPaul Mackerras int i; 59114cf11afSPaul Mackerras u32 mask = 0; 59214cf11afSPaul Mackerras 59314cf11afSPaul Mackerras for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 59414cf11afSPaul Mackerras mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 59514cf11afSPaul Mackerras return mask; 59614cf11afSPaul Mackerras } 59714cf11afSPaul Mackerras 59814cf11afSPaul Mackerras #ifdef CONFIG_SMP 59914cf11afSPaul Mackerras /* Get the mpic structure from the IPI number */ 60014cf11afSPaul Mackerras static inline struct mpic * mpic_from_ipi(unsigned int ipi) 60114cf11afSPaul Mackerras { 602b9e5b4e6SBenjamin Herrenschmidt return irq_desc[ipi].chip_data; 60314cf11afSPaul Mackerras } 60414cf11afSPaul Mackerras #endif 60514cf11afSPaul Mackerras 60614cf11afSPaul Mackerras /* Get the mpic structure from the irq number */ 60714cf11afSPaul Mackerras static inline struct mpic * mpic_from_irq(unsigned int irq) 60814cf11afSPaul Mackerras { 609b9e5b4e6SBenjamin Herrenschmidt return irq_desc[irq].chip_data; 61014cf11afSPaul Mackerras } 61114cf11afSPaul Mackerras 61214cf11afSPaul Mackerras /* Send an EOI */ 61314cf11afSPaul Mackerras static inline void mpic_eoi(struct mpic *mpic) 61414cf11afSPaul Mackerras { 6157233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 6167233593bSZang Roy-r61911 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 61714cf11afSPaul Mackerras } 61814cf11afSPaul Mackerras 61914cf11afSPaul Mackerras #ifdef CONFIG_SMP 620194046a1SOlof Johansson static irqreturn_t mpic_ipi_action(int irq, void *data) 62114cf11afSPaul Mackerras { 622194046a1SOlof Johansson long ipi = (long)data; 6237df2457dSOlof Johansson 624194046a1SOlof Johansson smp_message_recv(ipi); 6257df2457dSOlof Johansson 62614cf11afSPaul Mackerras return IRQ_HANDLED; 62714cf11afSPaul Mackerras } 62814cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 62914cf11afSPaul Mackerras 63014cf11afSPaul Mackerras /* 63114cf11afSPaul Mackerras * Linux descriptor level callbacks 63214cf11afSPaul Mackerras */ 63314cf11afSPaul Mackerras 63414cf11afSPaul Mackerras 63505af7bd2SMichael Ellerman void mpic_unmask_irq(unsigned int irq) 63614cf11afSPaul Mackerras { 63714cf11afSPaul Mackerras unsigned int loops = 100000; 63814cf11afSPaul Mackerras struct mpic *mpic = mpic_from_irq(irq); 6390ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 64014cf11afSPaul Mackerras 641bd561c79SPaul Mackerras DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 64214cf11afSPaul Mackerras 6437233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 6447233593bSZang Roy-r61911 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 645e5356640SBenjamin Herrenschmidt ~MPIC_VECPRI_MASK); 64614cf11afSPaul Mackerras /* make sure mask gets to controller before we return to user */ 64714cf11afSPaul Mackerras do { 64814cf11afSPaul Mackerras if (!loops--) { 64914cf11afSPaul Mackerras printk(KERN_ERR "mpic_enable_irq timeout\n"); 65014cf11afSPaul Mackerras break; 65114cf11afSPaul Mackerras } 6527233593bSZang Roy-r61911 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 6531beb6a7dSBenjamin Herrenschmidt } 6541beb6a7dSBenjamin Herrenschmidt 65505af7bd2SMichael Ellerman void mpic_mask_irq(unsigned int irq) 65614cf11afSPaul Mackerras { 65714cf11afSPaul Mackerras unsigned int loops = 100000; 65814cf11afSPaul Mackerras struct mpic *mpic = mpic_from_irq(irq); 6590ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 66014cf11afSPaul Mackerras 66114cf11afSPaul Mackerras DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 66214cf11afSPaul Mackerras 6637233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 6647233593bSZang Roy-r61911 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 665e5356640SBenjamin Herrenschmidt MPIC_VECPRI_MASK); 66614cf11afSPaul Mackerras 66714cf11afSPaul Mackerras /* make sure mask gets to controller before we return to user */ 66814cf11afSPaul Mackerras do { 66914cf11afSPaul Mackerras if (!loops--) { 67014cf11afSPaul Mackerras printk(KERN_ERR "mpic_enable_irq timeout\n"); 67114cf11afSPaul Mackerras break; 67214cf11afSPaul Mackerras } 6737233593bSZang Roy-r61911 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 67414cf11afSPaul Mackerras } 67514cf11afSPaul Mackerras 67605af7bd2SMichael Ellerman void mpic_end_irq(unsigned int irq) 67714cf11afSPaul Mackerras { 67814cf11afSPaul Mackerras struct mpic *mpic = mpic_from_irq(irq); 67914cf11afSPaul Mackerras 6801beb6a7dSBenjamin Herrenschmidt #ifdef DEBUG_IRQ 68114cf11afSPaul Mackerras DBG("%s: end_irq: %d\n", mpic->name, irq); 6821beb6a7dSBenjamin Herrenschmidt #endif 68314cf11afSPaul Mackerras /* We always EOI on end_irq() even for edge interrupts since that 68414cf11afSPaul Mackerras * should only lower the priority, the MPIC should have properly 68514cf11afSPaul Mackerras * latched another edge interrupt coming in anyway 68614cf11afSPaul Mackerras */ 68714cf11afSPaul Mackerras 68814cf11afSPaul Mackerras mpic_eoi(mpic); 68914cf11afSPaul Mackerras } 69014cf11afSPaul Mackerras 6916cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 692b9e5b4e6SBenjamin Herrenschmidt 693b9e5b4e6SBenjamin Herrenschmidt static void mpic_unmask_ht_irq(unsigned int irq) 694b9e5b4e6SBenjamin Herrenschmidt { 695b9e5b4e6SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(irq); 6960ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 697b9e5b4e6SBenjamin Herrenschmidt 698b9e5b4e6SBenjamin Herrenschmidt mpic_unmask_irq(irq); 699b9e5b4e6SBenjamin Herrenschmidt 700b9e5b4e6SBenjamin Herrenschmidt if (irq_desc[irq].status & IRQ_LEVEL) 701b9e5b4e6SBenjamin Herrenschmidt mpic_ht_end_irq(mpic, src); 702b9e5b4e6SBenjamin Herrenschmidt } 703b9e5b4e6SBenjamin Herrenschmidt 704b9e5b4e6SBenjamin Herrenschmidt static unsigned int mpic_startup_ht_irq(unsigned int irq) 705b9e5b4e6SBenjamin Herrenschmidt { 706b9e5b4e6SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(irq); 7070ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 708b9e5b4e6SBenjamin Herrenschmidt 709b9e5b4e6SBenjamin Herrenschmidt mpic_unmask_irq(irq); 710b9e5b4e6SBenjamin Herrenschmidt mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); 711b9e5b4e6SBenjamin Herrenschmidt 712b9e5b4e6SBenjamin Herrenschmidt return 0; 713b9e5b4e6SBenjamin Herrenschmidt } 714b9e5b4e6SBenjamin Herrenschmidt 715b9e5b4e6SBenjamin Herrenschmidt static void mpic_shutdown_ht_irq(unsigned int irq) 716b9e5b4e6SBenjamin Herrenschmidt { 717b9e5b4e6SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(irq); 7180ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 719b9e5b4e6SBenjamin Herrenschmidt 720b9e5b4e6SBenjamin Herrenschmidt mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); 721b9e5b4e6SBenjamin Herrenschmidt mpic_mask_irq(irq); 722b9e5b4e6SBenjamin Herrenschmidt } 723b9e5b4e6SBenjamin Herrenschmidt 724b9e5b4e6SBenjamin Herrenschmidt static void mpic_end_ht_irq(unsigned int irq) 725b9e5b4e6SBenjamin Herrenschmidt { 726b9e5b4e6SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(irq); 7270ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 728b9e5b4e6SBenjamin Herrenschmidt 729b9e5b4e6SBenjamin Herrenschmidt #ifdef DEBUG_IRQ 730b9e5b4e6SBenjamin Herrenschmidt DBG("%s: end_irq: %d\n", mpic->name, irq); 731b9e5b4e6SBenjamin Herrenschmidt #endif 732b9e5b4e6SBenjamin Herrenschmidt /* We always EOI on end_irq() even for edge interrupts since that 733b9e5b4e6SBenjamin Herrenschmidt * should only lower the priority, the MPIC should have properly 734b9e5b4e6SBenjamin Herrenschmidt * latched another edge interrupt coming in anyway 735b9e5b4e6SBenjamin Herrenschmidt */ 736b9e5b4e6SBenjamin Herrenschmidt 737b9e5b4e6SBenjamin Herrenschmidt if (irq_desc[irq].status & IRQ_LEVEL) 738b9e5b4e6SBenjamin Herrenschmidt mpic_ht_end_irq(mpic, src); 739b9e5b4e6SBenjamin Herrenschmidt mpic_eoi(mpic); 740b9e5b4e6SBenjamin Herrenschmidt } 7416cfef5b2SMichael Ellerman #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 742b9e5b4e6SBenjamin Herrenschmidt 74314cf11afSPaul Mackerras #ifdef CONFIG_SMP 74414cf11afSPaul Mackerras 745b9e5b4e6SBenjamin Herrenschmidt static void mpic_unmask_ipi(unsigned int irq) 74614cf11afSPaul Mackerras { 74714cf11afSPaul Mackerras struct mpic *mpic = mpic_from_ipi(irq); 7487df2457dSOlof Johansson unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 74914cf11afSPaul Mackerras 75014cf11afSPaul Mackerras DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 75114cf11afSPaul Mackerras mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 75214cf11afSPaul Mackerras } 75314cf11afSPaul Mackerras 754b9e5b4e6SBenjamin Herrenschmidt static void mpic_mask_ipi(unsigned int irq) 75514cf11afSPaul Mackerras { 75614cf11afSPaul Mackerras /* NEVER disable an IPI... that's just plain wrong! */ 75714cf11afSPaul Mackerras } 75814cf11afSPaul Mackerras 75914cf11afSPaul Mackerras static void mpic_end_ipi(unsigned int irq) 76014cf11afSPaul Mackerras { 76114cf11afSPaul Mackerras struct mpic *mpic = mpic_from_ipi(irq); 76214cf11afSPaul Mackerras 76314cf11afSPaul Mackerras /* 76414cf11afSPaul Mackerras * IPIs are marked IRQ_PER_CPU. This has the side effect of 76514cf11afSPaul Mackerras * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 76614cf11afSPaul Mackerras * applying to them. We EOI them late to avoid re-entering. 7676714465eSThomas Gleixner * We mark IPI's with IRQF_DISABLED as they must run with 76814cf11afSPaul Mackerras * irqs disabled. 76914cf11afSPaul Mackerras */ 77014cf11afSPaul Mackerras mpic_eoi(mpic); 77114cf11afSPaul Mackerras } 77214cf11afSPaul Mackerras 77314cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 77414cf11afSPaul Mackerras 77517b5ee04SOlof Johansson void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) 77614cf11afSPaul Mackerras { 77714cf11afSPaul Mackerras struct mpic *mpic = mpic_from_irq(irq); 7780ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 77914cf11afSPaul Mackerras 78014cf11afSPaul Mackerras cpumask_t tmp; 78114cf11afSPaul Mackerras 78214cf11afSPaul Mackerras cpus_and(tmp, cpumask, cpu_online_map); 78314cf11afSPaul Mackerras 7847233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 78514cf11afSPaul Mackerras mpic_physmask(cpus_addr(tmp)[0])); 78614cf11afSPaul Mackerras } 78714cf11afSPaul Mackerras 7887233593bSZang Roy-r61911 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 7890ebfff14SBenjamin Herrenschmidt { 7900ebfff14SBenjamin Herrenschmidt /* Now convert sense value */ 7916e99e458SBenjamin Herrenschmidt switch(type & IRQ_TYPE_SENSE_MASK) { 7920ebfff14SBenjamin Herrenschmidt case IRQ_TYPE_EDGE_RISING: 7937233593bSZang Roy-r61911 return MPIC_INFO(VECPRI_SENSE_EDGE) | 7947233593bSZang Roy-r61911 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 7950ebfff14SBenjamin Herrenschmidt case IRQ_TYPE_EDGE_FALLING: 7966e99e458SBenjamin Herrenschmidt case IRQ_TYPE_EDGE_BOTH: 7977233593bSZang Roy-r61911 return MPIC_INFO(VECPRI_SENSE_EDGE) | 7987233593bSZang Roy-r61911 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 7990ebfff14SBenjamin Herrenschmidt case IRQ_TYPE_LEVEL_HIGH: 8007233593bSZang Roy-r61911 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 8017233593bSZang Roy-r61911 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 8020ebfff14SBenjamin Herrenschmidt case IRQ_TYPE_LEVEL_LOW: 8030ebfff14SBenjamin Herrenschmidt default: 8047233593bSZang Roy-r61911 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 8057233593bSZang Roy-r61911 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 8060ebfff14SBenjamin Herrenschmidt } 8076e99e458SBenjamin Herrenschmidt } 8086e99e458SBenjamin Herrenschmidt 80905af7bd2SMichael Ellerman int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 8106e99e458SBenjamin Herrenschmidt { 8116e99e458SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(virq); 8126e99e458SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(virq); 8136e99e458SBenjamin Herrenschmidt struct irq_desc *desc = get_irq_desc(virq); 8146e99e458SBenjamin Herrenschmidt unsigned int vecpri, vold, vnew; 8156e99e458SBenjamin Herrenschmidt 81606fe98e6SBenjamin Herrenschmidt DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 8176e99e458SBenjamin Herrenschmidt mpic, virq, src, flow_type); 8186e99e458SBenjamin Herrenschmidt 8196e99e458SBenjamin Herrenschmidt if (src >= mpic->irq_count) 8206e99e458SBenjamin Herrenschmidt return -EINVAL; 8216e99e458SBenjamin Herrenschmidt 8226e99e458SBenjamin Herrenschmidt if (flow_type == IRQ_TYPE_NONE) 8236e99e458SBenjamin Herrenschmidt if (mpic->senses && src < mpic->senses_count) 8246e99e458SBenjamin Herrenschmidt flow_type = mpic->senses[src]; 8256e99e458SBenjamin Herrenschmidt if (flow_type == IRQ_TYPE_NONE) 8266e99e458SBenjamin Herrenschmidt flow_type = IRQ_TYPE_LEVEL_LOW; 8276e99e458SBenjamin Herrenschmidt 8286e99e458SBenjamin Herrenschmidt desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 8296e99e458SBenjamin Herrenschmidt desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 8306e99e458SBenjamin Herrenschmidt if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 8316e99e458SBenjamin Herrenschmidt desc->status |= IRQ_LEVEL; 8326e99e458SBenjamin Herrenschmidt 8336e99e458SBenjamin Herrenschmidt if (mpic_is_ht_interrupt(mpic, src)) 8346e99e458SBenjamin Herrenschmidt vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 8356e99e458SBenjamin Herrenschmidt MPIC_VECPRI_SENSE_EDGE; 8366e99e458SBenjamin Herrenschmidt else 8377233593bSZang Roy-r61911 vecpri = mpic_type_to_vecpri(mpic, flow_type); 8386e99e458SBenjamin Herrenschmidt 8397233593bSZang Roy-r61911 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 8407233593bSZang Roy-r61911 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 8417233593bSZang Roy-r61911 MPIC_INFO(VECPRI_SENSE_MASK)); 8426e99e458SBenjamin Herrenschmidt vnew |= vecpri; 8436e99e458SBenjamin Herrenschmidt if (vold != vnew) 8447233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 8456e99e458SBenjamin Herrenschmidt 8466e99e458SBenjamin Herrenschmidt return 0; 8470ebfff14SBenjamin Herrenschmidt } 8480ebfff14SBenjamin Herrenschmidt 84938958dd9SOlof Johansson void mpic_set_vector(unsigned int virq, unsigned int vector) 85038958dd9SOlof Johansson { 85138958dd9SOlof Johansson struct mpic *mpic = mpic_from_irq(virq); 85238958dd9SOlof Johansson unsigned int src = mpic_irq_to_hw(virq); 85338958dd9SOlof Johansson unsigned int vecpri; 85438958dd9SOlof Johansson 85538958dd9SOlof Johansson DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", 85638958dd9SOlof Johansson mpic, virq, src, vector); 85738958dd9SOlof Johansson 85838958dd9SOlof Johansson if (src >= mpic->irq_count) 85938958dd9SOlof Johansson return; 86038958dd9SOlof Johansson 86138958dd9SOlof Johansson vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 86238958dd9SOlof Johansson vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); 86338958dd9SOlof Johansson vecpri |= vector; 86438958dd9SOlof Johansson mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 86538958dd9SOlof Johansson } 86638958dd9SOlof Johansson 867b9e5b4e6SBenjamin Herrenschmidt static struct irq_chip mpic_irq_chip = { 868b9e5b4e6SBenjamin Herrenschmidt .mask = mpic_mask_irq, 869b9e5b4e6SBenjamin Herrenschmidt .unmask = mpic_unmask_irq, 870b9e5b4e6SBenjamin Herrenschmidt .eoi = mpic_end_irq, 8716e99e458SBenjamin Herrenschmidt .set_type = mpic_set_irq_type, 872b9e5b4e6SBenjamin Herrenschmidt }; 873b9e5b4e6SBenjamin Herrenschmidt 874b9e5b4e6SBenjamin Herrenschmidt #ifdef CONFIG_SMP 875b9e5b4e6SBenjamin Herrenschmidt static struct irq_chip mpic_ipi_chip = { 876b9e5b4e6SBenjamin Herrenschmidt .mask = mpic_mask_ipi, 877b9e5b4e6SBenjamin Herrenschmidt .unmask = mpic_unmask_ipi, 878b9e5b4e6SBenjamin Herrenschmidt .eoi = mpic_end_ipi, 879b9e5b4e6SBenjamin Herrenschmidt }; 880b9e5b4e6SBenjamin Herrenschmidt #endif /* CONFIG_SMP */ 881b9e5b4e6SBenjamin Herrenschmidt 8826cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 883b9e5b4e6SBenjamin Herrenschmidt static struct irq_chip mpic_irq_ht_chip = { 884b9e5b4e6SBenjamin Herrenschmidt .startup = mpic_startup_ht_irq, 885b9e5b4e6SBenjamin Herrenschmidt .shutdown = mpic_shutdown_ht_irq, 886b9e5b4e6SBenjamin Herrenschmidt .mask = mpic_mask_irq, 887b9e5b4e6SBenjamin Herrenschmidt .unmask = mpic_unmask_ht_irq, 888b9e5b4e6SBenjamin Herrenschmidt .eoi = mpic_end_ht_irq, 8896e99e458SBenjamin Herrenschmidt .set_type = mpic_set_irq_type, 890b9e5b4e6SBenjamin Herrenschmidt }; 8916cfef5b2SMichael Ellerman #endif /* CONFIG_MPIC_U3_HT_IRQS */ 892b9e5b4e6SBenjamin Herrenschmidt 89314cf11afSPaul Mackerras 8940ebfff14SBenjamin Herrenschmidt static int mpic_host_match(struct irq_host *h, struct device_node *node) 8950ebfff14SBenjamin Herrenschmidt { 8960ebfff14SBenjamin Herrenschmidt /* Exact match, unless mpic node is NULL */ 89752964f87SMichael Ellerman return h->of_node == NULL || h->of_node == node; 8980ebfff14SBenjamin Herrenschmidt } 8990ebfff14SBenjamin Herrenschmidt 9000ebfff14SBenjamin Herrenschmidt static int mpic_host_map(struct irq_host *h, unsigned int virq, 9016e99e458SBenjamin Herrenschmidt irq_hw_number_t hw) 9020ebfff14SBenjamin Herrenschmidt { 9030ebfff14SBenjamin Herrenschmidt struct mpic *mpic = h->host_data; 9046e99e458SBenjamin Herrenschmidt struct irq_chip *chip; 9050ebfff14SBenjamin Herrenschmidt 90606fe98e6SBenjamin Herrenschmidt DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 9070ebfff14SBenjamin Herrenschmidt 9087df2457dSOlof Johansson if (hw == mpic->spurious_vec) 9090ebfff14SBenjamin Herrenschmidt return -EINVAL; 9107fd72186SBenjamin Herrenschmidt if (mpic->protected && test_bit(hw, mpic->protected)) 9117fd72186SBenjamin Herrenschmidt return -EINVAL; 91206fe98e6SBenjamin Herrenschmidt 9130ebfff14SBenjamin Herrenschmidt #ifdef CONFIG_SMP 9147df2457dSOlof Johansson else if (hw >= mpic->ipi_vecs[0]) { 9150ebfff14SBenjamin Herrenschmidt WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 9160ebfff14SBenjamin Herrenschmidt 91706fe98e6SBenjamin Herrenschmidt DBG("mpic: mapping as IPI\n"); 9180ebfff14SBenjamin Herrenschmidt set_irq_chip_data(virq, mpic); 9190ebfff14SBenjamin Herrenschmidt set_irq_chip_and_handler(virq, &mpic->hc_ipi, 9200ebfff14SBenjamin Herrenschmidt handle_percpu_irq); 9210ebfff14SBenjamin Herrenschmidt return 0; 9220ebfff14SBenjamin Herrenschmidt } 9230ebfff14SBenjamin Herrenschmidt #endif /* CONFIG_SMP */ 9240ebfff14SBenjamin Herrenschmidt 9250ebfff14SBenjamin Herrenschmidt if (hw >= mpic->irq_count) 9260ebfff14SBenjamin Herrenschmidt return -EINVAL; 9270ebfff14SBenjamin Herrenschmidt 928a7de7c74SMichael Ellerman mpic_msi_reserve_hwirq(mpic, hw); 929a7de7c74SMichael Ellerman 9306e99e458SBenjamin Herrenschmidt /* Default chip */ 9310ebfff14SBenjamin Herrenschmidt chip = &mpic->hc_irq; 9320ebfff14SBenjamin Herrenschmidt 9336cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 9340ebfff14SBenjamin Herrenschmidt /* Check for HT interrupts, override vecpri */ 9356e99e458SBenjamin Herrenschmidt if (mpic_is_ht_interrupt(mpic, hw)) 9360ebfff14SBenjamin Herrenschmidt chip = &mpic->hc_ht_irq; 9376cfef5b2SMichael Ellerman #endif /* CONFIG_MPIC_U3_HT_IRQS */ 9380ebfff14SBenjamin Herrenschmidt 93906fe98e6SBenjamin Herrenschmidt DBG("mpic: mapping to irq chip @%p\n", chip); 9400ebfff14SBenjamin Herrenschmidt 9410ebfff14SBenjamin Herrenschmidt set_irq_chip_data(virq, mpic); 9420ebfff14SBenjamin Herrenschmidt set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 9436e99e458SBenjamin Herrenschmidt 9446e99e458SBenjamin Herrenschmidt /* Set default irq type */ 9456e99e458SBenjamin Herrenschmidt set_irq_type(virq, IRQ_TYPE_NONE); 9466e99e458SBenjamin Herrenschmidt 9470ebfff14SBenjamin Herrenschmidt return 0; 9480ebfff14SBenjamin Herrenschmidt } 9490ebfff14SBenjamin Herrenschmidt 9500ebfff14SBenjamin Herrenschmidt static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 9510ebfff14SBenjamin Herrenschmidt u32 *intspec, unsigned int intsize, 9520ebfff14SBenjamin Herrenschmidt irq_hw_number_t *out_hwirq, unsigned int *out_flags) 9530ebfff14SBenjamin Herrenschmidt 9540ebfff14SBenjamin Herrenschmidt { 9550ebfff14SBenjamin Herrenschmidt static unsigned char map_mpic_senses[4] = { 9560ebfff14SBenjamin Herrenschmidt IRQ_TYPE_EDGE_RISING, 9570ebfff14SBenjamin Herrenschmidt IRQ_TYPE_LEVEL_LOW, 9580ebfff14SBenjamin Herrenschmidt IRQ_TYPE_LEVEL_HIGH, 9590ebfff14SBenjamin Herrenschmidt IRQ_TYPE_EDGE_FALLING, 9600ebfff14SBenjamin Herrenschmidt }; 9610ebfff14SBenjamin Herrenschmidt 9620ebfff14SBenjamin Herrenschmidt *out_hwirq = intspec[0]; 96306fe98e6SBenjamin Herrenschmidt if (intsize > 1) { 96406fe98e6SBenjamin Herrenschmidt u32 mask = 0x3; 96506fe98e6SBenjamin Herrenschmidt 96606fe98e6SBenjamin Herrenschmidt /* Apple invented a new race of encoding on machines with 96706fe98e6SBenjamin Herrenschmidt * an HT APIC. They encode, among others, the index within 96806fe98e6SBenjamin Herrenschmidt * the HT APIC. We don't care about it here since thankfully, 96906fe98e6SBenjamin Herrenschmidt * it appears that they have the APIC already properly 97006fe98e6SBenjamin Herrenschmidt * configured, and thus our current fixup code that reads the 97106fe98e6SBenjamin Herrenschmidt * APIC config works fine. However, we still need to mask out 97206fe98e6SBenjamin Herrenschmidt * bits in the specifier to make sure we only get bit 0 which 97306fe98e6SBenjamin Herrenschmidt * is the level/edge bit (the only sense bit exposed by Apple), 97406fe98e6SBenjamin Herrenschmidt * as their bit 1 means something else. 97506fe98e6SBenjamin Herrenschmidt */ 97606fe98e6SBenjamin Herrenschmidt if (machine_is(powermac)) 97706fe98e6SBenjamin Herrenschmidt mask = 0x1; 97806fe98e6SBenjamin Herrenschmidt *out_flags = map_mpic_senses[intspec[1] & mask]; 97906fe98e6SBenjamin Herrenschmidt } else 9800ebfff14SBenjamin Herrenschmidt *out_flags = IRQ_TYPE_NONE; 9810ebfff14SBenjamin Herrenschmidt 98206fe98e6SBenjamin Herrenschmidt DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 98306fe98e6SBenjamin Herrenschmidt intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 98406fe98e6SBenjamin Herrenschmidt 9850ebfff14SBenjamin Herrenschmidt return 0; 9860ebfff14SBenjamin Herrenschmidt } 9870ebfff14SBenjamin Herrenschmidt 9880ebfff14SBenjamin Herrenschmidt static struct irq_host_ops mpic_host_ops = { 9890ebfff14SBenjamin Herrenschmidt .match = mpic_host_match, 9900ebfff14SBenjamin Herrenschmidt .map = mpic_host_map, 9910ebfff14SBenjamin Herrenschmidt .xlate = mpic_host_xlate, 9920ebfff14SBenjamin Herrenschmidt }; 9930ebfff14SBenjamin Herrenschmidt 99414cf11afSPaul Mackerras /* 99514cf11afSPaul Mackerras * Exported functions 99614cf11afSPaul Mackerras */ 99714cf11afSPaul Mackerras 9980ebfff14SBenjamin Herrenschmidt struct mpic * __init mpic_alloc(struct device_node *node, 999a959ff56SBenjamin Herrenschmidt phys_addr_t phys_addr, 100014cf11afSPaul Mackerras unsigned int flags, 100114cf11afSPaul Mackerras unsigned int isu_size, 100214cf11afSPaul Mackerras unsigned int irq_count, 100314cf11afSPaul Mackerras const char *name) 100414cf11afSPaul Mackerras { 100514cf11afSPaul Mackerras struct mpic *mpic; 1006*d9d1063dSJohannes Berg u32 greg_feature; 100714cf11afSPaul Mackerras const char *vers; 100814cf11afSPaul Mackerras int i; 10097df2457dSOlof Johansson int intvec_top; 1010a959ff56SBenjamin Herrenschmidt u64 paddr = phys_addr; 101114cf11afSPaul Mackerras 101214cf11afSPaul Mackerras mpic = alloc_bootmem(sizeof(struct mpic)); 101314cf11afSPaul Mackerras if (mpic == NULL) 101414cf11afSPaul Mackerras return NULL; 101514cf11afSPaul Mackerras 101614cf11afSPaul Mackerras memset(mpic, 0, sizeof(struct mpic)); 101714cf11afSPaul Mackerras mpic->name = name; 101814cf11afSPaul Mackerras 101952964f87SMichael Ellerman mpic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR, 102052964f87SMichael Ellerman isu_size, &mpic_host_ops, 10217df2457dSOlof Johansson flags & MPIC_LARGE_VECTORS ? 2048 : 256); 10220ebfff14SBenjamin Herrenschmidt if (mpic->irqhost == NULL) { 10230ebfff14SBenjamin Herrenschmidt of_node_put(node); 10240ebfff14SBenjamin Herrenschmidt return NULL; 10250ebfff14SBenjamin Herrenschmidt } 10260ebfff14SBenjamin Herrenschmidt 10270ebfff14SBenjamin Herrenschmidt mpic->irqhost->host_data = mpic; 1028b9e5b4e6SBenjamin Herrenschmidt mpic->hc_irq = mpic_irq_chip; 102914cf11afSPaul Mackerras mpic->hc_irq.typename = name; 103014cf11afSPaul Mackerras if (flags & MPIC_PRIMARY) 103114cf11afSPaul Mackerras mpic->hc_irq.set_affinity = mpic_set_affinity; 10326cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 1033b9e5b4e6SBenjamin Herrenschmidt mpic->hc_ht_irq = mpic_irq_ht_chip; 1034b9e5b4e6SBenjamin Herrenschmidt mpic->hc_ht_irq.typename = name; 1035b9e5b4e6SBenjamin Herrenschmidt if (flags & MPIC_PRIMARY) 1036b9e5b4e6SBenjamin Herrenschmidt mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 10376cfef5b2SMichael Ellerman #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1038fbf0274eSBenjamin Herrenschmidt 103914cf11afSPaul Mackerras #ifdef CONFIG_SMP 1040b9e5b4e6SBenjamin Herrenschmidt mpic->hc_ipi = mpic_ipi_chip; 10410ebfff14SBenjamin Herrenschmidt mpic->hc_ipi.typename = name; 104214cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 104314cf11afSPaul Mackerras 104414cf11afSPaul Mackerras mpic->flags = flags; 104514cf11afSPaul Mackerras mpic->isu_size = isu_size; 104614cf11afSPaul Mackerras mpic->irq_count = irq_count; 104714cf11afSPaul Mackerras mpic->num_sources = 0; /* so far */ 104814cf11afSPaul Mackerras 10497df2457dSOlof Johansson if (flags & MPIC_LARGE_VECTORS) 10507df2457dSOlof Johansson intvec_top = 2047; 10517df2457dSOlof Johansson else 10527df2457dSOlof Johansson intvec_top = 255; 10537df2457dSOlof Johansson 10547df2457dSOlof Johansson mpic->timer_vecs[0] = intvec_top - 8; 10557df2457dSOlof Johansson mpic->timer_vecs[1] = intvec_top - 7; 10567df2457dSOlof Johansson mpic->timer_vecs[2] = intvec_top - 6; 10577df2457dSOlof Johansson mpic->timer_vecs[3] = intvec_top - 5; 10587df2457dSOlof Johansson mpic->ipi_vecs[0] = intvec_top - 4; 10597df2457dSOlof Johansson mpic->ipi_vecs[1] = intvec_top - 3; 10607df2457dSOlof Johansson mpic->ipi_vecs[2] = intvec_top - 2; 10617df2457dSOlof Johansson mpic->ipi_vecs[3] = intvec_top - 1; 10627df2457dSOlof Johansson mpic->spurious_vec = intvec_top; 10637df2457dSOlof Johansson 1064a959ff56SBenjamin Herrenschmidt /* Check for "big-endian" in device-tree */ 1065e2eb6392SStephen Rothwell if (node && of_get_property(node, "big-endian", NULL) != NULL) 1066a959ff56SBenjamin Herrenschmidt mpic->flags |= MPIC_BIG_ENDIAN; 1067a959ff56SBenjamin Herrenschmidt 10687fd72186SBenjamin Herrenschmidt /* Look for protected sources */ 10697fd72186SBenjamin Herrenschmidt if (node) { 1070*d9d1063dSJohannes Berg int psize; 1071*d9d1063dSJohannes Berg unsigned int bits, mapsize; 10727fd72186SBenjamin Herrenschmidt const u32 *psrc = 10737fd72186SBenjamin Herrenschmidt of_get_property(node, "protected-sources", &psize); 10747fd72186SBenjamin Herrenschmidt if (psrc) { 10757fd72186SBenjamin Herrenschmidt psize /= 4; 10767fd72186SBenjamin Herrenschmidt bits = intvec_top + 1; 10777fd72186SBenjamin Herrenschmidt mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); 10787fd72186SBenjamin Herrenschmidt mpic->protected = alloc_bootmem(mapsize); 10797fd72186SBenjamin Herrenschmidt BUG_ON(mpic->protected == NULL); 10807fd72186SBenjamin Herrenschmidt memset(mpic->protected, 0, mapsize); 10817fd72186SBenjamin Herrenschmidt for (i = 0; i < psize; i++) { 10827fd72186SBenjamin Herrenschmidt if (psrc[i] > intvec_top) 10837fd72186SBenjamin Herrenschmidt continue; 10847fd72186SBenjamin Herrenschmidt __set_bit(psrc[i], mpic->protected); 10857fd72186SBenjamin Herrenschmidt } 10867fd72186SBenjamin Herrenschmidt } 10877fd72186SBenjamin Herrenschmidt } 1088a959ff56SBenjamin Herrenschmidt 10897233593bSZang Roy-r61911 #ifdef CONFIG_MPIC_WEIRD 10907233593bSZang Roy-r61911 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 10917233593bSZang Roy-r61911 #endif 10927233593bSZang Roy-r61911 1093fbf0274eSBenjamin Herrenschmidt /* default register type */ 1094fbf0274eSBenjamin Herrenschmidt mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 1095fbf0274eSBenjamin Herrenschmidt mpic_access_mmio_be : mpic_access_mmio_le; 1096fbf0274eSBenjamin Herrenschmidt 1097a959ff56SBenjamin Herrenschmidt /* If no physical address is passed in, a device-node is mandatory */ 1098a959ff56SBenjamin Herrenschmidt BUG_ON(paddr == 0 && node == NULL); 1099a959ff56SBenjamin Herrenschmidt 1100a959ff56SBenjamin Herrenschmidt /* If no physical address passed in, check if it's dcr based */ 11010411a5e2SMichael Ellerman if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { 1102fbf0274eSBenjamin Herrenschmidt #ifdef CONFIG_PPC_DCR 11030411a5e2SMichael Ellerman mpic->flags |= MPIC_USES_DCR; 1104fbf0274eSBenjamin Herrenschmidt mpic->reg_type = mpic_access_dcr; 1105fbf0274eSBenjamin Herrenschmidt #else 11060411a5e2SMichael Ellerman BUG(); 1107fbf0274eSBenjamin Herrenschmidt #endif /* CONFIG_PPC_DCR */ 11080411a5e2SMichael Ellerman } 1109fbf0274eSBenjamin Herrenschmidt 1110a959ff56SBenjamin Herrenschmidt /* If the MPIC is not DCR based, and no physical address was passed 1111a959ff56SBenjamin Herrenschmidt * in, try to obtain one 1112a959ff56SBenjamin Herrenschmidt */ 1113a959ff56SBenjamin Herrenschmidt if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1114*d9d1063dSJohannes Berg const u32 *reg = of_get_property(node, "reg", NULL); 1115a959ff56SBenjamin Herrenschmidt BUG_ON(reg == NULL); 1116a959ff56SBenjamin Herrenschmidt paddr = of_translate_address(node, reg); 1117a959ff56SBenjamin Herrenschmidt BUG_ON(paddr == OF_BAD_ADDR); 1118a959ff56SBenjamin Herrenschmidt } 1119a959ff56SBenjamin Herrenschmidt 112014cf11afSPaul Mackerras /* Map the global registers */ 1121a959ff56SBenjamin Herrenschmidt mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1122a959ff56SBenjamin Herrenschmidt mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 112314cf11afSPaul Mackerras 112414cf11afSPaul Mackerras /* Reset */ 112514cf11afSPaul Mackerras if (flags & MPIC_WANTS_RESET) { 11267233593bSZang Roy-r61911 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 11277233593bSZang Roy-r61911 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 112814cf11afSPaul Mackerras | MPIC_GREG_GCONF_RESET); 11297233593bSZang Roy-r61911 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 113014cf11afSPaul Mackerras & MPIC_GREG_GCONF_RESET) 113114cf11afSPaul Mackerras mb(); 113214cf11afSPaul Mackerras } 113314cf11afSPaul Mackerras 1134f365355eSOlof Johansson if (flags & MPIC_ENABLE_MCK) 1135f365355eSOlof Johansson mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1136f365355eSOlof Johansson mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1137f365355eSOlof Johansson | MPIC_GREG_GCONF_MCK); 1138f365355eSOlof Johansson 113914cf11afSPaul Mackerras /* Read feature register, calculate num CPUs and, for non-ISU 114014cf11afSPaul Mackerras * MPICs, num sources as well. On ISU MPICs, sources are counted 114114cf11afSPaul Mackerras * as ISUs are added 114214cf11afSPaul Mackerras */ 1143*d9d1063dSJohannes Berg greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1144*d9d1063dSJohannes Berg mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) 114514cf11afSPaul Mackerras >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 114614cf11afSPaul Mackerras if (isu_size == 0) 1147*d9d1063dSJohannes Berg mpic->num_sources = 1148*d9d1063dSJohannes Berg ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) 114914cf11afSPaul Mackerras >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 115014cf11afSPaul Mackerras 115114cf11afSPaul Mackerras /* Map the per-CPU registers */ 115214cf11afSPaul Mackerras for (i = 0; i < mpic->num_cpus; i++) { 1153a959ff56SBenjamin Herrenschmidt mpic_map(mpic, paddr, &mpic->cpuregs[i], 1154fbf0274eSBenjamin Herrenschmidt MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1155fbf0274eSBenjamin Herrenschmidt 0x1000); 115614cf11afSPaul Mackerras } 115714cf11afSPaul Mackerras 115814cf11afSPaul Mackerras /* Initialize main ISU if none provided */ 115914cf11afSPaul Mackerras if (mpic->isu_size == 0) { 116014cf11afSPaul Mackerras mpic->isu_size = mpic->num_sources; 1161a959ff56SBenjamin Herrenschmidt mpic_map(mpic, paddr, &mpic->isus[0], 1162fbf0274eSBenjamin Herrenschmidt MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 116314cf11afSPaul Mackerras } 116414cf11afSPaul Mackerras mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 116514cf11afSPaul Mackerras mpic->isu_mask = (1 << mpic->isu_shift) - 1; 116614cf11afSPaul Mackerras 116714cf11afSPaul Mackerras /* Display version */ 1168*d9d1063dSJohannes Berg switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { 116914cf11afSPaul Mackerras case 1: 117014cf11afSPaul Mackerras vers = "1.0"; 117114cf11afSPaul Mackerras break; 117214cf11afSPaul Mackerras case 2: 117314cf11afSPaul Mackerras vers = "1.2"; 117414cf11afSPaul Mackerras break; 117514cf11afSPaul Mackerras case 3: 117614cf11afSPaul Mackerras vers = "1.3"; 117714cf11afSPaul Mackerras break; 117814cf11afSPaul Mackerras default: 117914cf11afSPaul Mackerras vers = "<unknown>"; 118014cf11afSPaul Mackerras break; 118114cf11afSPaul Mackerras } 1182a959ff56SBenjamin Herrenschmidt printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1183a959ff56SBenjamin Herrenschmidt " max %d CPUs\n", 1184a959ff56SBenjamin Herrenschmidt name, vers, (unsigned long long)paddr, mpic->num_cpus); 1185a959ff56SBenjamin Herrenschmidt printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1186a959ff56SBenjamin Herrenschmidt mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 118714cf11afSPaul Mackerras 118814cf11afSPaul Mackerras mpic->next = mpics; 118914cf11afSPaul Mackerras mpics = mpic; 119014cf11afSPaul Mackerras 11910ebfff14SBenjamin Herrenschmidt if (flags & MPIC_PRIMARY) { 119214cf11afSPaul Mackerras mpic_primary = mpic; 11930ebfff14SBenjamin Herrenschmidt irq_set_default_host(mpic->irqhost); 11940ebfff14SBenjamin Herrenschmidt } 119514cf11afSPaul Mackerras 119614cf11afSPaul Mackerras return mpic; 119714cf11afSPaul Mackerras } 119814cf11afSPaul Mackerras 119914cf11afSPaul Mackerras void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1200a959ff56SBenjamin Herrenschmidt phys_addr_t paddr) 120114cf11afSPaul Mackerras { 120214cf11afSPaul Mackerras unsigned int isu_first = isu_num * mpic->isu_size; 120314cf11afSPaul Mackerras 120414cf11afSPaul Mackerras BUG_ON(isu_num >= MPIC_MAX_ISU); 120514cf11afSPaul Mackerras 1206a959ff56SBenjamin Herrenschmidt mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, 12077233593bSZang Roy-r61911 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 120814cf11afSPaul Mackerras if ((isu_first + mpic->isu_size) > mpic->num_sources) 120914cf11afSPaul Mackerras mpic->num_sources = isu_first + mpic->isu_size; 121014cf11afSPaul Mackerras } 121114cf11afSPaul Mackerras 12120ebfff14SBenjamin Herrenschmidt void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 12130ebfff14SBenjamin Herrenschmidt { 12140ebfff14SBenjamin Herrenschmidt mpic->senses = senses; 12150ebfff14SBenjamin Herrenschmidt mpic->senses_count = count; 12160ebfff14SBenjamin Herrenschmidt } 12170ebfff14SBenjamin Herrenschmidt 121814cf11afSPaul Mackerras void __init mpic_init(struct mpic *mpic) 121914cf11afSPaul Mackerras { 122014cf11afSPaul Mackerras int i; 122114cf11afSPaul Mackerras 122214cf11afSPaul Mackerras BUG_ON(mpic->num_sources == 0); 122314cf11afSPaul Mackerras 122414cf11afSPaul Mackerras printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 122514cf11afSPaul Mackerras 122614cf11afSPaul Mackerras /* Set current processor priority to max */ 12277233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 122814cf11afSPaul Mackerras 122914cf11afSPaul Mackerras /* Initialize timers: just disable them all */ 123014cf11afSPaul Mackerras for (i = 0; i < 4; i++) { 123114cf11afSPaul Mackerras mpic_write(mpic->tmregs, 12327233593bSZang Roy-r61911 i * MPIC_INFO(TIMER_STRIDE) + 12337233593bSZang Roy-r61911 MPIC_INFO(TIMER_DESTINATION), 0); 123414cf11afSPaul Mackerras mpic_write(mpic->tmregs, 12357233593bSZang Roy-r61911 i * MPIC_INFO(TIMER_STRIDE) + 12367233593bSZang Roy-r61911 MPIC_INFO(TIMER_VECTOR_PRI), 123714cf11afSPaul Mackerras MPIC_VECPRI_MASK | 12387df2457dSOlof Johansson (mpic->timer_vecs[0] + i)); 123914cf11afSPaul Mackerras } 124014cf11afSPaul Mackerras 124114cf11afSPaul Mackerras /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 124214cf11afSPaul Mackerras mpic_test_broken_ipi(mpic); 124314cf11afSPaul Mackerras for (i = 0; i < 4; i++) { 124414cf11afSPaul Mackerras mpic_ipi_write(i, 124514cf11afSPaul Mackerras MPIC_VECPRI_MASK | 124614cf11afSPaul Mackerras (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 12477df2457dSOlof Johansson (mpic->ipi_vecs[0] + i)); 124814cf11afSPaul Mackerras } 124914cf11afSPaul Mackerras 125014cf11afSPaul Mackerras /* Initialize interrupt sources */ 125114cf11afSPaul Mackerras if (mpic->irq_count == 0) 125214cf11afSPaul Mackerras mpic->irq_count = mpic->num_sources; 125314cf11afSPaul Mackerras 12541beb6a7dSBenjamin Herrenschmidt /* Do the HT PIC fixups on U3 broken mpic */ 125514cf11afSPaul Mackerras DBG("MPIC flags: %x\n", mpic->flags); 125605af7bd2SMichael Ellerman if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { 12571beb6a7dSBenjamin Herrenschmidt mpic_scan_ht_pics(mpic); 125805af7bd2SMichael Ellerman mpic_u3msi_init(mpic); 125905af7bd2SMichael Ellerman } 126014cf11afSPaul Mackerras 126138958dd9SOlof Johansson mpic_pasemi_msi_init(mpic); 126238958dd9SOlof Johansson 126314cf11afSPaul Mackerras for (i = 0; i < mpic->num_sources; i++) { 126414cf11afSPaul Mackerras /* start with vector = source number, and masked */ 12656e99e458SBenjamin Herrenschmidt u32 vecpri = MPIC_VECPRI_MASK | i | 12666e99e458SBenjamin Herrenschmidt (8 << MPIC_VECPRI_PRIORITY_SHIFT); 126714cf11afSPaul Mackerras 12687fd72186SBenjamin Herrenschmidt /* check if protected */ 12697fd72186SBenjamin Herrenschmidt if (mpic->protected && test_bit(i, mpic->protected)) 12707fd72186SBenjamin Herrenschmidt continue; 127114cf11afSPaul Mackerras /* init hw */ 12727233593bSZang Roy-r61911 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 12737233593bSZang Roy-r61911 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 127414cf11afSPaul Mackerras 1 << hard_smp_processor_id()); 127514cf11afSPaul Mackerras } 127614cf11afSPaul Mackerras 12777df2457dSOlof Johansson /* Init spurious vector */ 12787df2457dSOlof Johansson mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 127914cf11afSPaul Mackerras 12807233593bSZang Roy-r61911 /* Disable 8259 passthrough, if supported */ 12817233593bSZang Roy-r61911 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 12827233593bSZang Roy-r61911 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 12837233593bSZang Roy-r61911 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 128414cf11afSPaul Mackerras | MPIC_GREG_GCONF_8259_PTHROU_DIS); 128514cf11afSPaul Mackerras 1286d87bf3beSOlof Johansson if (mpic->flags & MPIC_NO_BIAS) 1287d87bf3beSOlof Johansson mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1288d87bf3beSOlof Johansson mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1289d87bf3beSOlof Johansson | MPIC_GREG_GCONF_NO_BIAS); 1290d87bf3beSOlof Johansson 129114cf11afSPaul Mackerras /* Set current processor priority to 0 */ 12927233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 12933669e930SJohannes Berg 12943669e930SJohannes Berg #ifdef CONFIG_PM 12953669e930SJohannes Berg /* allocate memory to save mpic state */ 12963669e930SJohannes Berg mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save)); 12973669e930SJohannes Berg BUG_ON(mpic->save_data == NULL); 12983669e930SJohannes Berg #endif 129914cf11afSPaul Mackerras } 130014cf11afSPaul Mackerras 1301868ea0c9SMark A. Greer void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1302868ea0c9SMark A. Greer { 1303868ea0c9SMark A. Greer u32 v; 130414cf11afSPaul Mackerras 1305868ea0c9SMark A. Greer v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1306868ea0c9SMark A. Greer v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1307868ea0c9SMark A. Greer v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1308868ea0c9SMark A. Greer mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1309868ea0c9SMark A. Greer } 1310868ea0c9SMark A. Greer 1311868ea0c9SMark A. Greer void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1312868ea0c9SMark A. Greer { 1313ba1826e5SBenjamin Herrenschmidt unsigned long flags; 1314868ea0c9SMark A. Greer u32 v; 1315868ea0c9SMark A. Greer 1316ba1826e5SBenjamin Herrenschmidt spin_lock_irqsave(&mpic_lock, flags); 1317868ea0c9SMark A. Greer v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1318868ea0c9SMark A. Greer if (enable) 1319868ea0c9SMark A. Greer v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1320868ea0c9SMark A. Greer else 1321868ea0c9SMark A. Greer v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1322868ea0c9SMark A. Greer mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1323ba1826e5SBenjamin Herrenschmidt spin_unlock_irqrestore(&mpic_lock, flags); 1324868ea0c9SMark A. Greer } 132514cf11afSPaul Mackerras 132614cf11afSPaul Mackerras void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 132714cf11afSPaul Mackerras { 1328*d9d1063dSJohannes Berg unsigned int is_ipi; 132914cf11afSPaul Mackerras struct mpic *mpic = mpic_find(irq, &is_ipi); 13300ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 133114cf11afSPaul Mackerras unsigned long flags; 133214cf11afSPaul Mackerras u32 reg; 133314cf11afSPaul Mackerras 133414cf11afSPaul Mackerras spin_lock_irqsave(&mpic_lock, flags); 133514cf11afSPaul Mackerras if (is_ipi) { 13367df2457dSOlof Johansson reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1337e5356640SBenjamin Herrenschmidt ~MPIC_VECPRI_PRIORITY_MASK; 13387df2457dSOlof Johansson mpic_ipi_write(src - mpic->ipi_vecs[0], 133914cf11afSPaul Mackerras reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 134014cf11afSPaul Mackerras } else { 13417233593bSZang Roy-r61911 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1342e5356640SBenjamin Herrenschmidt & ~MPIC_VECPRI_PRIORITY_MASK; 13437233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 134414cf11afSPaul Mackerras reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 134514cf11afSPaul Mackerras } 134614cf11afSPaul Mackerras spin_unlock_irqrestore(&mpic_lock, flags); 134714cf11afSPaul Mackerras } 134814cf11afSPaul Mackerras 134914cf11afSPaul Mackerras unsigned int mpic_irq_get_priority(unsigned int irq) 135014cf11afSPaul Mackerras { 1351*d9d1063dSJohannes Berg unsigned int is_ipi; 135214cf11afSPaul Mackerras struct mpic *mpic = mpic_find(irq, &is_ipi); 13530ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 135414cf11afSPaul Mackerras unsigned long flags; 135514cf11afSPaul Mackerras u32 reg; 135614cf11afSPaul Mackerras 135714cf11afSPaul Mackerras spin_lock_irqsave(&mpic_lock, flags); 135814cf11afSPaul Mackerras if (is_ipi) 13597df2457dSOlof Johansson reg = mpic_ipi_read(src = mpic->ipi_vecs[0]); 136014cf11afSPaul Mackerras else 13617233593bSZang Roy-r61911 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 136214cf11afSPaul Mackerras spin_unlock_irqrestore(&mpic_lock, flags); 136314cf11afSPaul Mackerras return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 136414cf11afSPaul Mackerras } 136514cf11afSPaul Mackerras 136614cf11afSPaul Mackerras void mpic_setup_this_cpu(void) 136714cf11afSPaul Mackerras { 136814cf11afSPaul Mackerras #ifdef CONFIG_SMP 136914cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 137014cf11afSPaul Mackerras unsigned long flags; 137114cf11afSPaul Mackerras u32 msk = 1 << hard_smp_processor_id(); 137214cf11afSPaul Mackerras unsigned int i; 137314cf11afSPaul Mackerras 137414cf11afSPaul Mackerras BUG_ON(mpic == NULL); 137514cf11afSPaul Mackerras 137614cf11afSPaul Mackerras DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 137714cf11afSPaul Mackerras 137814cf11afSPaul Mackerras spin_lock_irqsave(&mpic_lock, flags); 137914cf11afSPaul Mackerras 138014cf11afSPaul Mackerras /* let the mpic know we want intrs. default affinity is 0xffffffff 138114cf11afSPaul Mackerras * until changed via /proc. That's how it's done on x86. If we want 138214cf11afSPaul Mackerras * it differently, then we should make sure we also change the default 1383a53da52fSIngo Molnar * values of irq_desc[].affinity in irq.c. 138414cf11afSPaul Mackerras */ 138514cf11afSPaul Mackerras if (distribute_irqs) { 138614cf11afSPaul Mackerras for (i = 0; i < mpic->num_sources ; i++) 13877233593bSZang Roy-r61911 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 13887233593bSZang Roy-r61911 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 138914cf11afSPaul Mackerras } 139014cf11afSPaul Mackerras 139114cf11afSPaul Mackerras /* Set current processor priority to 0 */ 13927233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 139314cf11afSPaul Mackerras 139414cf11afSPaul Mackerras spin_unlock_irqrestore(&mpic_lock, flags); 139514cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 139614cf11afSPaul Mackerras } 139714cf11afSPaul Mackerras 139814cf11afSPaul Mackerras int mpic_cpu_get_priority(void) 139914cf11afSPaul Mackerras { 140014cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 140114cf11afSPaul Mackerras 14027233593bSZang Roy-r61911 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 140314cf11afSPaul Mackerras } 140414cf11afSPaul Mackerras 140514cf11afSPaul Mackerras void mpic_cpu_set_priority(int prio) 140614cf11afSPaul Mackerras { 140714cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 140814cf11afSPaul Mackerras 140914cf11afSPaul Mackerras prio &= MPIC_CPU_TASKPRI_MASK; 14107233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 141114cf11afSPaul Mackerras } 141214cf11afSPaul Mackerras 141314cf11afSPaul Mackerras /* 141414cf11afSPaul Mackerras * XXX: someone who knows mpic should check this. 141514cf11afSPaul Mackerras * do we need to eoi the ipi including for kexec cpu here (see xics comments)? 141614cf11afSPaul Mackerras * or can we reset the mpic in the new kernel? 141714cf11afSPaul Mackerras */ 141814cf11afSPaul Mackerras void mpic_teardown_this_cpu(int secondary) 141914cf11afSPaul Mackerras { 142014cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 142114cf11afSPaul Mackerras unsigned long flags; 142214cf11afSPaul Mackerras u32 msk = 1 << hard_smp_processor_id(); 142314cf11afSPaul Mackerras unsigned int i; 142414cf11afSPaul Mackerras 142514cf11afSPaul Mackerras BUG_ON(mpic == NULL); 142614cf11afSPaul Mackerras 142714cf11afSPaul Mackerras DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 142814cf11afSPaul Mackerras spin_lock_irqsave(&mpic_lock, flags); 142914cf11afSPaul Mackerras 143014cf11afSPaul Mackerras /* let the mpic know we don't want intrs. */ 143114cf11afSPaul Mackerras for (i = 0; i < mpic->num_sources ; i++) 14327233593bSZang Roy-r61911 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 14337233593bSZang Roy-r61911 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 143414cf11afSPaul Mackerras 143514cf11afSPaul Mackerras /* Set current processor priority to max */ 14367233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 143714cf11afSPaul Mackerras 143814cf11afSPaul Mackerras spin_unlock_irqrestore(&mpic_lock, flags); 143914cf11afSPaul Mackerras } 144014cf11afSPaul Mackerras 144114cf11afSPaul Mackerras 144214cf11afSPaul Mackerras void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 144314cf11afSPaul Mackerras { 144414cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 144514cf11afSPaul Mackerras 144614cf11afSPaul Mackerras BUG_ON(mpic == NULL); 144714cf11afSPaul Mackerras 14481beb6a7dSBenjamin Herrenschmidt #ifdef DEBUG_IPI 144914cf11afSPaul Mackerras DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 14501beb6a7dSBenjamin Herrenschmidt #endif 145114cf11afSPaul Mackerras 14527233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 14537233593bSZang Roy-r61911 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 145414cf11afSPaul Mackerras mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 145514cf11afSPaul Mackerras } 145614cf11afSPaul Mackerras 1457f365355eSOlof Johansson static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) 145814cf11afSPaul Mackerras { 14590ebfff14SBenjamin Herrenschmidt u32 src; 146014cf11afSPaul Mackerras 1461f365355eSOlof Johansson src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); 14621beb6a7dSBenjamin Herrenschmidt #ifdef DEBUG_LOW 1463f365355eSOlof Johansson DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); 14641beb6a7dSBenjamin Herrenschmidt #endif 14655cddd2e3SJosh Boyer if (unlikely(src == mpic->spurious_vec)) { 14665cddd2e3SJosh Boyer if (mpic->flags & MPIC_SPV_EOI) 14675cddd2e3SJosh Boyer mpic_eoi(mpic); 14680ebfff14SBenjamin Herrenschmidt return NO_IRQ; 14695cddd2e3SJosh Boyer } 14707fd72186SBenjamin Herrenschmidt if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 14717fd72186SBenjamin Herrenschmidt if (printk_ratelimit()) 14727fd72186SBenjamin Herrenschmidt printk(KERN_WARNING "%s: Got protected source %d !\n", 14737fd72186SBenjamin Herrenschmidt mpic->name, (int)src); 14747fd72186SBenjamin Herrenschmidt mpic_eoi(mpic); 14757fd72186SBenjamin Herrenschmidt return NO_IRQ; 14767fd72186SBenjamin Herrenschmidt } 14777fd72186SBenjamin Herrenschmidt 14780ebfff14SBenjamin Herrenschmidt return irq_linear_revmap(mpic->irqhost, src); 147914cf11afSPaul Mackerras } 148014cf11afSPaul Mackerras 1481f365355eSOlof Johansson unsigned int mpic_get_one_irq(struct mpic *mpic) 1482f365355eSOlof Johansson { 1483f365355eSOlof Johansson return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); 1484f365355eSOlof Johansson } 1485f365355eSOlof Johansson 148635a84c2fSOlaf Hering unsigned int mpic_get_irq(void) 148714cf11afSPaul Mackerras { 148814cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 148914cf11afSPaul Mackerras 149014cf11afSPaul Mackerras BUG_ON(mpic == NULL); 149114cf11afSPaul Mackerras 149235a84c2fSOlaf Hering return mpic_get_one_irq(mpic); 149314cf11afSPaul Mackerras } 149414cf11afSPaul Mackerras 1495f365355eSOlof Johansson unsigned int mpic_get_mcirq(void) 1496f365355eSOlof Johansson { 1497f365355eSOlof Johansson struct mpic *mpic = mpic_primary; 1498f365355eSOlof Johansson 1499f365355eSOlof Johansson BUG_ON(mpic == NULL); 1500f365355eSOlof Johansson 1501f365355eSOlof Johansson return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); 1502f365355eSOlof Johansson } 150314cf11afSPaul Mackerras 150414cf11afSPaul Mackerras #ifdef CONFIG_SMP 150514cf11afSPaul Mackerras void mpic_request_ipis(void) 150614cf11afSPaul Mackerras { 150714cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 1508194046a1SOlof Johansson long i, err; 15090ebfff14SBenjamin Herrenschmidt static char *ipi_names[] = { 15100ebfff14SBenjamin Herrenschmidt "IPI0 (call function)", 15110ebfff14SBenjamin Herrenschmidt "IPI1 (reschedule)", 15120ebfff14SBenjamin Herrenschmidt "IPI2 (unused)", 15130ebfff14SBenjamin Herrenschmidt "IPI3 (debugger break)", 15140ebfff14SBenjamin Herrenschmidt }; 151514cf11afSPaul Mackerras BUG_ON(mpic == NULL); 151614cf11afSPaul Mackerras 15170ebfff14SBenjamin Herrenschmidt printk(KERN_INFO "mpic: requesting IPIs ... \n"); 151814cf11afSPaul Mackerras 15190ebfff14SBenjamin Herrenschmidt for (i = 0; i < 4; i++) { 15200ebfff14SBenjamin Herrenschmidt unsigned int vipi = irq_create_mapping(mpic->irqhost, 15217df2457dSOlof Johansson mpic->ipi_vecs[0] + i); 15220ebfff14SBenjamin Herrenschmidt if (vipi == NO_IRQ) { 1523194046a1SOlof Johansson printk(KERN_ERR "Failed to map IPI %ld\n", i); 15240ebfff14SBenjamin Herrenschmidt break; 15250ebfff14SBenjamin Herrenschmidt } 1526d16f1b64SOlof Johansson err = request_irq(vipi, mpic_ipi_action, 1527d16f1b64SOlof Johansson IRQF_DISABLED|IRQF_PERCPU, 1528194046a1SOlof Johansson ipi_names[i], (void *)i); 1529d16f1b64SOlof Johansson if (err) { 1530194046a1SOlof Johansson printk(KERN_ERR "Request of irq %d for IPI %ld failed\n", 1531d16f1b64SOlof Johansson vipi, i); 1532d16f1b64SOlof Johansson break; 1533d16f1b64SOlof Johansson } 15340ebfff14SBenjamin Herrenschmidt } 153514cf11afSPaul Mackerras } 1536a9c59264SPaul Mackerras 1537a9c59264SPaul Mackerras void smp_mpic_message_pass(int target, int msg) 1538a9c59264SPaul Mackerras { 1539a9c59264SPaul Mackerras /* make sure we're sending something that translates to an IPI */ 1540a9c59264SPaul Mackerras if ((unsigned int)msg > 3) { 1541a9c59264SPaul Mackerras printk("SMP %d: smp_message_pass: unknown msg %d\n", 1542a9c59264SPaul Mackerras smp_processor_id(), msg); 1543a9c59264SPaul Mackerras return; 1544a9c59264SPaul Mackerras } 1545a9c59264SPaul Mackerras switch (target) { 1546a9c59264SPaul Mackerras case MSG_ALL: 1547a9c59264SPaul Mackerras mpic_send_ipi(msg, 0xffffffff); 1548a9c59264SPaul Mackerras break; 1549a9c59264SPaul Mackerras case MSG_ALL_BUT_SELF: 1550a9c59264SPaul Mackerras mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); 1551a9c59264SPaul Mackerras break; 1552a9c59264SPaul Mackerras default: 1553a9c59264SPaul Mackerras mpic_send_ipi(msg, 1 << target); 1554a9c59264SPaul Mackerras break; 1555a9c59264SPaul Mackerras } 1556a9c59264SPaul Mackerras } 1557775aeff4SMichael Ellerman 1558775aeff4SMichael Ellerman int __init smp_mpic_probe(void) 1559775aeff4SMichael Ellerman { 1560775aeff4SMichael Ellerman int nr_cpus; 1561775aeff4SMichael Ellerman 1562775aeff4SMichael Ellerman DBG("smp_mpic_probe()...\n"); 1563775aeff4SMichael Ellerman 1564775aeff4SMichael Ellerman nr_cpus = cpus_weight(cpu_possible_map); 1565775aeff4SMichael Ellerman 1566775aeff4SMichael Ellerman DBG("nr_cpus: %d\n", nr_cpus); 1567775aeff4SMichael Ellerman 1568775aeff4SMichael Ellerman if (nr_cpus > 1) 1569775aeff4SMichael Ellerman mpic_request_ipis(); 1570775aeff4SMichael Ellerman 1571775aeff4SMichael Ellerman return nr_cpus; 1572775aeff4SMichael Ellerman } 1573775aeff4SMichael Ellerman 1574775aeff4SMichael Ellerman void __devinit smp_mpic_setup_cpu(int cpu) 1575775aeff4SMichael Ellerman { 1576775aeff4SMichael Ellerman mpic_setup_this_cpu(); 1577775aeff4SMichael Ellerman } 157814cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 15793669e930SJohannes Berg 15803669e930SJohannes Berg #ifdef CONFIG_PM 15813669e930SJohannes Berg static int mpic_suspend(struct sys_device *dev, pm_message_t state) 15823669e930SJohannes Berg { 15833669e930SJohannes Berg struct mpic *mpic = container_of(dev, struct mpic, sysdev); 15843669e930SJohannes Berg int i; 15853669e930SJohannes Berg 15863669e930SJohannes Berg for (i = 0; i < mpic->num_sources; i++) { 15873669e930SJohannes Berg mpic->save_data[i].vecprio = 15883669e930SJohannes Berg mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 15893669e930SJohannes Berg mpic->save_data[i].dest = 15903669e930SJohannes Berg mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 15913669e930SJohannes Berg } 15923669e930SJohannes Berg 15933669e930SJohannes Berg return 0; 15943669e930SJohannes Berg } 15953669e930SJohannes Berg 15963669e930SJohannes Berg static int mpic_resume(struct sys_device *dev) 15973669e930SJohannes Berg { 15983669e930SJohannes Berg struct mpic *mpic = container_of(dev, struct mpic, sysdev); 15993669e930SJohannes Berg int i; 16003669e930SJohannes Berg 16013669e930SJohannes Berg for (i = 0; i < mpic->num_sources; i++) { 16023669e930SJohannes Berg mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 16033669e930SJohannes Berg mpic->save_data[i].vecprio); 16043669e930SJohannes Berg mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 16053669e930SJohannes Berg mpic->save_data[i].dest); 16063669e930SJohannes Berg 16073669e930SJohannes Berg #ifdef CONFIG_MPIC_U3_HT_IRQS 16083669e930SJohannes Berg { 16093669e930SJohannes Berg struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 16103669e930SJohannes Berg 16113669e930SJohannes Berg if (fixup->base) { 16123669e930SJohannes Berg /* we use the lowest bit in an inverted meaning */ 16133669e930SJohannes Berg if ((mpic->save_data[i].fixup_data & 1) == 0) 16143669e930SJohannes Berg continue; 16153669e930SJohannes Berg 16163669e930SJohannes Berg /* Enable and configure */ 16173669e930SJohannes Berg writeb(0x10 + 2 * fixup->index, fixup->base + 2); 16183669e930SJohannes Berg 16193669e930SJohannes Berg writel(mpic->save_data[i].fixup_data & ~1, 16203669e930SJohannes Berg fixup->base + 4); 16213669e930SJohannes Berg } 16223669e930SJohannes Berg } 16233669e930SJohannes Berg #endif 16243669e930SJohannes Berg } /* end for loop */ 16253669e930SJohannes Berg 16263669e930SJohannes Berg return 0; 16273669e930SJohannes Berg } 16283669e930SJohannes Berg #endif 16293669e930SJohannes Berg 16303669e930SJohannes Berg static struct sysdev_class mpic_sysclass = { 16313669e930SJohannes Berg #ifdef CONFIG_PM 16323669e930SJohannes Berg .resume = mpic_resume, 16333669e930SJohannes Berg .suspend = mpic_suspend, 16343669e930SJohannes Berg #endif 1635af5ca3f4SKay Sievers .name = "mpic", 16363669e930SJohannes Berg }; 16373669e930SJohannes Berg 16383669e930SJohannes Berg static int mpic_init_sys(void) 16393669e930SJohannes Berg { 16403669e930SJohannes Berg struct mpic *mpic = mpics; 16413669e930SJohannes Berg int error, id = 0; 16423669e930SJohannes Berg 16433669e930SJohannes Berg error = sysdev_class_register(&mpic_sysclass); 16443669e930SJohannes Berg 16453669e930SJohannes Berg while (mpic && !error) { 16463669e930SJohannes Berg mpic->sysdev.cls = &mpic_sysclass; 16473669e930SJohannes Berg mpic->sysdev.id = id++; 16483669e930SJohannes Berg error = sysdev_register(&mpic->sysdev); 16493669e930SJohannes Berg mpic = mpic->next; 16503669e930SJohannes Berg } 16513669e930SJohannes Berg return error; 16523669e930SJohannes Berg } 16533669e930SJohannes Berg 16543669e930SJohannes Berg device_initcall(mpic_init_sys); 1655