114cf11afSPaul Mackerras /* 214cf11afSPaul Mackerras * arch/powerpc/kernel/mpic.c 314cf11afSPaul Mackerras * 414cf11afSPaul Mackerras * Driver for interrupt controllers following the OpenPIC standard, the 514cf11afSPaul Mackerras * common implementation beeing IBM's MPIC. This driver also can deal 614cf11afSPaul Mackerras * with various broken implementations of this HW. 714cf11afSPaul Mackerras * 814cf11afSPaul Mackerras * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 914cf11afSPaul Mackerras * 1014cf11afSPaul Mackerras * This file is subject to the terms and conditions of the GNU General Public 1114cf11afSPaul Mackerras * License. See the file COPYING in the main directory of this archive 1214cf11afSPaul Mackerras * for more details. 1314cf11afSPaul Mackerras */ 1414cf11afSPaul Mackerras 1514cf11afSPaul Mackerras #undef DEBUG 161beb6a7dSBenjamin Herrenschmidt #undef DEBUG_IPI 171beb6a7dSBenjamin Herrenschmidt #undef DEBUG_IRQ 181beb6a7dSBenjamin Herrenschmidt #undef DEBUG_LOW 1914cf11afSPaul Mackerras 2014cf11afSPaul Mackerras #include <linux/types.h> 2114cf11afSPaul Mackerras #include <linux/kernel.h> 2214cf11afSPaul Mackerras #include <linux/init.h> 2314cf11afSPaul Mackerras #include <linux/irq.h> 2414cf11afSPaul Mackerras #include <linux/smp.h> 2514cf11afSPaul Mackerras #include <linux/interrupt.h> 2614cf11afSPaul Mackerras #include <linux/bootmem.h> 2714cf11afSPaul Mackerras #include <linux/spinlock.h> 2814cf11afSPaul Mackerras #include <linux/pci.h> 29*5a0e3ad6STejun Heo #include <linux/slab.h> 3014cf11afSPaul Mackerras 3114cf11afSPaul Mackerras #include <asm/ptrace.h> 3214cf11afSPaul Mackerras #include <asm/signal.h> 3314cf11afSPaul Mackerras #include <asm/io.h> 3414cf11afSPaul Mackerras #include <asm/pgtable.h> 3514cf11afSPaul Mackerras #include <asm/irq.h> 3614cf11afSPaul Mackerras #include <asm/machdep.h> 3714cf11afSPaul Mackerras #include <asm/mpic.h> 3814cf11afSPaul Mackerras #include <asm/smp.h> 3914cf11afSPaul Mackerras 40a7de7c74SMichael Ellerman #include "mpic.h" 41a7de7c74SMichael Ellerman 4214cf11afSPaul Mackerras #ifdef DEBUG 4314cf11afSPaul Mackerras #define DBG(fmt...) printk(fmt) 4414cf11afSPaul Mackerras #else 4514cf11afSPaul Mackerras #define DBG(fmt...) 4614cf11afSPaul Mackerras #endif 4714cf11afSPaul Mackerras 4814cf11afSPaul Mackerras static struct mpic *mpics; 4914cf11afSPaul Mackerras static struct mpic *mpic_primary; 50203041adSThomas Gleixner static DEFINE_RAW_SPINLOCK(mpic_lock); 5114cf11afSPaul Mackerras 52c0c0d996SPaul Mackerras #ifdef CONFIG_PPC32 /* XXX for now */ 53e40c7f02SAndy Whitcroft #ifdef CONFIG_IRQ_ALL_CPUS 54e40c7f02SAndy Whitcroft #define distribute_irqs (1) 55e40c7f02SAndy Whitcroft #else 56e40c7f02SAndy Whitcroft #define distribute_irqs (0) 57e40c7f02SAndy Whitcroft #endif 58c0c0d996SPaul Mackerras #endif 5914cf11afSPaul Mackerras 607233593bSZang Roy-r61911 #ifdef CONFIG_MPIC_WEIRD 617233593bSZang Roy-r61911 static u32 mpic_infos[][MPIC_IDX_END] = { 627233593bSZang Roy-r61911 [0] = { /* Original OpenPIC compatible MPIC */ 637233593bSZang Roy-r61911 MPIC_GREG_BASE, 647233593bSZang Roy-r61911 MPIC_GREG_FEATURE_0, 657233593bSZang Roy-r61911 MPIC_GREG_GLOBAL_CONF_0, 667233593bSZang Roy-r61911 MPIC_GREG_VENDOR_ID, 677233593bSZang Roy-r61911 MPIC_GREG_IPI_VECTOR_PRI_0, 687233593bSZang Roy-r61911 MPIC_GREG_IPI_STRIDE, 697233593bSZang Roy-r61911 MPIC_GREG_SPURIOUS, 707233593bSZang Roy-r61911 MPIC_GREG_TIMER_FREQ, 717233593bSZang Roy-r61911 727233593bSZang Roy-r61911 MPIC_TIMER_BASE, 737233593bSZang Roy-r61911 MPIC_TIMER_STRIDE, 747233593bSZang Roy-r61911 MPIC_TIMER_CURRENT_CNT, 757233593bSZang Roy-r61911 MPIC_TIMER_BASE_CNT, 767233593bSZang Roy-r61911 MPIC_TIMER_VECTOR_PRI, 777233593bSZang Roy-r61911 MPIC_TIMER_DESTINATION, 787233593bSZang Roy-r61911 797233593bSZang Roy-r61911 MPIC_CPU_BASE, 807233593bSZang Roy-r61911 MPIC_CPU_STRIDE, 817233593bSZang Roy-r61911 MPIC_CPU_IPI_DISPATCH_0, 827233593bSZang Roy-r61911 MPIC_CPU_IPI_DISPATCH_STRIDE, 837233593bSZang Roy-r61911 MPIC_CPU_CURRENT_TASK_PRI, 847233593bSZang Roy-r61911 MPIC_CPU_WHOAMI, 857233593bSZang Roy-r61911 MPIC_CPU_INTACK, 867233593bSZang Roy-r61911 MPIC_CPU_EOI, 87f365355eSOlof Johansson MPIC_CPU_MCACK, 887233593bSZang Roy-r61911 897233593bSZang Roy-r61911 MPIC_IRQ_BASE, 907233593bSZang Roy-r61911 MPIC_IRQ_STRIDE, 917233593bSZang Roy-r61911 MPIC_IRQ_VECTOR_PRI, 927233593bSZang Roy-r61911 MPIC_VECPRI_VECTOR_MASK, 937233593bSZang Roy-r61911 MPIC_VECPRI_POLARITY_POSITIVE, 947233593bSZang Roy-r61911 MPIC_VECPRI_POLARITY_NEGATIVE, 957233593bSZang Roy-r61911 MPIC_VECPRI_SENSE_LEVEL, 967233593bSZang Roy-r61911 MPIC_VECPRI_SENSE_EDGE, 977233593bSZang Roy-r61911 MPIC_VECPRI_POLARITY_MASK, 987233593bSZang Roy-r61911 MPIC_VECPRI_SENSE_MASK, 997233593bSZang Roy-r61911 MPIC_IRQ_DESTINATION 1007233593bSZang Roy-r61911 }, 1017233593bSZang Roy-r61911 [1] = { /* Tsi108/109 PIC */ 1027233593bSZang Roy-r61911 TSI108_GREG_BASE, 1037233593bSZang Roy-r61911 TSI108_GREG_FEATURE_0, 1047233593bSZang Roy-r61911 TSI108_GREG_GLOBAL_CONF_0, 1057233593bSZang Roy-r61911 TSI108_GREG_VENDOR_ID, 1067233593bSZang Roy-r61911 TSI108_GREG_IPI_VECTOR_PRI_0, 1077233593bSZang Roy-r61911 TSI108_GREG_IPI_STRIDE, 1087233593bSZang Roy-r61911 TSI108_GREG_SPURIOUS, 1097233593bSZang Roy-r61911 TSI108_GREG_TIMER_FREQ, 1107233593bSZang Roy-r61911 1117233593bSZang Roy-r61911 TSI108_TIMER_BASE, 1127233593bSZang Roy-r61911 TSI108_TIMER_STRIDE, 1137233593bSZang Roy-r61911 TSI108_TIMER_CURRENT_CNT, 1147233593bSZang Roy-r61911 TSI108_TIMER_BASE_CNT, 1157233593bSZang Roy-r61911 TSI108_TIMER_VECTOR_PRI, 1167233593bSZang Roy-r61911 TSI108_TIMER_DESTINATION, 1177233593bSZang Roy-r61911 1187233593bSZang Roy-r61911 TSI108_CPU_BASE, 1197233593bSZang Roy-r61911 TSI108_CPU_STRIDE, 1207233593bSZang Roy-r61911 TSI108_CPU_IPI_DISPATCH_0, 1217233593bSZang Roy-r61911 TSI108_CPU_IPI_DISPATCH_STRIDE, 1227233593bSZang Roy-r61911 TSI108_CPU_CURRENT_TASK_PRI, 1237233593bSZang Roy-r61911 TSI108_CPU_WHOAMI, 1247233593bSZang Roy-r61911 TSI108_CPU_INTACK, 1257233593bSZang Roy-r61911 TSI108_CPU_EOI, 126f365355eSOlof Johansson TSI108_CPU_MCACK, 1277233593bSZang Roy-r61911 1287233593bSZang Roy-r61911 TSI108_IRQ_BASE, 1297233593bSZang Roy-r61911 TSI108_IRQ_STRIDE, 1307233593bSZang Roy-r61911 TSI108_IRQ_VECTOR_PRI, 1317233593bSZang Roy-r61911 TSI108_VECPRI_VECTOR_MASK, 1327233593bSZang Roy-r61911 TSI108_VECPRI_POLARITY_POSITIVE, 1337233593bSZang Roy-r61911 TSI108_VECPRI_POLARITY_NEGATIVE, 1347233593bSZang Roy-r61911 TSI108_VECPRI_SENSE_LEVEL, 1357233593bSZang Roy-r61911 TSI108_VECPRI_SENSE_EDGE, 1367233593bSZang Roy-r61911 TSI108_VECPRI_POLARITY_MASK, 1377233593bSZang Roy-r61911 TSI108_VECPRI_SENSE_MASK, 1387233593bSZang Roy-r61911 TSI108_IRQ_DESTINATION 1397233593bSZang Roy-r61911 }, 1407233593bSZang Roy-r61911 }; 1417233593bSZang Roy-r61911 1427233593bSZang Roy-r61911 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] 1437233593bSZang Roy-r61911 1447233593bSZang Roy-r61911 #else /* CONFIG_MPIC_WEIRD */ 1457233593bSZang Roy-r61911 1467233593bSZang Roy-r61911 #define MPIC_INFO(name) MPIC_##name 1477233593bSZang Roy-r61911 1487233593bSZang Roy-r61911 #endif /* CONFIG_MPIC_WEIRD */ 1497233593bSZang Roy-r61911 15014cf11afSPaul Mackerras /* 15114cf11afSPaul Mackerras * Register accessor functions 15214cf11afSPaul Mackerras */ 15314cf11afSPaul Mackerras 15414cf11afSPaul Mackerras 155fbf0274eSBenjamin Herrenschmidt static inline u32 _mpic_read(enum mpic_reg_type type, 156fbf0274eSBenjamin Herrenschmidt struct mpic_reg_bank *rb, 15714cf11afSPaul Mackerras unsigned int reg) 15814cf11afSPaul Mackerras { 159fbf0274eSBenjamin Herrenschmidt switch(type) { 160fbf0274eSBenjamin Herrenschmidt #ifdef CONFIG_PPC_DCR 161fbf0274eSBenjamin Herrenschmidt case mpic_access_dcr: 16283f34df4SMichael Ellerman return dcr_read(rb->dhost, reg); 163fbf0274eSBenjamin Herrenschmidt #endif 164fbf0274eSBenjamin Herrenschmidt case mpic_access_mmio_be: 165fbf0274eSBenjamin Herrenschmidt return in_be32(rb->base + (reg >> 2)); 166fbf0274eSBenjamin Herrenschmidt case mpic_access_mmio_le: 167fbf0274eSBenjamin Herrenschmidt default: 168fbf0274eSBenjamin Herrenschmidt return in_le32(rb->base + (reg >> 2)); 169fbf0274eSBenjamin Herrenschmidt } 17014cf11afSPaul Mackerras } 17114cf11afSPaul Mackerras 172fbf0274eSBenjamin Herrenschmidt static inline void _mpic_write(enum mpic_reg_type type, 173fbf0274eSBenjamin Herrenschmidt struct mpic_reg_bank *rb, 17414cf11afSPaul Mackerras unsigned int reg, u32 value) 17514cf11afSPaul Mackerras { 176fbf0274eSBenjamin Herrenschmidt switch(type) { 177fbf0274eSBenjamin Herrenschmidt #ifdef CONFIG_PPC_DCR 178fbf0274eSBenjamin Herrenschmidt case mpic_access_dcr: 179d9d1063dSJohannes Berg dcr_write(rb->dhost, reg, value); 180d9d1063dSJohannes Berg break; 181fbf0274eSBenjamin Herrenschmidt #endif 182fbf0274eSBenjamin Herrenschmidt case mpic_access_mmio_be: 183d9d1063dSJohannes Berg out_be32(rb->base + (reg >> 2), value); 184d9d1063dSJohannes Berg break; 185fbf0274eSBenjamin Herrenschmidt case mpic_access_mmio_le: 186fbf0274eSBenjamin Herrenschmidt default: 187d9d1063dSJohannes Berg out_le32(rb->base + (reg >> 2), value); 188d9d1063dSJohannes Berg break; 189fbf0274eSBenjamin Herrenschmidt } 19014cf11afSPaul Mackerras } 19114cf11afSPaul Mackerras 19214cf11afSPaul Mackerras static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 19314cf11afSPaul Mackerras { 194fbf0274eSBenjamin Herrenschmidt enum mpic_reg_type type = mpic->reg_type; 1957233593bSZang Roy-r61911 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 1967233593bSZang Roy-r61911 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 19714cf11afSPaul Mackerras 198fbf0274eSBenjamin Herrenschmidt if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) 199fbf0274eSBenjamin Herrenschmidt type = mpic_access_mmio_be; 200fbf0274eSBenjamin Herrenschmidt return _mpic_read(type, &mpic->gregs, offset); 20114cf11afSPaul Mackerras } 20214cf11afSPaul Mackerras 20314cf11afSPaul Mackerras static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 20414cf11afSPaul Mackerras { 2057233593bSZang Roy-r61911 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + 2067233593bSZang Roy-r61911 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); 20714cf11afSPaul Mackerras 208fbf0274eSBenjamin Herrenschmidt _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 20914cf11afSPaul Mackerras } 21014cf11afSPaul Mackerras 21114cf11afSPaul Mackerras static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 21214cf11afSPaul Mackerras { 21314cf11afSPaul Mackerras unsigned int cpu = 0; 21414cf11afSPaul Mackerras 21514cf11afSPaul Mackerras if (mpic->flags & MPIC_PRIMARY) 21614cf11afSPaul Mackerras cpu = hard_smp_processor_id(); 217fbf0274eSBenjamin Herrenschmidt return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 21814cf11afSPaul Mackerras } 21914cf11afSPaul Mackerras 22014cf11afSPaul Mackerras static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 22114cf11afSPaul Mackerras { 22214cf11afSPaul Mackerras unsigned int cpu = 0; 22314cf11afSPaul Mackerras 22414cf11afSPaul Mackerras if (mpic->flags & MPIC_PRIMARY) 22514cf11afSPaul Mackerras cpu = hard_smp_processor_id(); 22614cf11afSPaul Mackerras 227fbf0274eSBenjamin Herrenschmidt _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 22814cf11afSPaul Mackerras } 22914cf11afSPaul Mackerras 23014cf11afSPaul Mackerras static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) 23114cf11afSPaul Mackerras { 23214cf11afSPaul Mackerras unsigned int isu = src_no >> mpic->isu_shift; 23314cf11afSPaul Mackerras unsigned int idx = src_no & mpic->isu_mask; 23411a6b292SMichael Ellerman unsigned int val; 23514cf11afSPaul Mackerras 23611a6b292SMichael Ellerman val = _mpic_read(mpic->reg_type, &mpic->isus[isu], 23711a6b292SMichael Ellerman reg + (idx * MPIC_INFO(IRQ_STRIDE))); 2380d72ba93SOlof Johansson #ifdef CONFIG_MPIC_BROKEN_REGREAD 2390d72ba93SOlof Johansson if (reg == 0) 24011a6b292SMichael Ellerman val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | 24111a6b292SMichael Ellerman mpic->isu_reg0_shadow[src_no]; 2420d72ba93SOlof Johansson #endif 24311a6b292SMichael Ellerman return val; 24414cf11afSPaul Mackerras } 24514cf11afSPaul Mackerras 24614cf11afSPaul Mackerras static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 24714cf11afSPaul Mackerras unsigned int reg, u32 value) 24814cf11afSPaul Mackerras { 24914cf11afSPaul Mackerras unsigned int isu = src_no >> mpic->isu_shift; 25014cf11afSPaul Mackerras unsigned int idx = src_no & mpic->isu_mask; 25114cf11afSPaul Mackerras 252fbf0274eSBenjamin Herrenschmidt _mpic_write(mpic->reg_type, &mpic->isus[isu], 2537233593bSZang Roy-r61911 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); 2540d72ba93SOlof Johansson 2550d72ba93SOlof Johansson #ifdef CONFIG_MPIC_BROKEN_REGREAD 2560d72ba93SOlof Johansson if (reg == 0) 25711a6b292SMichael Ellerman mpic->isu_reg0_shadow[src_no] = 25811a6b292SMichael Ellerman value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); 2590d72ba93SOlof Johansson #endif 26014cf11afSPaul Mackerras } 26114cf11afSPaul Mackerras 262fbf0274eSBenjamin Herrenschmidt #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) 263fbf0274eSBenjamin Herrenschmidt #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 26414cf11afSPaul Mackerras #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 26514cf11afSPaul Mackerras #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 26614cf11afSPaul Mackerras #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 26714cf11afSPaul Mackerras #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 26814cf11afSPaul Mackerras #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 26914cf11afSPaul Mackerras #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) 27014cf11afSPaul Mackerras 27114cf11afSPaul Mackerras 27214cf11afSPaul Mackerras /* 27314cf11afSPaul Mackerras * Low level utility functions 27414cf11afSPaul Mackerras */ 27514cf11afSPaul Mackerras 27614cf11afSPaul Mackerras 277c51a3fdcSBecky Bruce static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, 278fbf0274eSBenjamin Herrenschmidt struct mpic_reg_bank *rb, unsigned int offset, 279fbf0274eSBenjamin Herrenschmidt unsigned int size) 280fbf0274eSBenjamin Herrenschmidt { 281fbf0274eSBenjamin Herrenschmidt rb->base = ioremap(phys_addr + offset, size); 282fbf0274eSBenjamin Herrenschmidt BUG_ON(rb->base == NULL); 283fbf0274eSBenjamin Herrenschmidt } 284fbf0274eSBenjamin Herrenschmidt 285fbf0274eSBenjamin Herrenschmidt #ifdef CONFIG_PPC_DCR 2865a2642f6SBenjamin Herrenschmidt static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, 2875a2642f6SBenjamin Herrenschmidt struct mpic_reg_bank *rb, 288fbf0274eSBenjamin Herrenschmidt unsigned int offset, unsigned int size) 289fbf0274eSBenjamin Herrenschmidt { 2900411a5e2SMichael Ellerman const u32 *dbasep; 2910411a5e2SMichael Ellerman 2925a2642f6SBenjamin Herrenschmidt dbasep = of_get_property(node, "dcr-reg", NULL); 2930411a5e2SMichael Ellerman 2945a2642f6SBenjamin Herrenschmidt rb->dhost = dcr_map(node, *dbasep + offset, size); 295fbf0274eSBenjamin Herrenschmidt BUG_ON(!DCR_MAP_OK(rb->dhost)); 296fbf0274eSBenjamin Herrenschmidt } 297fbf0274eSBenjamin Herrenschmidt 2985a2642f6SBenjamin Herrenschmidt static inline void mpic_map(struct mpic *mpic, struct device_node *node, 2995a2642f6SBenjamin Herrenschmidt phys_addr_t phys_addr, struct mpic_reg_bank *rb, 3005a2642f6SBenjamin Herrenschmidt unsigned int offset, unsigned int size) 301fbf0274eSBenjamin Herrenschmidt { 302fbf0274eSBenjamin Herrenschmidt if (mpic->flags & MPIC_USES_DCR) 3035a2642f6SBenjamin Herrenschmidt _mpic_map_dcr(mpic, node, rb, offset, size); 304fbf0274eSBenjamin Herrenschmidt else 305fbf0274eSBenjamin Herrenschmidt _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 306fbf0274eSBenjamin Herrenschmidt } 307fbf0274eSBenjamin Herrenschmidt #else /* CONFIG_PPC_DCR */ 3085a2642f6SBenjamin Herrenschmidt #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 309fbf0274eSBenjamin Herrenschmidt #endif /* !CONFIG_PPC_DCR */ 310fbf0274eSBenjamin Herrenschmidt 311fbf0274eSBenjamin Herrenschmidt 31214cf11afSPaul Mackerras 31314cf11afSPaul Mackerras /* Check if we have one of those nice broken MPICs with a flipped endian on 31414cf11afSPaul Mackerras * reads from IPI registers 31514cf11afSPaul Mackerras */ 31614cf11afSPaul Mackerras static void __init mpic_test_broken_ipi(struct mpic *mpic) 31714cf11afSPaul Mackerras { 31814cf11afSPaul Mackerras u32 r; 31914cf11afSPaul Mackerras 3207233593bSZang Roy-r61911 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); 3217233593bSZang Roy-r61911 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); 32214cf11afSPaul Mackerras 32314cf11afSPaul Mackerras if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 32414cf11afSPaul Mackerras printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 32514cf11afSPaul Mackerras mpic->flags |= MPIC_BROKEN_IPI; 32614cf11afSPaul Mackerras } 32714cf11afSPaul Mackerras } 32814cf11afSPaul Mackerras 3296cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 33014cf11afSPaul Mackerras 33114cf11afSPaul Mackerras /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) 33214cf11afSPaul Mackerras * to force the edge setting on the MPIC and do the ack workaround. 33314cf11afSPaul Mackerras */ 3341beb6a7dSBenjamin Herrenschmidt static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 33514cf11afSPaul Mackerras { 3361beb6a7dSBenjamin Herrenschmidt if (source >= 128 || !mpic->fixups) 33714cf11afSPaul Mackerras return 0; 3381beb6a7dSBenjamin Herrenschmidt return mpic->fixups[source].base != NULL; 33914cf11afSPaul Mackerras } 34014cf11afSPaul Mackerras 341c4b22f26SSegher Boessenkool 3421beb6a7dSBenjamin Herrenschmidt static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) 34314cf11afSPaul Mackerras { 3441beb6a7dSBenjamin Herrenschmidt struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 34514cf11afSPaul Mackerras 3461beb6a7dSBenjamin Herrenschmidt if (fixup->applebase) { 3471beb6a7dSBenjamin Herrenschmidt unsigned int soff = (fixup->index >> 3) & ~3; 3481beb6a7dSBenjamin Herrenschmidt unsigned int mask = 1U << (fixup->index & 0x1f); 3491beb6a7dSBenjamin Herrenschmidt writel(mask, fixup->applebase + soff); 3501beb6a7dSBenjamin Herrenschmidt } else { 351203041adSThomas Gleixner raw_spin_lock(&mpic->fixup_lock); 3521beb6a7dSBenjamin Herrenschmidt writeb(0x11 + 2 * fixup->index, fixup->base + 2); 353c4b22f26SSegher Boessenkool writel(fixup->data, fixup->base + 4); 354203041adSThomas Gleixner raw_spin_unlock(&mpic->fixup_lock); 35514cf11afSPaul Mackerras } 3561beb6a7dSBenjamin Herrenschmidt } 35714cf11afSPaul Mackerras 3581beb6a7dSBenjamin Herrenschmidt static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 3591beb6a7dSBenjamin Herrenschmidt unsigned int irqflags) 3601beb6a7dSBenjamin Herrenschmidt { 3611beb6a7dSBenjamin Herrenschmidt struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 3621beb6a7dSBenjamin Herrenschmidt unsigned long flags; 3631beb6a7dSBenjamin Herrenschmidt u32 tmp; 36414cf11afSPaul Mackerras 3651beb6a7dSBenjamin Herrenschmidt if (fixup->base == NULL) 3661beb6a7dSBenjamin Herrenschmidt return; 3671beb6a7dSBenjamin Herrenschmidt 36806fe98e6SBenjamin Herrenschmidt DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 3691beb6a7dSBenjamin Herrenschmidt source, irqflags, fixup->index); 370203041adSThomas Gleixner raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 3711beb6a7dSBenjamin Herrenschmidt /* Enable and configure */ 3721beb6a7dSBenjamin Herrenschmidt writeb(0x10 + 2 * fixup->index, fixup->base + 2); 3731beb6a7dSBenjamin Herrenschmidt tmp = readl(fixup->base + 4); 3741beb6a7dSBenjamin Herrenschmidt tmp &= ~(0x23U); 3751beb6a7dSBenjamin Herrenschmidt if (irqflags & IRQ_LEVEL) 3761beb6a7dSBenjamin Herrenschmidt tmp |= 0x22; 3771beb6a7dSBenjamin Herrenschmidt writel(tmp, fixup->base + 4); 378203041adSThomas Gleixner raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 3793669e930SJohannes Berg 3803669e930SJohannes Berg #ifdef CONFIG_PM 3813669e930SJohannes Berg /* use the lowest bit inverted to the actual HW, 3823669e930SJohannes Berg * set if this fixup was enabled, clear otherwise */ 3833669e930SJohannes Berg mpic->save_data[source].fixup_data = tmp | 1; 3843669e930SJohannes Berg #endif 3851beb6a7dSBenjamin Herrenschmidt } 3861beb6a7dSBenjamin Herrenschmidt 3871beb6a7dSBenjamin Herrenschmidt static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 3881beb6a7dSBenjamin Herrenschmidt unsigned int irqflags) 3891beb6a7dSBenjamin Herrenschmidt { 3901beb6a7dSBenjamin Herrenschmidt struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 3911beb6a7dSBenjamin Herrenschmidt unsigned long flags; 3921beb6a7dSBenjamin Herrenschmidt u32 tmp; 3931beb6a7dSBenjamin Herrenschmidt 3941beb6a7dSBenjamin Herrenschmidt if (fixup->base == NULL) 3951beb6a7dSBenjamin Herrenschmidt return; 3961beb6a7dSBenjamin Herrenschmidt 39706fe98e6SBenjamin Herrenschmidt DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 3981beb6a7dSBenjamin Herrenschmidt 3991beb6a7dSBenjamin Herrenschmidt /* Disable */ 400203041adSThomas Gleixner raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 4011beb6a7dSBenjamin Herrenschmidt writeb(0x10 + 2 * fixup->index, fixup->base + 2); 4021beb6a7dSBenjamin Herrenschmidt tmp = readl(fixup->base + 4); 40372b13819SSegher Boessenkool tmp |= 1; 4041beb6a7dSBenjamin Herrenschmidt writel(tmp, fixup->base + 4); 405203041adSThomas Gleixner raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 4063669e930SJohannes Berg 4073669e930SJohannes Berg #ifdef CONFIG_PM 4083669e930SJohannes Berg /* use the lowest bit inverted to the actual HW, 4093669e930SJohannes Berg * set if this fixup was enabled, clear otherwise */ 4103669e930SJohannes Berg mpic->save_data[source].fixup_data = tmp & ~1; 4113669e930SJohannes Berg #endif 4121beb6a7dSBenjamin Herrenschmidt } 4131beb6a7dSBenjamin Herrenschmidt 414812fd1fdSMichael Ellerman #ifdef CONFIG_PCI_MSI 415812fd1fdSMichael Ellerman static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 416812fd1fdSMichael Ellerman unsigned int devfn) 417812fd1fdSMichael Ellerman { 418812fd1fdSMichael Ellerman u8 __iomem *base; 419812fd1fdSMichael Ellerman u8 pos, flags; 420812fd1fdSMichael Ellerman u64 addr = 0; 421812fd1fdSMichael Ellerman 422812fd1fdSMichael Ellerman for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 423812fd1fdSMichael Ellerman pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 424812fd1fdSMichael Ellerman u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 425812fd1fdSMichael Ellerman if (id == PCI_CAP_ID_HT) { 426812fd1fdSMichael Ellerman id = readb(devbase + pos + 3); 427812fd1fdSMichael Ellerman if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) 428812fd1fdSMichael Ellerman break; 429812fd1fdSMichael Ellerman } 430812fd1fdSMichael Ellerman } 431812fd1fdSMichael Ellerman 432812fd1fdSMichael Ellerman if (pos == 0) 433812fd1fdSMichael Ellerman return; 434812fd1fdSMichael Ellerman 435812fd1fdSMichael Ellerman base = devbase + pos; 436812fd1fdSMichael Ellerman 437812fd1fdSMichael Ellerman flags = readb(base + HT_MSI_FLAGS); 438812fd1fdSMichael Ellerman if (!(flags & HT_MSI_FLAGS_FIXED)) { 439812fd1fdSMichael Ellerman addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; 440812fd1fdSMichael Ellerman addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); 441812fd1fdSMichael Ellerman } 442812fd1fdSMichael Ellerman 443fe333321SIngo Molnar printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", 444812fd1fdSMichael Ellerman PCI_SLOT(devfn), PCI_FUNC(devfn), 445812fd1fdSMichael Ellerman flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); 446812fd1fdSMichael Ellerman 447812fd1fdSMichael Ellerman if (!(flags & HT_MSI_FLAGS_ENABLE)) 448812fd1fdSMichael Ellerman writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); 449812fd1fdSMichael Ellerman } 450812fd1fdSMichael Ellerman #else 451812fd1fdSMichael Ellerman static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, 452812fd1fdSMichael Ellerman unsigned int devfn) 453812fd1fdSMichael Ellerman { 454812fd1fdSMichael Ellerman return; 455812fd1fdSMichael Ellerman } 456812fd1fdSMichael Ellerman #endif 457812fd1fdSMichael Ellerman 4581beb6a7dSBenjamin Herrenschmidt static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, 4591beb6a7dSBenjamin Herrenschmidt unsigned int devfn, u32 vdid) 46014cf11afSPaul Mackerras { 461c4b22f26SSegher Boessenkool int i, irq, n; 4621beb6a7dSBenjamin Herrenschmidt u8 __iomem *base; 46314cf11afSPaul Mackerras u32 tmp; 464c4b22f26SSegher Boessenkool u8 pos; 46514cf11afSPaul Mackerras 4661beb6a7dSBenjamin Herrenschmidt for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 4671beb6a7dSBenjamin Herrenschmidt pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 4681beb6a7dSBenjamin Herrenschmidt u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 46946ff3463SBrice Goglin if (id == PCI_CAP_ID_HT) { 470c4b22f26SSegher Boessenkool id = readb(devbase + pos + 3); 471beb7cc82SMichael Ellerman if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) 472c4b22f26SSegher Boessenkool break; 473c4b22f26SSegher Boessenkool } 474c4b22f26SSegher Boessenkool } 475c4b22f26SSegher Boessenkool if (pos == 0) 476c4b22f26SSegher Boessenkool return; 477c4b22f26SSegher Boessenkool 4781beb6a7dSBenjamin Herrenschmidt base = devbase + pos; 4791beb6a7dSBenjamin Herrenschmidt writeb(0x01, base + 2); 4801beb6a7dSBenjamin Herrenschmidt n = (readl(base + 4) >> 16) & 0xff; 481c4b22f26SSegher Boessenkool 4821beb6a7dSBenjamin Herrenschmidt printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" 4831beb6a7dSBenjamin Herrenschmidt " has %d irqs\n", 4841beb6a7dSBenjamin Herrenschmidt devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); 485c4b22f26SSegher Boessenkool 486c4b22f26SSegher Boessenkool for (i = 0; i <= n; i++) { 4871beb6a7dSBenjamin Herrenschmidt writeb(0x10 + 2 * i, base + 2); 4881beb6a7dSBenjamin Herrenschmidt tmp = readl(base + 4); 48914cf11afSPaul Mackerras irq = (tmp >> 16) & 0xff; 4901beb6a7dSBenjamin Herrenschmidt DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); 4911beb6a7dSBenjamin Herrenschmidt /* mask it , will be unmasked later */ 4921beb6a7dSBenjamin Herrenschmidt tmp |= 0x1; 4931beb6a7dSBenjamin Herrenschmidt writel(tmp, base + 4); 4941beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].index = i; 4951beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].base = base; 4961beb6a7dSBenjamin Herrenschmidt /* Apple HT PIC has a non-standard way of doing EOIs */ 4971beb6a7dSBenjamin Herrenschmidt if ((vdid & 0xffff) == 0x106b) 4981beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].applebase = devbase + 0x60; 4991beb6a7dSBenjamin Herrenschmidt else 5001beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].applebase = NULL; 5011beb6a7dSBenjamin Herrenschmidt writeb(0x11 + 2 * i, base + 2); 5021beb6a7dSBenjamin Herrenschmidt mpic->fixups[irq].data = readl(base + 4) | 0x80000000; 50314cf11afSPaul Mackerras } 50414cf11afSPaul Mackerras } 50514cf11afSPaul Mackerras 50614cf11afSPaul Mackerras 5071beb6a7dSBenjamin Herrenschmidt static void __init mpic_scan_ht_pics(struct mpic *mpic) 50814cf11afSPaul Mackerras { 50914cf11afSPaul Mackerras unsigned int devfn; 51014cf11afSPaul Mackerras u8 __iomem *cfgspace; 51114cf11afSPaul Mackerras 5121beb6a7dSBenjamin Herrenschmidt printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); 51314cf11afSPaul Mackerras 51414cf11afSPaul Mackerras /* Allocate fixups array */ 515ea96025aSAnton Vorontsov mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); 51614cf11afSPaul Mackerras BUG_ON(mpic->fixups == NULL); 51714cf11afSPaul Mackerras 51814cf11afSPaul Mackerras /* Init spinlock */ 519203041adSThomas Gleixner raw_spin_lock_init(&mpic->fixup_lock); 52014cf11afSPaul Mackerras 521c4b22f26SSegher Boessenkool /* Map U3 config space. We assume all IO-APICs are on the primary bus 522c4b22f26SSegher Boessenkool * so we only need to map 64kB. 52314cf11afSPaul Mackerras */ 524c4b22f26SSegher Boessenkool cfgspace = ioremap(0xf2000000, 0x10000); 52514cf11afSPaul Mackerras BUG_ON(cfgspace == NULL); 52614cf11afSPaul Mackerras 5271beb6a7dSBenjamin Herrenschmidt /* Now we scan all slots. We do a very quick scan, we read the header 5281beb6a7dSBenjamin Herrenschmidt * type, vendor ID and device ID only, that's plenty enough 52914cf11afSPaul Mackerras */ 530c4b22f26SSegher Boessenkool for (devfn = 0; devfn < 0x100; devfn++) { 53114cf11afSPaul Mackerras u8 __iomem *devbase = cfgspace + (devfn << 8); 53214cf11afSPaul Mackerras u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); 53314cf11afSPaul Mackerras u32 l = readl(devbase + PCI_VENDOR_ID); 5341beb6a7dSBenjamin Herrenschmidt u16 s; 53514cf11afSPaul Mackerras 53614cf11afSPaul Mackerras DBG("devfn %x, l: %x\n", devfn, l); 53714cf11afSPaul Mackerras 53814cf11afSPaul Mackerras /* If no device, skip */ 53914cf11afSPaul Mackerras if (l == 0xffffffff || l == 0x00000000 || 54014cf11afSPaul Mackerras l == 0x0000ffff || l == 0xffff0000) 54114cf11afSPaul Mackerras goto next; 5421beb6a7dSBenjamin Herrenschmidt /* Check if is supports capability lists */ 5431beb6a7dSBenjamin Herrenschmidt s = readw(devbase + PCI_STATUS); 5441beb6a7dSBenjamin Herrenschmidt if (!(s & PCI_STATUS_CAP_LIST)) 5451beb6a7dSBenjamin Herrenschmidt goto next; 54614cf11afSPaul Mackerras 5471beb6a7dSBenjamin Herrenschmidt mpic_scan_ht_pic(mpic, devbase, devfn, l); 548812fd1fdSMichael Ellerman mpic_scan_ht_msi(mpic, devbase, devfn); 54914cf11afSPaul Mackerras 55014cf11afSPaul Mackerras next: 55114cf11afSPaul Mackerras /* next device, if function 0 */ 552c4b22f26SSegher Boessenkool if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) 55314cf11afSPaul Mackerras devfn += 7; 55414cf11afSPaul Mackerras } 55514cf11afSPaul Mackerras } 55614cf11afSPaul Mackerras 5576cfef5b2SMichael Ellerman #else /* CONFIG_MPIC_U3_HT_IRQS */ 5586e99e458SBenjamin Herrenschmidt 5596e99e458SBenjamin Herrenschmidt static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) 5606e99e458SBenjamin Herrenschmidt { 5616e99e458SBenjamin Herrenschmidt return 0; 5626e99e458SBenjamin Herrenschmidt } 5636e99e458SBenjamin Herrenschmidt 5646e99e458SBenjamin Herrenschmidt static void __init mpic_scan_ht_pics(struct mpic *mpic) 5656e99e458SBenjamin Herrenschmidt { 5666e99e458SBenjamin Herrenschmidt } 5676e99e458SBenjamin Herrenschmidt 5686cfef5b2SMichael Ellerman #endif /* CONFIG_MPIC_U3_HT_IRQS */ 56914cf11afSPaul Mackerras 5703c10c9c4SKumar Gala #ifdef CONFIG_SMP 57138e1313fSYang Li static int irq_choose_cpu(const cpumask_t *mask) 5723c10c9c4SKumar Gala { 5733c10c9c4SKumar Gala int cpuid; 5743c10c9c4SKumar Gala 57538e1313fSYang Li if (cpumask_equal(mask, cpu_all_mask)) { 5763c10c9c4SKumar Gala static int irq_rover; 577203041adSThomas Gleixner static DEFINE_RAW_SPINLOCK(irq_rover_lock); 5783c10c9c4SKumar Gala unsigned long flags; 5793c10c9c4SKumar Gala 5803c10c9c4SKumar Gala /* Round-robin distribution... */ 5813c10c9c4SKumar Gala do_round_robin: 582203041adSThomas Gleixner raw_spin_lock_irqsave(&irq_rover_lock, flags); 5833c10c9c4SKumar Gala 5843c10c9c4SKumar Gala while (!cpu_online(irq_rover)) { 5853c10c9c4SKumar Gala if (++irq_rover >= NR_CPUS) 5863c10c9c4SKumar Gala irq_rover = 0; 5873c10c9c4SKumar Gala } 5883c10c9c4SKumar Gala cpuid = irq_rover; 5893c10c9c4SKumar Gala do { 5903c10c9c4SKumar Gala if (++irq_rover >= NR_CPUS) 5913c10c9c4SKumar Gala irq_rover = 0; 5923c10c9c4SKumar Gala } while (!cpu_online(irq_rover)); 5933c10c9c4SKumar Gala 594203041adSThomas Gleixner raw_spin_unlock_irqrestore(&irq_rover_lock, flags); 5953c10c9c4SKumar Gala } else { 59638e1313fSYang Li cpuid = cpumask_first_and(mask, cpu_online_mask); 59738e1313fSYang Li if (cpuid >= nr_cpu_ids) 5983c10c9c4SKumar Gala goto do_round_robin; 5993c10c9c4SKumar Gala } 6003c10c9c4SKumar Gala 6017a0d7940SKumar Gala return get_hard_smp_processor_id(cpuid); 6023c10c9c4SKumar Gala } 6033c10c9c4SKumar Gala #else 60438e1313fSYang Li static int irq_choose_cpu(const cpumask_t *mask) 6053c10c9c4SKumar Gala { 6063c10c9c4SKumar Gala return hard_smp_processor_id(); 6073c10c9c4SKumar Gala } 6083c10c9c4SKumar Gala #endif 60914cf11afSPaul Mackerras 6100ebfff14SBenjamin Herrenschmidt #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 6110ebfff14SBenjamin Herrenschmidt 61214cf11afSPaul Mackerras /* Find an mpic associated with a given linux interrupt */ 613d69a78d7STony Breeds static struct mpic *mpic_find(unsigned int irq) 61414cf11afSPaul Mackerras { 6150ebfff14SBenjamin Herrenschmidt if (irq < NUM_ISA_INTERRUPTS) 61614cf11afSPaul Mackerras return NULL; 6170ebfff14SBenjamin Herrenschmidt 6186cff46f4SMichael Ellerman return irq_to_desc(irq)->chip_data; 61914cf11afSPaul Mackerras } 62014cf11afSPaul Mackerras 621d69a78d7STony Breeds /* Determine if the linux irq is an IPI */ 622d69a78d7STony Breeds static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) 623d69a78d7STony Breeds { 624d69a78d7STony Breeds unsigned int src = mpic_irq_to_hw(irq); 625d69a78d7STony Breeds 626d69a78d7STony Breeds return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); 627d69a78d7STony Breeds } 628d69a78d7STony Breeds 629d69a78d7STony Breeds 63014cf11afSPaul Mackerras /* Convert a cpu mask from logical to physical cpu numbers. */ 63114cf11afSPaul Mackerras static inline u32 mpic_physmask(u32 cpumask) 63214cf11afSPaul Mackerras { 63314cf11afSPaul Mackerras int i; 63414cf11afSPaul Mackerras u32 mask = 0; 63514cf11afSPaul Mackerras 63614cf11afSPaul Mackerras for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) 63714cf11afSPaul Mackerras mask |= (cpumask & 1) << get_hard_smp_processor_id(i); 63814cf11afSPaul Mackerras return mask; 63914cf11afSPaul Mackerras } 64014cf11afSPaul Mackerras 64114cf11afSPaul Mackerras #ifdef CONFIG_SMP 64214cf11afSPaul Mackerras /* Get the mpic structure from the IPI number */ 64314cf11afSPaul Mackerras static inline struct mpic * mpic_from_ipi(unsigned int ipi) 64414cf11afSPaul Mackerras { 6456cff46f4SMichael Ellerman return irq_to_desc(ipi)->chip_data; 64614cf11afSPaul Mackerras } 64714cf11afSPaul Mackerras #endif 64814cf11afSPaul Mackerras 64914cf11afSPaul Mackerras /* Get the mpic structure from the irq number */ 65014cf11afSPaul Mackerras static inline struct mpic * mpic_from_irq(unsigned int irq) 65114cf11afSPaul Mackerras { 6526cff46f4SMichael Ellerman return irq_to_desc(irq)->chip_data; 65314cf11afSPaul Mackerras } 65414cf11afSPaul Mackerras 65514cf11afSPaul Mackerras /* Send an EOI */ 65614cf11afSPaul Mackerras static inline void mpic_eoi(struct mpic *mpic) 65714cf11afSPaul Mackerras { 6587233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); 6597233593bSZang Roy-r61911 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); 66014cf11afSPaul Mackerras } 66114cf11afSPaul Mackerras 66214cf11afSPaul Mackerras /* 66314cf11afSPaul Mackerras * Linux descriptor level callbacks 66414cf11afSPaul Mackerras */ 66514cf11afSPaul Mackerras 66614cf11afSPaul Mackerras 66705af7bd2SMichael Ellerman void mpic_unmask_irq(unsigned int irq) 66814cf11afSPaul Mackerras { 66914cf11afSPaul Mackerras unsigned int loops = 100000; 67014cf11afSPaul Mackerras struct mpic *mpic = mpic_from_irq(irq); 6710ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 67214cf11afSPaul Mackerras 673bd561c79SPaul Mackerras DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 67414cf11afSPaul Mackerras 6757233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 6767233593bSZang Roy-r61911 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 677e5356640SBenjamin Herrenschmidt ~MPIC_VECPRI_MASK); 67814cf11afSPaul Mackerras /* make sure mask gets to controller before we return to user */ 67914cf11afSPaul Mackerras do { 68014cf11afSPaul Mackerras if (!loops--) { 68114cf11afSPaul Mackerras printk(KERN_ERR "mpic_enable_irq timeout\n"); 68214cf11afSPaul Mackerras break; 68314cf11afSPaul Mackerras } 6847233593bSZang Roy-r61911 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 6851beb6a7dSBenjamin Herrenschmidt } 6861beb6a7dSBenjamin Herrenschmidt 68705af7bd2SMichael Ellerman void mpic_mask_irq(unsigned int irq) 68814cf11afSPaul Mackerras { 68914cf11afSPaul Mackerras unsigned int loops = 100000; 69014cf11afSPaul Mackerras struct mpic *mpic = mpic_from_irq(irq); 6910ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 69214cf11afSPaul Mackerras 69314cf11afSPaul Mackerras DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 69414cf11afSPaul Mackerras 6957233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 6967233593bSZang Roy-r61911 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 697e5356640SBenjamin Herrenschmidt MPIC_VECPRI_MASK); 69814cf11afSPaul Mackerras 69914cf11afSPaul Mackerras /* make sure mask gets to controller before we return to user */ 70014cf11afSPaul Mackerras do { 70114cf11afSPaul Mackerras if (!loops--) { 70214cf11afSPaul Mackerras printk(KERN_ERR "mpic_enable_irq timeout\n"); 70314cf11afSPaul Mackerras break; 70414cf11afSPaul Mackerras } 7057233593bSZang Roy-r61911 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 70614cf11afSPaul Mackerras } 70714cf11afSPaul Mackerras 70805af7bd2SMichael Ellerman void mpic_end_irq(unsigned int irq) 70914cf11afSPaul Mackerras { 71014cf11afSPaul Mackerras struct mpic *mpic = mpic_from_irq(irq); 71114cf11afSPaul Mackerras 7121beb6a7dSBenjamin Herrenschmidt #ifdef DEBUG_IRQ 71314cf11afSPaul Mackerras DBG("%s: end_irq: %d\n", mpic->name, irq); 7141beb6a7dSBenjamin Herrenschmidt #endif 71514cf11afSPaul Mackerras /* We always EOI on end_irq() even for edge interrupts since that 71614cf11afSPaul Mackerras * should only lower the priority, the MPIC should have properly 71714cf11afSPaul Mackerras * latched another edge interrupt coming in anyway 71814cf11afSPaul Mackerras */ 71914cf11afSPaul Mackerras 72014cf11afSPaul Mackerras mpic_eoi(mpic); 72114cf11afSPaul Mackerras } 72214cf11afSPaul Mackerras 7236cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 724b9e5b4e6SBenjamin Herrenschmidt 725b9e5b4e6SBenjamin Herrenschmidt static void mpic_unmask_ht_irq(unsigned int irq) 726b9e5b4e6SBenjamin Herrenschmidt { 727b9e5b4e6SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(irq); 7280ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 729b9e5b4e6SBenjamin Herrenschmidt 730b9e5b4e6SBenjamin Herrenschmidt mpic_unmask_irq(irq); 731b9e5b4e6SBenjamin Herrenschmidt 7326cff46f4SMichael Ellerman if (irq_to_desc(irq)->status & IRQ_LEVEL) 733b9e5b4e6SBenjamin Herrenschmidt mpic_ht_end_irq(mpic, src); 734b9e5b4e6SBenjamin Herrenschmidt } 735b9e5b4e6SBenjamin Herrenschmidt 736b9e5b4e6SBenjamin Herrenschmidt static unsigned int mpic_startup_ht_irq(unsigned int irq) 737b9e5b4e6SBenjamin Herrenschmidt { 738b9e5b4e6SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(irq); 7390ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 740b9e5b4e6SBenjamin Herrenschmidt 741b9e5b4e6SBenjamin Herrenschmidt mpic_unmask_irq(irq); 7426cff46f4SMichael Ellerman mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status); 743b9e5b4e6SBenjamin Herrenschmidt 744b9e5b4e6SBenjamin Herrenschmidt return 0; 745b9e5b4e6SBenjamin Herrenschmidt } 746b9e5b4e6SBenjamin Herrenschmidt 747b9e5b4e6SBenjamin Herrenschmidt static void mpic_shutdown_ht_irq(unsigned int irq) 748b9e5b4e6SBenjamin Herrenschmidt { 749b9e5b4e6SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(irq); 7500ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 751b9e5b4e6SBenjamin Herrenschmidt 7526cff46f4SMichael Ellerman mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status); 753b9e5b4e6SBenjamin Herrenschmidt mpic_mask_irq(irq); 754b9e5b4e6SBenjamin Herrenschmidt } 755b9e5b4e6SBenjamin Herrenschmidt 756b9e5b4e6SBenjamin Herrenschmidt static void mpic_end_ht_irq(unsigned int irq) 757b9e5b4e6SBenjamin Herrenschmidt { 758b9e5b4e6SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(irq); 7590ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 760b9e5b4e6SBenjamin Herrenschmidt 761b9e5b4e6SBenjamin Herrenschmidt #ifdef DEBUG_IRQ 762b9e5b4e6SBenjamin Herrenschmidt DBG("%s: end_irq: %d\n", mpic->name, irq); 763b9e5b4e6SBenjamin Herrenschmidt #endif 764b9e5b4e6SBenjamin Herrenschmidt /* We always EOI on end_irq() even for edge interrupts since that 765b9e5b4e6SBenjamin Herrenschmidt * should only lower the priority, the MPIC should have properly 766b9e5b4e6SBenjamin Herrenschmidt * latched another edge interrupt coming in anyway 767b9e5b4e6SBenjamin Herrenschmidt */ 768b9e5b4e6SBenjamin Herrenschmidt 7696cff46f4SMichael Ellerman if (irq_to_desc(irq)->status & IRQ_LEVEL) 770b9e5b4e6SBenjamin Herrenschmidt mpic_ht_end_irq(mpic, src); 771b9e5b4e6SBenjamin Herrenschmidt mpic_eoi(mpic); 772b9e5b4e6SBenjamin Herrenschmidt } 7736cfef5b2SMichael Ellerman #endif /* !CONFIG_MPIC_U3_HT_IRQS */ 774b9e5b4e6SBenjamin Herrenschmidt 77514cf11afSPaul Mackerras #ifdef CONFIG_SMP 77614cf11afSPaul Mackerras 777b9e5b4e6SBenjamin Herrenschmidt static void mpic_unmask_ipi(unsigned int irq) 77814cf11afSPaul Mackerras { 77914cf11afSPaul Mackerras struct mpic *mpic = mpic_from_ipi(irq); 7807df2457dSOlof Johansson unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 78114cf11afSPaul Mackerras 78214cf11afSPaul Mackerras DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 78314cf11afSPaul Mackerras mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 78414cf11afSPaul Mackerras } 78514cf11afSPaul Mackerras 786b9e5b4e6SBenjamin Herrenschmidt static void mpic_mask_ipi(unsigned int irq) 78714cf11afSPaul Mackerras { 78814cf11afSPaul Mackerras /* NEVER disable an IPI... that's just plain wrong! */ 78914cf11afSPaul Mackerras } 79014cf11afSPaul Mackerras 79114cf11afSPaul Mackerras static void mpic_end_ipi(unsigned int irq) 79214cf11afSPaul Mackerras { 79314cf11afSPaul Mackerras struct mpic *mpic = mpic_from_ipi(irq); 79414cf11afSPaul Mackerras 79514cf11afSPaul Mackerras /* 79614cf11afSPaul Mackerras * IPIs are marked IRQ_PER_CPU. This has the side effect of 79714cf11afSPaul Mackerras * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from 79814cf11afSPaul Mackerras * applying to them. We EOI them late to avoid re-entering. 7996714465eSThomas Gleixner * We mark IPI's with IRQF_DISABLED as they must run with 80014cf11afSPaul Mackerras * irqs disabled. 80114cf11afSPaul Mackerras */ 80214cf11afSPaul Mackerras mpic_eoi(mpic); 80314cf11afSPaul Mackerras } 80414cf11afSPaul Mackerras 80514cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 80614cf11afSPaul Mackerras 807d5dedd45SYinghai Lu int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) 80814cf11afSPaul Mackerras { 80914cf11afSPaul Mackerras struct mpic *mpic = mpic_from_irq(irq); 8100ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 81114cf11afSPaul Mackerras 8123c10c9c4SKumar Gala if (mpic->flags & MPIC_SINGLE_DEST_CPU) { 81338e1313fSYang Li int cpuid = irq_choose_cpu(cpumask); 8143c10c9c4SKumar Gala 8153c10c9c4SKumar Gala mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); 8163c10c9c4SKumar Gala } else { 81714cf11afSPaul Mackerras cpumask_t tmp; 81814cf11afSPaul Mackerras 8190de26520SRusty Russell cpumask_and(&tmp, cpumask, cpu_online_mask); 82014cf11afSPaul Mackerras 8217233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 82214cf11afSPaul Mackerras mpic_physmask(cpus_addr(tmp)[0])); 82314cf11afSPaul Mackerras } 824d5dedd45SYinghai Lu 825d5dedd45SYinghai Lu return 0; 8263c10c9c4SKumar Gala } 82714cf11afSPaul Mackerras 8287233593bSZang Roy-r61911 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 8290ebfff14SBenjamin Herrenschmidt { 8300ebfff14SBenjamin Herrenschmidt /* Now convert sense value */ 8316e99e458SBenjamin Herrenschmidt switch(type & IRQ_TYPE_SENSE_MASK) { 8320ebfff14SBenjamin Herrenschmidt case IRQ_TYPE_EDGE_RISING: 8337233593bSZang Roy-r61911 return MPIC_INFO(VECPRI_SENSE_EDGE) | 8347233593bSZang Roy-r61911 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 8350ebfff14SBenjamin Herrenschmidt case IRQ_TYPE_EDGE_FALLING: 8366e99e458SBenjamin Herrenschmidt case IRQ_TYPE_EDGE_BOTH: 8377233593bSZang Roy-r61911 return MPIC_INFO(VECPRI_SENSE_EDGE) | 8387233593bSZang Roy-r61911 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 8390ebfff14SBenjamin Herrenschmidt case IRQ_TYPE_LEVEL_HIGH: 8407233593bSZang Roy-r61911 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 8417233593bSZang Roy-r61911 MPIC_INFO(VECPRI_POLARITY_POSITIVE); 8420ebfff14SBenjamin Herrenschmidt case IRQ_TYPE_LEVEL_LOW: 8430ebfff14SBenjamin Herrenschmidt default: 8447233593bSZang Roy-r61911 return MPIC_INFO(VECPRI_SENSE_LEVEL) | 8457233593bSZang Roy-r61911 MPIC_INFO(VECPRI_POLARITY_NEGATIVE); 8460ebfff14SBenjamin Herrenschmidt } 8476e99e458SBenjamin Herrenschmidt } 8486e99e458SBenjamin Herrenschmidt 84905af7bd2SMichael Ellerman int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 8506e99e458SBenjamin Herrenschmidt { 8516e99e458SBenjamin Herrenschmidt struct mpic *mpic = mpic_from_irq(virq); 8526e99e458SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(virq); 8536cff46f4SMichael Ellerman struct irq_desc *desc = irq_to_desc(virq); 8546e99e458SBenjamin Herrenschmidt unsigned int vecpri, vold, vnew; 8556e99e458SBenjamin Herrenschmidt 85606fe98e6SBenjamin Herrenschmidt DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 8576e99e458SBenjamin Herrenschmidt mpic, virq, src, flow_type); 8586e99e458SBenjamin Herrenschmidt 8596e99e458SBenjamin Herrenschmidt if (src >= mpic->irq_count) 8606e99e458SBenjamin Herrenschmidt return -EINVAL; 8616e99e458SBenjamin Herrenschmidt 8626e99e458SBenjamin Herrenschmidt if (flow_type == IRQ_TYPE_NONE) 8636e99e458SBenjamin Herrenschmidt if (mpic->senses && src < mpic->senses_count) 8646e99e458SBenjamin Herrenschmidt flow_type = mpic->senses[src]; 8656e99e458SBenjamin Herrenschmidt if (flow_type == IRQ_TYPE_NONE) 8666e99e458SBenjamin Herrenschmidt flow_type = IRQ_TYPE_LEVEL_LOW; 8676e99e458SBenjamin Herrenschmidt 8686e99e458SBenjamin Herrenschmidt desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 8696e99e458SBenjamin Herrenschmidt desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 8706e99e458SBenjamin Herrenschmidt if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 8716e99e458SBenjamin Herrenschmidt desc->status |= IRQ_LEVEL; 8726e99e458SBenjamin Herrenschmidt 8736e99e458SBenjamin Herrenschmidt if (mpic_is_ht_interrupt(mpic, src)) 8746e99e458SBenjamin Herrenschmidt vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 8756e99e458SBenjamin Herrenschmidt MPIC_VECPRI_SENSE_EDGE; 8766e99e458SBenjamin Herrenschmidt else 8777233593bSZang Roy-r61911 vecpri = mpic_type_to_vecpri(mpic, flow_type); 8786e99e458SBenjamin Herrenschmidt 8797233593bSZang Roy-r61911 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 8807233593bSZang Roy-r61911 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | 8817233593bSZang Roy-r61911 MPIC_INFO(VECPRI_SENSE_MASK)); 8826e99e458SBenjamin Herrenschmidt vnew |= vecpri; 8836e99e458SBenjamin Herrenschmidt if (vold != vnew) 8847233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 8856e99e458SBenjamin Herrenschmidt 8866e99e458SBenjamin Herrenschmidt return 0; 8870ebfff14SBenjamin Herrenschmidt } 8880ebfff14SBenjamin Herrenschmidt 88938958dd9SOlof Johansson void mpic_set_vector(unsigned int virq, unsigned int vector) 89038958dd9SOlof Johansson { 89138958dd9SOlof Johansson struct mpic *mpic = mpic_from_irq(virq); 89238958dd9SOlof Johansson unsigned int src = mpic_irq_to_hw(virq); 89338958dd9SOlof Johansson unsigned int vecpri; 89438958dd9SOlof Johansson 89538958dd9SOlof Johansson DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", 89638958dd9SOlof Johansson mpic, virq, src, vector); 89738958dd9SOlof Johansson 89838958dd9SOlof Johansson if (src >= mpic->irq_count) 89938958dd9SOlof Johansson return; 90038958dd9SOlof Johansson 90138958dd9SOlof Johansson vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); 90238958dd9SOlof Johansson vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); 90338958dd9SOlof Johansson vecpri |= vector; 90438958dd9SOlof Johansson mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 90538958dd9SOlof Johansson } 90638958dd9SOlof Johansson 907b9e5b4e6SBenjamin Herrenschmidt static struct irq_chip mpic_irq_chip = { 908b9e5b4e6SBenjamin Herrenschmidt .mask = mpic_mask_irq, 909b9e5b4e6SBenjamin Herrenschmidt .unmask = mpic_unmask_irq, 910b9e5b4e6SBenjamin Herrenschmidt .eoi = mpic_end_irq, 9116e99e458SBenjamin Herrenschmidt .set_type = mpic_set_irq_type, 912b9e5b4e6SBenjamin Herrenschmidt }; 913b9e5b4e6SBenjamin Herrenschmidt 914b9e5b4e6SBenjamin Herrenschmidt #ifdef CONFIG_SMP 915b9e5b4e6SBenjamin Herrenschmidt static struct irq_chip mpic_ipi_chip = { 916b9e5b4e6SBenjamin Herrenschmidt .mask = mpic_mask_ipi, 917b9e5b4e6SBenjamin Herrenschmidt .unmask = mpic_unmask_ipi, 918b9e5b4e6SBenjamin Herrenschmidt .eoi = mpic_end_ipi, 919b9e5b4e6SBenjamin Herrenschmidt }; 920b9e5b4e6SBenjamin Herrenschmidt #endif /* CONFIG_SMP */ 921b9e5b4e6SBenjamin Herrenschmidt 9226cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 923b9e5b4e6SBenjamin Herrenschmidt static struct irq_chip mpic_irq_ht_chip = { 924b9e5b4e6SBenjamin Herrenschmidt .startup = mpic_startup_ht_irq, 925b9e5b4e6SBenjamin Herrenschmidt .shutdown = mpic_shutdown_ht_irq, 926b9e5b4e6SBenjamin Herrenschmidt .mask = mpic_mask_irq, 927b9e5b4e6SBenjamin Herrenschmidt .unmask = mpic_unmask_ht_irq, 928b9e5b4e6SBenjamin Herrenschmidt .eoi = mpic_end_ht_irq, 9296e99e458SBenjamin Herrenschmidt .set_type = mpic_set_irq_type, 930b9e5b4e6SBenjamin Herrenschmidt }; 9316cfef5b2SMichael Ellerman #endif /* CONFIG_MPIC_U3_HT_IRQS */ 932b9e5b4e6SBenjamin Herrenschmidt 93314cf11afSPaul Mackerras 9340ebfff14SBenjamin Herrenschmidt static int mpic_host_match(struct irq_host *h, struct device_node *node) 9350ebfff14SBenjamin Herrenschmidt { 9360ebfff14SBenjamin Herrenschmidt /* Exact match, unless mpic node is NULL */ 93752964f87SMichael Ellerman return h->of_node == NULL || h->of_node == node; 9380ebfff14SBenjamin Herrenschmidt } 9390ebfff14SBenjamin Herrenschmidt 9400ebfff14SBenjamin Herrenschmidt static int mpic_host_map(struct irq_host *h, unsigned int virq, 9416e99e458SBenjamin Herrenschmidt irq_hw_number_t hw) 9420ebfff14SBenjamin Herrenschmidt { 9430ebfff14SBenjamin Herrenschmidt struct mpic *mpic = h->host_data; 9446e99e458SBenjamin Herrenschmidt struct irq_chip *chip; 9450ebfff14SBenjamin Herrenschmidt 94606fe98e6SBenjamin Herrenschmidt DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); 9470ebfff14SBenjamin Herrenschmidt 9487df2457dSOlof Johansson if (hw == mpic->spurious_vec) 9490ebfff14SBenjamin Herrenschmidt return -EINVAL; 9507fd72186SBenjamin Herrenschmidt if (mpic->protected && test_bit(hw, mpic->protected)) 9517fd72186SBenjamin Herrenschmidt return -EINVAL; 95206fe98e6SBenjamin Herrenschmidt 9530ebfff14SBenjamin Herrenschmidt #ifdef CONFIG_SMP 9547df2457dSOlof Johansson else if (hw >= mpic->ipi_vecs[0]) { 9550ebfff14SBenjamin Herrenschmidt WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 9560ebfff14SBenjamin Herrenschmidt 95706fe98e6SBenjamin Herrenschmidt DBG("mpic: mapping as IPI\n"); 9580ebfff14SBenjamin Herrenschmidt set_irq_chip_data(virq, mpic); 9590ebfff14SBenjamin Herrenschmidt set_irq_chip_and_handler(virq, &mpic->hc_ipi, 9600ebfff14SBenjamin Herrenschmidt handle_percpu_irq); 9610ebfff14SBenjamin Herrenschmidt return 0; 9620ebfff14SBenjamin Herrenschmidt } 9630ebfff14SBenjamin Herrenschmidt #endif /* CONFIG_SMP */ 9640ebfff14SBenjamin Herrenschmidt 9650ebfff14SBenjamin Herrenschmidt if (hw >= mpic->irq_count) 9660ebfff14SBenjamin Herrenschmidt return -EINVAL; 9670ebfff14SBenjamin Herrenschmidt 968a7de7c74SMichael Ellerman mpic_msi_reserve_hwirq(mpic, hw); 969a7de7c74SMichael Ellerman 9706e99e458SBenjamin Herrenschmidt /* Default chip */ 9710ebfff14SBenjamin Herrenschmidt chip = &mpic->hc_irq; 9720ebfff14SBenjamin Herrenschmidt 9736cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 9740ebfff14SBenjamin Herrenschmidt /* Check for HT interrupts, override vecpri */ 9756e99e458SBenjamin Herrenschmidt if (mpic_is_ht_interrupt(mpic, hw)) 9760ebfff14SBenjamin Herrenschmidt chip = &mpic->hc_ht_irq; 9776cfef5b2SMichael Ellerman #endif /* CONFIG_MPIC_U3_HT_IRQS */ 9780ebfff14SBenjamin Herrenschmidt 97906fe98e6SBenjamin Herrenschmidt DBG("mpic: mapping to irq chip @%p\n", chip); 9800ebfff14SBenjamin Herrenschmidt 9810ebfff14SBenjamin Herrenschmidt set_irq_chip_data(virq, mpic); 9820ebfff14SBenjamin Herrenschmidt set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 9836e99e458SBenjamin Herrenschmidt 9846e99e458SBenjamin Herrenschmidt /* Set default irq type */ 9856e99e458SBenjamin Herrenschmidt set_irq_type(virq, IRQ_TYPE_NONE); 9866e99e458SBenjamin Herrenschmidt 9870ebfff14SBenjamin Herrenschmidt return 0; 9880ebfff14SBenjamin Herrenschmidt } 9890ebfff14SBenjamin Herrenschmidt 9900ebfff14SBenjamin Herrenschmidt static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, 99140d50cf7SRoman Fietze const u32 *intspec, unsigned int intsize, 9920ebfff14SBenjamin Herrenschmidt irq_hw_number_t *out_hwirq, unsigned int *out_flags) 9930ebfff14SBenjamin Herrenschmidt 9940ebfff14SBenjamin Herrenschmidt { 9950ebfff14SBenjamin Herrenschmidt static unsigned char map_mpic_senses[4] = { 9960ebfff14SBenjamin Herrenschmidt IRQ_TYPE_EDGE_RISING, 9970ebfff14SBenjamin Herrenschmidt IRQ_TYPE_LEVEL_LOW, 9980ebfff14SBenjamin Herrenschmidt IRQ_TYPE_LEVEL_HIGH, 9990ebfff14SBenjamin Herrenschmidt IRQ_TYPE_EDGE_FALLING, 10000ebfff14SBenjamin Herrenschmidt }; 10010ebfff14SBenjamin Herrenschmidt 10020ebfff14SBenjamin Herrenschmidt *out_hwirq = intspec[0]; 100306fe98e6SBenjamin Herrenschmidt if (intsize > 1) { 100406fe98e6SBenjamin Herrenschmidt u32 mask = 0x3; 100506fe98e6SBenjamin Herrenschmidt 100606fe98e6SBenjamin Herrenschmidt /* Apple invented a new race of encoding on machines with 100706fe98e6SBenjamin Herrenschmidt * an HT APIC. They encode, among others, the index within 100806fe98e6SBenjamin Herrenschmidt * the HT APIC. We don't care about it here since thankfully, 100906fe98e6SBenjamin Herrenschmidt * it appears that they have the APIC already properly 101006fe98e6SBenjamin Herrenschmidt * configured, and thus our current fixup code that reads the 101106fe98e6SBenjamin Herrenschmidt * APIC config works fine. However, we still need to mask out 101206fe98e6SBenjamin Herrenschmidt * bits in the specifier to make sure we only get bit 0 which 101306fe98e6SBenjamin Herrenschmidt * is the level/edge bit (the only sense bit exposed by Apple), 101406fe98e6SBenjamin Herrenschmidt * as their bit 1 means something else. 101506fe98e6SBenjamin Herrenschmidt */ 101606fe98e6SBenjamin Herrenschmidt if (machine_is(powermac)) 101706fe98e6SBenjamin Herrenschmidt mask = 0x1; 101806fe98e6SBenjamin Herrenschmidt *out_flags = map_mpic_senses[intspec[1] & mask]; 101906fe98e6SBenjamin Herrenschmidt } else 10200ebfff14SBenjamin Herrenschmidt *out_flags = IRQ_TYPE_NONE; 10210ebfff14SBenjamin Herrenschmidt 102206fe98e6SBenjamin Herrenschmidt DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", 102306fe98e6SBenjamin Herrenschmidt intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); 102406fe98e6SBenjamin Herrenschmidt 10250ebfff14SBenjamin Herrenschmidt return 0; 10260ebfff14SBenjamin Herrenschmidt } 10270ebfff14SBenjamin Herrenschmidt 10280ebfff14SBenjamin Herrenschmidt static struct irq_host_ops mpic_host_ops = { 10290ebfff14SBenjamin Herrenschmidt .match = mpic_host_match, 10300ebfff14SBenjamin Herrenschmidt .map = mpic_host_map, 10310ebfff14SBenjamin Herrenschmidt .xlate = mpic_host_xlate, 10320ebfff14SBenjamin Herrenschmidt }; 10330ebfff14SBenjamin Herrenschmidt 103414cf11afSPaul Mackerras /* 103514cf11afSPaul Mackerras * Exported functions 103614cf11afSPaul Mackerras */ 103714cf11afSPaul Mackerras 10380ebfff14SBenjamin Herrenschmidt struct mpic * __init mpic_alloc(struct device_node *node, 1039a959ff56SBenjamin Herrenschmidt phys_addr_t phys_addr, 104014cf11afSPaul Mackerras unsigned int flags, 104114cf11afSPaul Mackerras unsigned int isu_size, 104214cf11afSPaul Mackerras unsigned int irq_count, 104314cf11afSPaul Mackerras const char *name) 104414cf11afSPaul Mackerras { 104514cf11afSPaul Mackerras struct mpic *mpic; 1046d9d1063dSJohannes Berg u32 greg_feature; 104714cf11afSPaul Mackerras const char *vers; 104814cf11afSPaul Mackerras int i; 10497df2457dSOlof Johansson int intvec_top; 1050a959ff56SBenjamin Herrenschmidt u64 paddr = phys_addr; 105114cf11afSPaul Mackerras 105285355bb2SKumar Gala mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); 105314cf11afSPaul Mackerras if (mpic == NULL) 105414cf11afSPaul Mackerras return NULL; 105514cf11afSPaul Mackerras 105614cf11afSPaul Mackerras mpic->name = name; 105714cf11afSPaul Mackerras 1058b9e5b4e6SBenjamin Herrenschmidt mpic->hc_irq = mpic_irq_chip; 1059b27df672SThomas Gleixner mpic->hc_irq.name = name; 106014cf11afSPaul Mackerras if (flags & MPIC_PRIMARY) 106114cf11afSPaul Mackerras mpic->hc_irq.set_affinity = mpic_set_affinity; 10626cfef5b2SMichael Ellerman #ifdef CONFIG_MPIC_U3_HT_IRQS 1063b9e5b4e6SBenjamin Herrenschmidt mpic->hc_ht_irq = mpic_irq_ht_chip; 1064b27df672SThomas Gleixner mpic->hc_ht_irq.name = name; 1065b9e5b4e6SBenjamin Herrenschmidt if (flags & MPIC_PRIMARY) 1066b9e5b4e6SBenjamin Herrenschmidt mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 10676cfef5b2SMichael Ellerman #endif /* CONFIG_MPIC_U3_HT_IRQS */ 1068fbf0274eSBenjamin Herrenschmidt 106914cf11afSPaul Mackerras #ifdef CONFIG_SMP 1070b9e5b4e6SBenjamin Herrenschmidt mpic->hc_ipi = mpic_ipi_chip; 1071b27df672SThomas Gleixner mpic->hc_ipi.name = name; 107214cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 107314cf11afSPaul Mackerras 107414cf11afSPaul Mackerras mpic->flags = flags; 107514cf11afSPaul Mackerras mpic->isu_size = isu_size; 107614cf11afSPaul Mackerras mpic->irq_count = irq_count; 107714cf11afSPaul Mackerras mpic->num_sources = 0; /* so far */ 107814cf11afSPaul Mackerras 10797df2457dSOlof Johansson if (flags & MPIC_LARGE_VECTORS) 10807df2457dSOlof Johansson intvec_top = 2047; 10817df2457dSOlof Johansson else 10827df2457dSOlof Johansson intvec_top = 255; 10837df2457dSOlof Johansson 10847df2457dSOlof Johansson mpic->timer_vecs[0] = intvec_top - 8; 10857df2457dSOlof Johansson mpic->timer_vecs[1] = intvec_top - 7; 10867df2457dSOlof Johansson mpic->timer_vecs[2] = intvec_top - 6; 10877df2457dSOlof Johansson mpic->timer_vecs[3] = intvec_top - 5; 10887df2457dSOlof Johansson mpic->ipi_vecs[0] = intvec_top - 4; 10897df2457dSOlof Johansson mpic->ipi_vecs[1] = intvec_top - 3; 10907df2457dSOlof Johansson mpic->ipi_vecs[2] = intvec_top - 2; 10917df2457dSOlof Johansson mpic->ipi_vecs[3] = intvec_top - 1; 10927df2457dSOlof Johansson mpic->spurious_vec = intvec_top; 10937df2457dSOlof Johansson 1094a959ff56SBenjamin Herrenschmidt /* Check for "big-endian" in device-tree */ 1095e2eb6392SStephen Rothwell if (node && of_get_property(node, "big-endian", NULL) != NULL) 1096a959ff56SBenjamin Herrenschmidt mpic->flags |= MPIC_BIG_ENDIAN; 1097a959ff56SBenjamin Herrenschmidt 10987fd72186SBenjamin Herrenschmidt /* Look for protected sources */ 10997fd72186SBenjamin Herrenschmidt if (node) { 1100d9d1063dSJohannes Berg int psize; 1101d9d1063dSJohannes Berg unsigned int bits, mapsize; 11027fd72186SBenjamin Herrenschmidt const u32 *psrc = 11037fd72186SBenjamin Herrenschmidt of_get_property(node, "protected-sources", &psize); 11047fd72186SBenjamin Herrenschmidt if (psrc) { 11057fd72186SBenjamin Herrenschmidt psize /= 4; 11067fd72186SBenjamin Herrenschmidt bits = intvec_top + 1; 11077fd72186SBenjamin Herrenschmidt mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); 1108ea96025aSAnton Vorontsov mpic->protected = kzalloc(mapsize, GFP_KERNEL); 11097fd72186SBenjamin Herrenschmidt BUG_ON(mpic->protected == NULL); 11107fd72186SBenjamin Herrenschmidt for (i = 0; i < psize; i++) { 11117fd72186SBenjamin Herrenschmidt if (psrc[i] > intvec_top) 11127fd72186SBenjamin Herrenschmidt continue; 11137fd72186SBenjamin Herrenschmidt __set_bit(psrc[i], mpic->protected); 11147fd72186SBenjamin Herrenschmidt } 11157fd72186SBenjamin Herrenschmidt } 11167fd72186SBenjamin Herrenschmidt } 1117a959ff56SBenjamin Herrenschmidt 11187233593bSZang Roy-r61911 #ifdef CONFIG_MPIC_WEIRD 11197233593bSZang Roy-r61911 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; 11207233593bSZang Roy-r61911 #endif 11217233593bSZang Roy-r61911 1122fbf0274eSBenjamin Herrenschmidt /* default register type */ 1123fbf0274eSBenjamin Herrenschmidt mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? 1124fbf0274eSBenjamin Herrenschmidt mpic_access_mmio_be : mpic_access_mmio_le; 1125fbf0274eSBenjamin Herrenschmidt 1126a959ff56SBenjamin Herrenschmidt /* If no physical address is passed in, a device-node is mandatory */ 1127a959ff56SBenjamin Herrenschmidt BUG_ON(paddr == 0 && node == NULL); 1128a959ff56SBenjamin Herrenschmidt 1129a959ff56SBenjamin Herrenschmidt /* If no physical address passed in, check if it's dcr based */ 11300411a5e2SMichael Ellerman if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { 1131fbf0274eSBenjamin Herrenschmidt #ifdef CONFIG_PPC_DCR 11320411a5e2SMichael Ellerman mpic->flags |= MPIC_USES_DCR; 1133fbf0274eSBenjamin Herrenschmidt mpic->reg_type = mpic_access_dcr; 1134fbf0274eSBenjamin Herrenschmidt #else 11350411a5e2SMichael Ellerman BUG(); 1136fbf0274eSBenjamin Herrenschmidt #endif /* CONFIG_PPC_DCR */ 11370411a5e2SMichael Ellerman } 1138fbf0274eSBenjamin Herrenschmidt 1139a959ff56SBenjamin Herrenschmidt /* If the MPIC is not DCR based, and no physical address was passed 1140a959ff56SBenjamin Herrenschmidt * in, try to obtain one 1141a959ff56SBenjamin Herrenschmidt */ 1142a959ff56SBenjamin Herrenschmidt if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { 1143d9d1063dSJohannes Berg const u32 *reg = of_get_property(node, "reg", NULL); 1144a959ff56SBenjamin Herrenschmidt BUG_ON(reg == NULL); 1145a959ff56SBenjamin Herrenschmidt paddr = of_translate_address(node, reg); 1146a959ff56SBenjamin Herrenschmidt BUG_ON(paddr == OF_BAD_ADDR); 1147a959ff56SBenjamin Herrenschmidt } 1148a959ff56SBenjamin Herrenschmidt 114914cf11afSPaul Mackerras /* Map the global registers */ 11505a2642f6SBenjamin Herrenschmidt mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 11515a2642f6SBenjamin Herrenschmidt mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 115214cf11afSPaul Mackerras 115314cf11afSPaul Mackerras /* Reset */ 115414cf11afSPaul Mackerras if (flags & MPIC_WANTS_RESET) { 11557233593bSZang Roy-r61911 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 11567233593bSZang Roy-r61911 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 115714cf11afSPaul Mackerras | MPIC_GREG_GCONF_RESET); 11587233593bSZang Roy-r61911 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 115914cf11afSPaul Mackerras & MPIC_GREG_GCONF_RESET) 116014cf11afSPaul Mackerras mb(); 116114cf11afSPaul Mackerras } 116214cf11afSPaul Mackerras 1163d91e4ea7SKumar Gala /* CoreInt */ 1164d91e4ea7SKumar Gala if (flags & MPIC_ENABLE_COREINT) 1165d91e4ea7SKumar Gala mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1166d91e4ea7SKumar Gala mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1167d91e4ea7SKumar Gala | MPIC_GREG_GCONF_COREINT); 1168d91e4ea7SKumar Gala 1169f365355eSOlof Johansson if (flags & MPIC_ENABLE_MCK) 1170f365355eSOlof Johansson mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1171f365355eSOlof Johansson mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1172f365355eSOlof Johansson | MPIC_GREG_GCONF_MCK); 1173f365355eSOlof Johansson 117414cf11afSPaul Mackerras /* Read feature register, calculate num CPUs and, for non-ISU 117514cf11afSPaul Mackerras * MPICs, num sources as well. On ISU MPICs, sources are counted 117614cf11afSPaul Mackerras * as ISUs are added 117714cf11afSPaul Mackerras */ 1178d9d1063dSJohannes Berg greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); 1179d9d1063dSJohannes Berg mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) 118014cf11afSPaul Mackerras >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 11815073e7eeSAnton Vorontsov if (isu_size == 0) { 1182475ca391SKumar Gala if (flags & MPIC_BROKEN_FRR_NIRQS) 1183475ca391SKumar Gala mpic->num_sources = mpic->irq_count; 1184475ca391SKumar Gala else 1185d9d1063dSJohannes Berg mpic->num_sources = 1186d9d1063dSJohannes Berg ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) 118714cf11afSPaul Mackerras >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; 11885073e7eeSAnton Vorontsov } 118914cf11afSPaul Mackerras 119014cf11afSPaul Mackerras /* Map the per-CPU registers */ 119114cf11afSPaul Mackerras for (i = 0; i < mpic->num_cpus; i++) { 11925a2642f6SBenjamin Herrenschmidt mpic_map(mpic, node, paddr, &mpic->cpuregs[i], 1193fbf0274eSBenjamin Herrenschmidt MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1194fbf0274eSBenjamin Herrenschmidt 0x1000); 119514cf11afSPaul Mackerras } 119614cf11afSPaul Mackerras 119714cf11afSPaul Mackerras /* Initialize main ISU if none provided */ 119814cf11afSPaul Mackerras if (mpic->isu_size == 0) { 119914cf11afSPaul Mackerras mpic->isu_size = mpic->num_sources; 12005a2642f6SBenjamin Herrenschmidt mpic_map(mpic, node, paddr, &mpic->isus[0], 1201fbf0274eSBenjamin Herrenschmidt MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 120214cf11afSPaul Mackerras } 120314cf11afSPaul Mackerras mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 120414cf11afSPaul Mackerras mpic->isu_mask = (1 << mpic->isu_shift) - 1; 120514cf11afSPaul Mackerras 120631207dabSKumar Gala mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 120731207dabSKumar Gala isu_size ? isu_size : mpic->num_sources, 120831207dabSKumar Gala &mpic_host_ops, 120931207dabSKumar Gala flags & MPIC_LARGE_VECTORS ? 2048 : 256); 121031207dabSKumar Gala if (mpic->irqhost == NULL) 121131207dabSKumar Gala return NULL; 121231207dabSKumar Gala 121331207dabSKumar Gala mpic->irqhost->host_data = mpic; 121431207dabSKumar Gala 121514cf11afSPaul Mackerras /* Display version */ 1216d9d1063dSJohannes Berg switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { 121714cf11afSPaul Mackerras case 1: 121814cf11afSPaul Mackerras vers = "1.0"; 121914cf11afSPaul Mackerras break; 122014cf11afSPaul Mackerras case 2: 122114cf11afSPaul Mackerras vers = "1.2"; 122214cf11afSPaul Mackerras break; 122314cf11afSPaul Mackerras case 3: 122414cf11afSPaul Mackerras vers = "1.3"; 122514cf11afSPaul Mackerras break; 122614cf11afSPaul Mackerras default: 122714cf11afSPaul Mackerras vers = "<unknown>"; 122814cf11afSPaul Mackerras break; 122914cf11afSPaul Mackerras } 1230a959ff56SBenjamin Herrenschmidt printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," 1231a959ff56SBenjamin Herrenschmidt " max %d CPUs\n", 1232a959ff56SBenjamin Herrenschmidt name, vers, (unsigned long long)paddr, mpic->num_cpus); 1233a959ff56SBenjamin Herrenschmidt printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", 1234a959ff56SBenjamin Herrenschmidt mpic->isu_size, mpic->isu_shift, mpic->isu_mask); 123514cf11afSPaul Mackerras 123614cf11afSPaul Mackerras mpic->next = mpics; 123714cf11afSPaul Mackerras mpics = mpic; 123814cf11afSPaul Mackerras 12390ebfff14SBenjamin Herrenschmidt if (flags & MPIC_PRIMARY) { 124014cf11afSPaul Mackerras mpic_primary = mpic; 12410ebfff14SBenjamin Herrenschmidt irq_set_default_host(mpic->irqhost); 12420ebfff14SBenjamin Herrenschmidt } 124314cf11afSPaul Mackerras 124414cf11afSPaul Mackerras return mpic; 124514cf11afSPaul Mackerras } 124614cf11afSPaul Mackerras 124714cf11afSPaul Mackerras void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 1248a959ff56SBenjamin Herrenschmidt phys_addr_t paddr) 124914cf11afSPaul Mackerras { 125014cf11afSPaul Mackerras unsigned int isu_first = isu_num * mpic->isu_size; 125114cf11afSPaul Mackerras 125214cf11afSPaul Mackerras BUG_ON(isu_num >= MPIC_MAX_ISU); 125314cf11afSPaul Mackerras 12545a2642f6SBenjamin Herrenschmidt mpic_map(mpic, mpic->irqhost->of_node, 12555a2642f6SBenjamin Herrenschmidt paddr, &mpic->isus[isu_num], 0, 12567233593bSZang Roy-r61911 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 12575a2642f6SBenjamin Herrenschmidt 125814cf11afSPaul Mackerras if ((isu_first + mpic->isu_size) > mpic->num_sources) 125914cf11afSPaul Mackerras mpic->num_sources = isu_first + mpic->isu_size; 126014cf11afSPaul Mackerras } 126114cf11afSPaul Mackerras 12620ebfff14SBenjamin Herrenschmidt void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) 12630ebfff14SBenjamin Herrenschmidt { 12640ebfff14SBenjamin Herrenschmidt mpic->senses = senses; 12650ebfff14SBenjamin Herrenschmidt mpic->senses_count = count; 12660ebfff14SBenjamin Herrenschmidt } 12670ebfff14SBenjamin Herrenschmidt 126814cf11afSPaul Mackerras void __init mpic_init(struct mpic *mpic) 126914cf11afSPaul Mackerras { 127014cf11afSPaul Mackerras int i; 1271cc353c30SArnd Bergmann int cpu; 127214cf11afSPaul Mackerras 127314cf11afSPaul Mackerras BUG_ON(mpic->num_sources == 0); 127414cf11afSPaul Mackerras 127514cf11afSPaul Mackerras printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 127614cf11afSPaul Mackerras 127714cf11afSPaul Mackerras /* Set current processor priority to max */ 12787233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 127914cf11afSPaul Mackerras 128014cf11afSPaul Mackerras /* Initialize timers: just disable them all */ 128114cf11afSPaul Mackerras for (i = 0; i < 4; i++) { 128214cf11afSPaul Mackerras mpic_write(mpic->tmregs, 12837233593bSZang Roy-r61911 i * MPIC_INFO(TIMER_STRIDE) + 12847233593bSZang Roy-r61911 MPIC_INFO(TIMER_DESTINATION), 0); 128514cf11afSPaul Mackerras mpic_write(mpic->tmregs, 12867233593bSZang Roy-r61911 i * MPIC_INFO(TIMER_STRIDE) + 12877233593bSZang Roy-r61911 MPIC_INFO(TIMER_VECTOR_PRI), 128814cf11afSPaul Mackerras MPIC_VECPRI_MASK | 12897df2457dSOlof Johansson (mpic->timer_vecs[0] + i)); 129014cf11afSPaul Mackerras } 129114cf11afSPaul Mackerras 129214cf11afSPaul Mackerras /* Initialize IPIs to our reserved vectors and mark them disabled for now */ 129314cf11afSPaul Mackerras mpic_test_broken_ipi(mpic); 129414cf11afSPaul Mackerras for (i = 0; i < 4; i++) { 129514cf11afSPaul Mackerras mpic_ipi_write(i, 129614cf11afSPaul Mackerras MPIC_VECPRI_MASK | 129714cf11afSPaul Mackerras (10 << MPIC_VECPRI_PRIORITY_SHIFT) | 12987df2457dSOlof Johansson (mpic->ipi_vecs[0] + i)); 129914cf11afSPaul Mackerras } 130014cf11afSPaul Mackerras 130114cf11afSPaul Mackerras /* Initialize interrupt sources */ 130214cf11afSPaul Mackerras if (mpic->irq_count == 0) 130314cf11afSPaul Mackerras mpic->irq_count = mpic->num_sources; 130414cf11afSPaul Mackerras 13051beb6a7dSBenjamin Herrenschmidt /* Do the HT PIC fixups on U3 broken mpic */ 130614cf11afSPaul Mackerras DBG("MPIC flags: %x\n", mpic->flags); 130705af7bd2SMichael Ellerman if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { 13081beb6a7dSBenjamin Herrenschmidt mpic_scan_ht_pics(mpic); 130905af7bd2SMichael Ellerman mpic_u3msi_init(mpic); 131005af7bd2SMichael Ellerman } 131114cf11afSPaul Mackerras 131238958dd9SOlof Johansson mpic_pasemi_msi_init(mpic); 131338958dd9SOlof Johansson 1314cc353c30SArnd Bergmann if (mpic->flags & MPIC_PRIMARY) 1315cc353c30SArnd Bergmann cpu = hard_smp_processor_id(); 1316cc353c30SArnd Bergmann else 1317cc353c30SArnd Bergmann cpu = 0; 1318cc353c30SArnd Bergmann 131914cf11afSPaul Mackerras for (i = 0; i < mpic->num_sources; i++) { 132014cf11afSPaul Mackerras /* start with vector = source number, and masked */ 13216e99e458SBenjamin Herrenschmidt u32 vecpri = MPIC_VECPRI_MASK | i | 13226e99e458SBenjamin Herrenschmidt (8 << MPIC_VECPRI_PRIORITY_SHIFT); 132314cf11afSPaul Mackerras 13247fd72186SBenjamin Herrenschmidt /* check if protected */ 13257fd72186SBenjamin Herrenschmidt if (mpic->protected && test_bit(i, mpic->protected)) 13267fd72186SBenjamin Herrenschmidt continue; 132714cf11afSPaul Mackerras /* init hw */ 13287233593bSZang Roy-r61911 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1329cc353c30SArnd Bergmann mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); 133014cf11afSPaul Mackerras } 133114cf11afSPaul Mackerras 13327df2457dSOlof Johansson /* Init spurious vector */ 13337df2457dSOlof Johansson mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); 133414cf11afSPaul Mackerras 13357233593bSZang Roy-r61911 /* Disable 8259 passthrough, if supported */ 13367233593bSZang Roy-r61911 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) 13377233593bSZang Roy-r61911 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 13387233593bSZang Roy-r61911 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 133914cf11afSPaul Mackerras | MPIC_GREG_GCONF_8259_PTHROU_DIS); 134014cf11afSPaul Mackerras 1341d87bf3beSOlof Johansson if (mpic->flags & MPIC_NO_BIAS) 1342d87bf3beSOlof Johansson mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1343d87bf3beSOlof Johansson mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1344d87bf3beSOlof Johansson | MPIC_GREG_GCONF_NO_BIAS); 1345d87bf3beSOlof Johansson 134614cf11afSPaul Mackerras /* Set current processor priority to 0 */ 13477233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 13483669e930SJohannes Berg 13493669e930SJohannes Berg #ifdef CONFIG_PM 13503669e930SJohannes Berg /* allocate memory to save mpic state */ 1351ea96025aSAnton Vorontsov mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), 1352ea96025aSAnton Vorontsov GFP_KERNEL); 13533669e930SJohannes Berg BUG_ON(mpic->save_data == NULL); 13543669e930SJohannes Berg #endif 135514cf11afSPaul Mackerras } 135614cf11afSPaul Mackerras 1357868ea0c9SMark A. Greer void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1358868ea0c9SMark A. Greer { 1359868ea0c9SMark A. Greer u32 v; 136014cf11afSPaul Mackerras 1361868ea0c9SMark A. Greer v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1362868ea0c9SMark A. Greer v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; 1363868ea0c9SMark A. Greer v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); 1364868ea0c9SMark A. Greer mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1365868ea0c9SMark A. Greer } 1366868ea0c9SMark A. Greer 1367868ea0c9SMark A. Greer void __init mpic_set_serial_int(struct mpic *mpic, int enable) 1368868ea0c9SMark A. Greer { 1369ba1826e5SBenjamin Herrenschmidt unsigned long flags; 1370868ea0c9SMark A. Greer u32 v; 1371868ea0c9SMark A. Greer 1372203041adSThomas Gleixner raw_spin_lock_irqsave(&mpic_lock, flags); 1373868ea0c9SMark A. Greer v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); 1374868ea0c9SMark A. Greer if (enable) 1375868ea0c9SMark A. Greer v |= MPIC_GREG_GLOBAL_CONF_1_SIE; 1376868ea0c9SMark A. Greer else 1377868ea0c9SMark A. Greer v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; 1378868ea0c9SMark A. Greer mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); 1379203041adSThomas Gleixner raw_spin_unlock_irqrestore(&mpic_lock, flags); 1380868ea0c9SMark A. Greer } 138114cf11afSPaul Mackerras 138214cf11afSPaul Mackerras void mpic_irq_set_priority(unsigned int irq, unsigned int pri) 138314cf11afSPaul Mackerras { 1384d69a78d7STony Breeds struct mpic *mpic = mpic_find(irq); 13850ebfff14SBenjamin Herrenschmidt unsigned int src = mpic_irq_to_hw(irq); 138614cf11afSPaul Mackerras unsigned long flags; 138714cf11afSPaul Mackerras u32 reg; 138814cf11afSPaul Mackerras 138906a901c5SStephen Rothwell if (!mpic) 139006a901c5SStephen Rothwell return; 139106a901c5SStephen Rothwell 1392203041adSThomas Gleixner raw_spin_lock_irqsave(&mpic_lock, flags); 1393d69a78d7STony Breeds if (mpic_is_ipi(mpic, irq)) { 13947df2457dSOlof Johansson reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & 1395e5356640SBenjamin Herrenschmidt ~MPIC_VECPRI_PRIORITY_MASK; 13967df2457dSOlof Johansson mpic_ipi_write(src - mpic->ipi_vecs[0], 139714cf11afSPaul Mackerras reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 139814cf11afSPaul Mackerras } else { 13997233593bSZang Roy-r61911 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1400e5356640SBenjamin Herrenschmidt & ~MPIC_VECPRI_PRIORITY_MASK; 14017233593bSZang Roy-r61911 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 140214cf11afSPaul Mackerras reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 140314cf11afSPaul Mackerras } 1404203041adSThomas Gleixner raw_spin_unlock_irqrestore(&mpic_lock, flags); 140514cf11afSPaul Mackerras } 140614cf11afSPaul Mackerras 140714cf11afSPaul Mackerras void mpic_setup_this_cpu(void) 140814cf11afSPaul Mackerras { 140914cf11afSPaul Mackerras #ifdef CONFIG_SMP 141014cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 141114cf11afSPaul Mackerras unsigned long flags; 141214cf11afSPaul Mackerras u32 msk = 1 << hard_smp_processor_id(); 141314cf11afSPaul Mackerras unsigned int i; 141414cf11afSPaul Mackerras 141514cf11afSPaul Mackerras BUG_ON(mpic == NULL); 141614cf11afSPaul Mackerras 141714cf11afSPaul Mackerras DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 141814cf11afSPaul Mackerras 1419203041adSThomas Gleixner raw_spin_lock_irqsave(&mpic_lock, flags); 142014cf11afSPaul Mackerras 142114cf11afSPaul Mackerras /* let the mpic know we want intrs. default affinity is 0xffffffff 142214cf11afSPaul Mackerras * until changed via /proc. That's how it's done on x86. If we want 142314cf11afSPaul Mackerras * it differently, then we should make sure we also change the default 1424a53da52fSIngo Molnar * values of irq_desc[].affinity in irq.c. 142514cf11afSPaul Mackerras */ 142614cf11afSPaul Mackerras if (distribute_irqs) { 142714cf11afSPaul Mackerras for (i = 0; i < mpic->num_sources ; i++) 14287233593bSZang Roy-r61911 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 14297233593bSZang Roy-r61911 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); 143014cf11afSPaul Mackerras } 143114cf11afSPaul Mackerras 143214cf11afSPaul Mackerras /* Set current processor priority to 0 */ 14337233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); 143414cf11afSPaul Mackerras 1435203041adSThomas Gleixner raw_spin_unlock_irqrestore(&mpic_lock, flags); 143614cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 143714cf11afSPaul Mackerras } 143814cf11afSPaul Mackerras 143914cf11afSPaul Mackerras int mpic_cpu_get_priority(void) 144014cf11afSPaul Mackerras { 144114cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 144214cf11afSPaul Mackerras 14437233593bSZang Roy-r61911 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); 144414cf11afSPaul Mackerras } 144514cf11afSPaul Mackerras 144614cf11afSPaul Mackerras void mpic_cpu_set_priority(int prio) 144714cf11afSPaul Mackerras { 144814cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 144914cf11afSPaul Mackerras 145014cf11afSPaul Mackerras prio &= MPIC_CPU_TASKPRI_MASK; 14517233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); 145214cf11afSPaul Mackerras } 145314cf11afSPaul Mackerras 145414cf11afSPaul Mackerras void mpic_teardown_this_cpu(int secondary) 145514cf11afSPaul Mackerras { 145614cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 145714cf11afSPaul Mackerras unsigned long flags; 145814cf11afSPaul Mackerras u32 msk = 1 << hard_smp_processor_id(); 145914cf11afSPaul Mackerras unsigned int i; 146014cf11afSPaul Mackerras 146114cf11afSPaul Mackerras BUG_ON(mpic == NULL); 146214cf11afSPaul Mackerras 146314cf11afSPaul Mackerras DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); 1464203041adSThomas Gleixner raw_spin_lock_irqsave(&mpic_lock, flags); 146514cf11afSPaul Mackerras 146614cf11afSPaul Mackerras /* let the mpic know we don't want intrs. */ 146714cf11afSPaul Mackerras for (i = 0; i < mpic->num_sources ; i++) 14687233593bSZang Roy-r61911 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 14697233593bSZang Roy-r61911 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); 147014cf11afSPaul Mackerras 147114cf11afSPaul Mackerras /* Set current processor priority to max */ 14727233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 14737132799bSValentine Barshak /* We need to EOI the IPI since not all platforms reset the MPIC 14747132799bSValentine Barshak * on boot and new interrupts wouldn't get delivered otherwise. 14757132799bSValentine Barshak */ 14767132799bSValentine Barshak mpic_eoi(mpic); 147714cf11afSPaul Mackerras 1478203041adSThomas Gleixner raw_spin_unlock_irqrestore(&mpic_lock, flags); 147914cf11afSPaul Mackerras } 148014cf11afSPaul Mackerras 148114cf11afSPaul Mackerras 148214cf11afSPaul Mackerras void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) 148314cf11afSPaul Mackerras { 148414cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 148514cf11afSPaul Mackerras 148614cf11afSPaul Mackerras BUG_ON(mpic == NULL); 148714cf11afSPaul Mackerras 14881beb6a7dSBenjamin Herrenschmidt #ifdef DEBUG_IPI 148914cf11afSPaul Mackerras DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 14901beb6a7dSBenjamin Herrenschmidt #endif 149114cf11afSPaul Mackerras 14927233593bSZang Roy-r61911 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + 14937233593bSZang Roy-r61911 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), 149414cf11afSPaul Mackerras mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 149514cf11afSPaul Mackerras } 149614cf11afSPaul Mackerras 1497f365355eSOlof Johansson static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) 149814cf11afSPaul Mackerras { 14990ebfff14SBenjamin Herrenschmidt u32 src; 150014cf11afSPaul Mackerras 1501f365355eSOlof Johansson src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); 15021beb6a7dSBenjamin Herrenschmidt #ifdef DEBUG_LOW 1503f365355eSOlof Johansson DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); 15041beb6a7dSBenjamin Herrenschmidt #endif 15055cddd2e3SJosh Boyer if (unlikely(src == mpic->spurious_vec)) { 15065cddd2e3SJosh Boyer if (mpic->flags & MPIC_SPV_EOI) 15075cddd2e3SJosh Boyer mpic_eoi(mpic); 15080ebfff14SBenjamin Herrenschmidt return NO_IRQ; 15095cddd2e3SJosh Boyer } 15107fd72186SBenjamin Herrenschmidt if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 15117fd72186SBenjamin Herrenschmidt if (printk_ratelimit()) 15127fd72186SBenjamin Herrenschmidt printk(KERN_WARNING "%s: Got protected source %d !\n", 15137fd72186SBenjamin Herrenschmidt mpic->name, (int)src); 15147fd72186SBenjamin Herrenschmidt mpic_eoi(mpic); 15157fd72186SBenjamin Herrenschmidt return NO_IRQ; 15167fd72186SBenjamin Herrenschmidt } 15177fd72186SBenjamin Herrenschmidt 15180ebfff14SBenjamin Herrenschmidt return irq_linear_revmap(mpic->irqhost, src); 151914cf11afSPaul Mackerras } 152014cf11afSPaul Mackerras 1521f365355eSOlof Johansson unsigned int mpic_get_one_irq(struct mpic *mpic) 1522f365355eSOlof Johansson { 1523f365355eSOlof Johansson return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); 1524f365355eSOlof Johansson } 1525f365355eSOlof Johansson 152635a84c2fSOlaf Hering unsigned int mpic_get_irq(void) 152714cf11afSPaul Mackerras { 152814cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 152914cf11afSPaul Mackerras 153014cf11afSPaul Mackerras BUG_ON(mpic == NULL); 153114cf11afSPaul Mackerras 153235a84c2fSOlaf Hering return mpic_get_one_irq(mpic); 153314cf11afSPaul Mackerras } 153414cf11afSPaul Mackerras 1535d91e4ea7SKumar Gala unsigned int mpic_get_coreint_irq(void) 1536d91e4ea7SKumar Gala { 1537d91e4ea7SKumar Gala #ifdef CONFIG_BOOKE 1538d91e4ea7SKumar Gala struct mpic *mpic = mpic_primary; 1539d91e4ea7SKumar Gala u32 src; 1540d91e4ea7SKumar Gala 1541d91e4ea7SKumar Gala BUG_ON(mpic == NULL); 1542d91e4ea7SKumar Gala 1543d91e4ea7SKumar Gala src = mfspr(SPRN_EPR); 1544d91e4ea7SKumar Gala 1545d91e4ea7SKumar Gala if (unlikely(src == mpic->spurious_vec)) { 1546d91e4ea7SKumar Gala if (mpic->flags & MPIC_SPV_EOI) 1547d91e4ea7SKumar Gala mpic_eoi(mpic); 1548d91e4ea7SKumar Gala return NO_IRQ; 1549d91e4ea7SKumar Gala } 1550d91e4ea7SKumar Gala if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { 1551d91e4ea7SKumar Gala if (printk_ratelimit()) 1552d91e4ea7SKumar Gala printk(KERN_WARNING "%s: Got protected source %d !\n", 1553d91e4ea7SKumar Gala mpic->name, (int)src); 1554d91e4ea7SKumar Gala return NO_IRQ; 1555d91e4ea7SKumar Gala } 1556d91e4ea7SKumar Gala 1557d91e4ea7SKumar Gala return irq_linear_revmap(mpic->irqhost, src); 1558d91e4ea7SKumar Gala #else 1559d91e4ea7SKumar Gala return NO_IRQ; 1560d91e4ea7SKumar Gala #endif 1561d91e4ea7SKumar Gala } 1562d91e4ea7SKumar Gala 1563f365355eSOlof Johansson unsigned int mpic_get_mcirq(void) 1564f365355eSOlof Johansson { 1565f365355eSOlof Johansson struct mpic *mpic = mpic_primary; 1566f365355eSOlof Johansson 1567f365355eSOlof Johansson BUG_ON(mpic == NULL); 1568f365355eSOlof Johansson 1569f365355eSOlof Johansson return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); 1570f365355eSOlof Johansson } 157114cf11afSPaul Mackerras 157214cf11afSPaul Mackerras #ifdef CONFIG_SMP 157314cf11afSPaul Mackerras void mpic_request_ipis(void) 157414cf11afSPaul Mackerras { 157514cf11afSPaul Mackerras struct mpic *mpic = mpic_primary; 157678608dd3SMilton Miller int i; 157714cf11afSPaul Mackerras BUG_ON(mpic == NULL); 157814cf11afSPaul Mackerras 15790ebfff14SBenjamin Herrenschmidt printk(KERN_INFO "mpic: requesting IPIs...\n"); 158014cf11afSPaul Mackerras 15810ebfff14SBenjamin Herrenschmidt for (i = 0; i < 4; i++) { 15820ebfff14SBenjamin Herrenschmidt unsigned int vipi = irq_create_mapping(mpic->irqhost, 15837df2457dSOlof Johansson mpic->ipi_vecs[0] + i); 15840ebfff14SBenjamin Herrenschmidt if (vipi == NO_IRQ) { 158578608dd3SMilton Miller printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); 158678608dd3SMilton Miller continue; 15870ebfff14SBenjamin Herrenschmidt } 158878608dd3SMilton Miller smp_request_message_ipi(vipi, i); 15890ebfff14SBenjamin Herrenschmidt } 159014cf11afSPaul Mackerras } 1591a9c59264SPaul Mackerras 1592a9c59264SPaul Mackerras void smp_mpic_message_pass(int target, int msg) 1593a9c59264SPaul Mackerras { 1594a9c59264SPaul Mackerras /* make sure we're sending something that translates to an IPI */ 1595a9c59264SPaul Mackerras if ((unsigned int)msg > 3) { 1596a9c59264SPaul Mackerras printk("SMP %d: smp_message_pass: unknown msg %d\n", 1597a9c59264SPaul Mackerras smp_processor_id(), msg); 1598a9c59264SPaul Mackerras return; 1599a9c59264SPaul Mackerras } 1600a9c59264SPaul Mackerras switch (target) { 1601a9c59264SPaul Mackerras case MSG_ALL: 1602a9c59264SPaul Mackerras mpic_send_ipi(msg, 0xffffffff); 1603a9c59264SPaul Mackerras break; 1604a9c59264SPaul Mackerras case MSG_ALL_BUT_SELF: 1605a9c59264SPaul Mackerras mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); 1606a9c59264SPaul Mackerras break; 1607a9c59264SPaul Mackerras default: 1608a9c59264SPaul Mackerras mpic_send_ipi(msg, 1 << target); 1609a9c59264SPaul Mackerras break; 1610a9c59264SPaul Mackerras } 1611a9c59264SPaul Mackerras } 1612775aeff4SMichael Ellerman 1613775aeff4SMichael Ellerman int __init smp_mpic_probe(void) 1614775aeff4SMichael Ellerman { 1615775aeff4SMichael Ellerman int nr_cpus; 1616775aeff4SMichael Ellerman 1617775aeff4SMichael Ellerman DBG("smp_mpic_probe()...\n"); 1618775aeff4SMichael Ellerman 1619775aeff4SMichael Ellerman nr_cpus = cpus_weight(cpu_possible_map); 1620775aeff4SMichael Ellerman 1621775aeff4SMichael Ellerman DBG("nr_cpus: %d\n", nr_cpus); 1622775aeff4SMichael Ellerman 1623775aeff4SMichael Ellerman if (nr_cpus > 1) 1624775aeff4SMichael Ellerman mpic_request_ipis(); 1625775aeff4SMichael Ellerman 1626775aeff4SMichael Ellerman return nr_cpus; 1627775aeff4SMichael Ellerman } 1628775aeff4SMichael Ellerman 1629775aeff4SMichael Ellerman void __devinit smp_mpic_setup_cpu(int cpu) 1630775aeff4SMichael Ellerman { 1631775aeff4SMichael Ellerman mpic_setup_this_cpu(); 1632775aeff4SMichael Ellerman } 163314cf11afSPaul Mackerras #endif /* CONFIG_SMP */ 16343669e930SJohannes Berg 16353669e930SJohannes Berg #ifdef CONFIG_PM 16363669e930SJohannes Berg static int mpic_suspend(struct sys_device *dev, pm_message_t state) 16373669e930SJohannes Berg { 16383669e930SJohannes Berg struct mpic *mpic = container_of(dev, struct mpic, sysdev); 16393669e930SJohannes Berg int i; 16403669e930SJohannes Berg 16413669e930SJohannes Berg for (i = 0; i < mpic->num_sources; i++) { 16423669e930SJohannes Berg mpic->save_data[i].vecprio = 16433669e930SJohannes Berg mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); 16443669e930SJohannes Berg mpic->save_data[i].dest = 16453669e930SJohannes Berg mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); 16463669e930SJohannes Berg } 16473669e930SJohannes Berg 16483669e930SJohannes Berg return 0; 16493669e930SJohannes Berg } 16503669e930SJohannes Berg 16513669e930SJohannes Berg static int mpic_resume(struct sys_device *dev) 16523669e930SJohannes Berg { 16533669e930SJohannes Berg struct mpic *mpic = container_of(dev, struct mpic, sysdev); 16543669e930SJohannes Berg int i; 16553669e930SJohannes Berg 16563669e930SJohannes Berg for (i = 0; i < mpic->num_sources; i++) { 16573669e930SJohannes Berg mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), 16583669e930SJohannes Berg mpic->save_data[i].vecprio); 16593669e930SJohannes Berg mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 16603669e930SJohannes Berg mpic->save_data[i].dest); 16613669e930SJohannes Berg 16623669e930SJohannes Berg #ifdef CONFIG_MPIC_U3_HT_IRQS 16633669e930SJohannes Berg { 16643669e930SJohannes Berg struct mpic_irq_fixup *fixup = &mpic->fixups[i]; 16653669e930SJohannes Berg 16663669e930SJohannes Berg if (fixup->base) { 16673669e930SJohannes Berg /* we use the lowest bit in an inverted meaning */ 16683669e930SJohannes Berg if ((mpic->save_data[i].fixup_data & 1) == 0) 16693669e930SJohannes Berg continue; 16703669e930SJohannes Berg 16713669e930SJohannes Berg /* Enable and configure */ 16723669e930SJohannes Berg writeb(0x10 + 2 * fixup->index, fixup->base + 2); 16733669e930SJohannes Berg 16743669e930SJohannes Berg writel(mpic->save_data[i].fixup_data & ~1, 16753669e930SJohannes Berg fixup->base + 4); 16763669e930SJohannes Berg } 16773669e930SJohannes Berg } 16783669e930SJohannes Berg #endif 16793669e930SJohannes Berg } /* end for loop */ 16803669e930SJohannes Berg 16813669e930SJohannes Berg return 0; 16823669e930SJohannes Berg } 16833669e930SJohannes Berg #endif 16843669e930SJohannes Berg 16853669e930SJohannes Berg static struct sysdev_class mpic_sysclass = { 16863669e930SJohannes Berg #ifdef CONFIG_PM 16873669e930SJohannes Berg .resume = mpic_resume, 16883669e930SJohannes Berg .suspend = mpic_suspend, 16893669e930SJohannes Berg #endif 1690af5ca3f4SKay Sievers .name = "mpic", 16913669e930SJohannes Berg }; 16923669e930SJohannes Berg 16933669e930SJohannes Berg static int mpic_init_sys(void) 16943669e930SJohannes Berg { 16953669e930SJohannes Berg struct mpic *mpic = mpics; 16963669e930SJohannes Berg int error, id = 0; 16973669e930SJohannes Berg 16983669e930SJohannes Berg error = sysdev_class_register(&mpic_sysclass); 16993669e930SJohannes Berg 17003669e930SJohannes Berg while (mpic && !error) { 17013669e930SJohannes Berg mpic->sysdev.cls = &mpic_sysclass; 17023669e930SJohannes Berg mpic->sysdev.id = id++; 17033669e930SJohannes Berg error = sysdev_register(&mpic->sysdev); 17043669e930SJohannes Berg mpic = mpic->next; 17053669e930SJohannes Berg } 17063669e930SJohannes Berg return error; 17073669e930SJohannes Berg } 17083669e930SJohannes Berg 17093669e930SJohannes Berg device_initcall(mpic_init_sys); 1710