1 /* 2 * Freescale MPC85xx/MPC86xx RapidIO RMU support 3 * 4 * Copyright 2009 Sysgo AG 5 * Thomas Moll <thomas.moll@sysgo.com> 6 * - fixed maintenance access routines, check for aligned access 7 * 8 * Copyright 2009 Integrated Device Technology, Inc. 9 * Alex Bounine <alexandre.bounine@idt.com> 10 * - Added Port-Write message handling 11 * - Added Machine Check exception handling 12 * 13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc. 14 * Zhang Wei <wei.zhang@freescale.com> 15 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com> 16 * Liu Gang <Gang.Liu@freescale.com> 17 * 18 * Copyright 2005 MontaVista Software, Inc. 19 * Matt Porter <mporter@kernel.crashing.org> 20 * 21 * This program is free software; you can redistribute it and/or modify it 22 * under the terms of the GNU General Public License as published by the 23 * Free Software Foundation; either version 2 of the License, or (at your 24 * option) any later version. 25 */ 26 27 #include <linux/types.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/interrupt.h> 30 #include <linux/of_platform.h> 31 #include <linux/slab.h> 32 33 #include "fsl_rio.h" 34 35 #define GET_RMM_HANDLE(mport) \ 36 (((struct rio_priv *)(mport->priv))->rmm_handle) 37 38 /* RapidIO definition irq, which read from OF-tree */ 39 #define IRQ_RIO_PW(m) (((struct fsl_rio_pw *)(m))->pwirq) 40 #define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq) 41 #define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq) 42 #define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq) 43 44 #define RIO_MIN_TX_RING_SIZE 2 45 #define RIO_MAX_TX_RING_SIZE 2048 46 #define RIO_MIN_RX_RING_SIZE 2 47 #define RIO_MAX_RX_RING_SIZE 2048 48 49 #define RIO_IPWMR_SEN 0x00100000 50 #define RIO_IPWMR_QFIE 0x00000100 51 #define RIO_IPWMR_EIE 0x00000020 52 #define RIO_IPWMR_CQ 0x00000002 53 #define RIO_IPWMR_PWE 0x00000001 54 55 #define RIO_IPWSR_QF 0x00100000 56 #define RIO_IPWSR_TE 0x00000080 57 #define RIO_IPWSR_QFI 0x00000010 58 #define RIO_IPWSR_PWD 0x00000008 59 #define RIO_IPWSR_PWB 0x00000004 60 61 #define RIO_EPWISR 0x10010 62 /* EPWISR Error match value */ 63 #define RIO_EPWISR_PINT1 0x80000000 64 #define RIO_EPWISR_PINT2 0x40000000 65 #define RIO_EPWISR_MU 0x00000002 66 #define RIO_EPWISR_PW 0x00000001 67 68 #define IPWSR_CLEAR 0x98 69 #define OMSR_CLEAR 0x1cb3 70 #define IMSR_CLEAR 0x491 71 #define IDSR_CLEAR 0x91 72 #define ODSR_CLEAR 0x1c00 73 #define LTLEECSR_ENABLE_ALL 0xFFC000FC 74 #define RIO_LTLEECSR 0x060c 75 76 #define RIO_IM0SR 0x64 77 #define RIO_IM1SR 0x164 78 #define RIO_OM0SR 0x4 79 #define RIO_OM1SR 0x104 80 81 #define RIO_DBELL_WIN_SIZE 0x1000 82 83 #define RIO_MSG_OMR_MUI 0x00000002 84 #define RIO_MSG_OSR_TE 0x00000080 85 #define RIO_MSG_OSR_QOI 0x00000020 86 #define RIO_MSG_OSR_QFI 0x00000010 87 #define RIO_MSG_OSR_MUB 0x00000004 88 #define RIO_MSG_OSR_EOMI 0x00000002 89 #define RIO_MSG_OSR_QEI 0x00000001 90 91 #define RIO_MSG_IMR_MI 0x00000002 92 #define RIO_MSG_ISR_TE 0x00000080 93 #define RIO_MSG_ISR_QFI 0x00000010 94 #define RIO_MSG_ISR_DIQI 0x00000001 95 96 #define RIO_MSG_DESC_SIZE 32 97 #define RIO_MSG_BUFFER_SIZE 4096 98 99 #define DOORBELL_DMR_DI 0x00000002 100 #define DOORBELL_DSR_TE 0x00000080 101 #define DOORBELL_DSR_QFI 0x00000010 102 #define DOORBELL_DSR_DIQI 0x00000001 103 #define DOORBELL_TID_OFFSET 0x02 104 #define DOORBELL_SID_OFFSET 0x04 105 #define DOORBELL_INFO_OFFSET 0x06 106 107 #define DOORBELL_MESSAGE_SIZE 0x08 108 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) 109 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) 110 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) 111 112 struct rio_msg_regs { 113 u32 omr; 114 u32 osr; 115 u32 pad1; 116 u32 odqdpar; 117 u32 pad2; 118 u32 osar; 119 u32 odpr; 120 u32 odatr; 121 u32 odcr; 122 u32 pad3; 123 u32 odqepar; 124 u32 pad4[13]; 125 u32 imr; 126 u32 isr; 127 u32 pad5; 128 u32 ifqdpar; 129 u32 pad6; 130 u32 ifqepar; 131 }; 132 133 struct rio_dbell_regs { 134 u32 odmr; 135 u32 odsr; 136 u32 pad1[4]; 137 u32 oddpr; 138 u32 oddatr; 139 u32 pad2[3]; 140 u32 odretcr; 141 u32 pad3[12]; 142 u32 dmr; 143 u32 dsr; 144 u32 pad4; 145 u32 dqdpar; 146 u32 pad5; 147 u32 dqepar; 148 }; 149 150 struct rio_pw_regs { 151 u32 pwmr; 152 u32 pwsr; 153 u32 epwqbar; 154 u32 pwqbar; 155 }; 156 157 158 struct rio_tx_desc { 159 u32 pad1; 160 u32 saddr; 161 u32 dport; 162 u32 dattr; 163 u32 pad2; 164 u32 pad3; 165 u32 dwcnt; 166 u32 pad4; 167 }; 168 169 struct rio_msg_tx_ring { 170 void *virt; 171 dma_addr_t phys; 172 void *virt_buffer[RIO_MAX_TX_RING_SIZE]; 173 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; 174 int tx_slot; 175 int size; 176 void *dev_id; 177 }; 178 179 struct rio_msg_rx_ring { 180 void *virt; 181 dma_addr_t phys; 182 void *virt_buffer[RIO_MAX_RX_RING_SIZE]; 183 int rx_slot; 184 int size; 185 void *dev_id; 186 }; 187 188 struct fsl_rmu { 189 struct rio_msg_regs __iomem *msg_regs; 190 struct rio_msg_tx_ring msg_tx_ring; 191 struct rio_msg_rx_ring msg_rx_ring; 192 int txirq; 193 int rxirq; 194 }; 195 196 /** 197 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 198 * @irq: Linux interrupt number 199 * @dev_instance: Pointer to interrupt-specific data 200 * 201 * Handles outbound message interrupts. Executes a register outbound 202 * mailbox event handler and acks the interrupt occurrence. 203 */ 204 static irqreturn_t 205 fsl_rio_tx_handler(int irq, void *dev_instance) 206 { 207 int osr; 208 struct rio_mport *port = (struct rio_mport *)dev_instance; 209 struct fsl_rmu *rmu = GET_RMM_HANDLE(port); 210 211 osr = in_be32(&rmu->msg_regs->osr); 212 213 if (osr & RIO_MSG_OSR_TE) { 214 pr_info("RIO: outbound message transmission error\n"); 215 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE); 216 goto out; 217 } 218 219 if (osr & RIO_MSG_OSR_QOI) { 220 pr_info("RIO: outbound message queue overflow\n"); 221 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI); 222 goto out; 223 } 224 225 if (osr & RIO_MSG_OSR_EOMI) { 226 u32 dqp = in_be32(&rmu->msg_regs->odqdpar); 227 int slot = (dqp - rmu->msg_tx_ring.phys) >> 5; 228 if (port->outb_msg[0].mcback != NULL) { 229 port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id, 230 -1, 231 slot); 232 } 233 /* Ack the end-of-message interrupt */ 234 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI); 235 } 236 237 out: 238 return IRQ_HANDLED; 239 } 240 241 /** 242 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler 243 * @irq: Linux interrupt number 244 * @dev_instance: Pointer to interrupt-specific data 245 * 246 * Handles inbound message interrupts. Executes a registered inbound 247 * mailbox event handler and acks the interrupt occurrence. 248 */ 249 static irqreturn_t 250 fsl_rio_rx_handler(int irq, void *dev_instance) 251 { 252 int isr; 253 struct rio_mport *port = (struct rio_mport *)dev_instance; 254 struct fsl_rmu *rmu = GET_RMM_HANDLE(port); 255 256 isr = in_be32(&rmu->msg_regs->isr); 257 258 if (isr & RIO_MSG_ISR_TE) { 259 pr_info("RIO: inbound message reception error\n"); 260 out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE); 261 goto out; 262 } 263 264 /* XXX Need to check/dispatch until queue empty */ 265 if (isr & RIO_MSG_ISR_DIQI) { 266 /* 267 * Can receive messages for any mailbox/letter to that 268 * mailbox destination. So, make the callback with an 269 * unknown/invalid mailbox number argument. 270 */ 271 if (port->inb_msg[0].mcback != NULL) 272 port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id, 273 -1, 274 -1); 275 276 /* Ack the queueing interrupt */ 277 out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI); 278 } 279 280 out: 281 return IRQ_HANDLED; 282 } 283 284 /** 285 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 286 * @irq: Linux interrupt number 287 * @dev_instance: Pointer to interrupt-specific data 288 * 289 * Handles doorbell interrupts. Parses a list of registered 290 * doorbell event handlers and executes a matching event handler. 291 */ 292 static irqreturn_t 293 fsl_rio_dbell_handler(int irq, void *dev_instance) 294 { 295 int dsr; 296 struct fsl_rio_dbell *fsl_dbell = (struct fsl_rio_dbell *)dev_instance; 297 int i; 298 299 dsr = in_be32(&fsl_dbell->dbell_regs->dsr); 300 301 if (dsr & DOORBELL_DSR_TE) { 302 pr_info("RIO: doorbell reception error\n"); 303 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE); 304 goto out; 305 } 306 307 if (dsr & DOORBELL_DSR_QFI) { 308 pr_info("RIO: doorbell queue full\n"); 309 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI); 310 } 311 312 /* XXX Need to check/dispatch until queue empty */ 313 if (dsr & DOORBELL_DSR_DIQI) { 314 u32 dmsg = 315 (u32) fsl_dbell->dbell_ring.virt + 316 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff); 317 struct rio_dbell *dbell; 318 int found = 0; 319 320 pr_debug 321 ("RIO: processing doorbell," 322 " sid %2.2x tid %2.2x info %4.4x\n", 323 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 324 325 for (i = 0; i < MAX_PORT_NUM; i++) { 326 if (fsl_dbell->mport[i]) { 327 list_for_each_entry(dbell, 328 &fsl_dbell->mport[i]->dbells, node) { 329 if ((dbell->res->start 330 <= DBELL_INF(dmsg)) 331 && (dbell->res->end 332 >= DBELL_INF(dmsg))) { 333 found = 1; 334 break; 335 } 336 } 337 if (found && dbell->dinb) { 338 dbell->dinb(fsl_dbell->mport[i], 339 dbell->dev_id, DBELL_SID(dmsg), 340 DBELL_TID(dmsg), 341 DBELL_INF(dmsg)); 342 break; 343 } 344 } 345 } 346 347 if (!found) { 348 pr_debug 349 ("RIO: spurious doorbell," 350 " sid %2.2x tid %2.2x info %4.4x\n", 351 DBELL_SID(dmsg), DBELL_TID(dmsg), 352 DBELL_INF(dmsg)); 353 } 354 setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); 355 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI); 356 } 357 358 out: 359 return IRQ_HANDLED; 360 } 361 362 void msg_unit_error_handler(void) 363 { 364 365 /*XXX: Error recovery is not implemented, we just clear errors */ 366 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 367 368 out_be32((u32 *)(rmu_regs_win + RIO_IM0SR), IMSR_CLEAR); 369 out_be32((u32 *)(rmu_regs_win + RIO_IM1SR), IMSR_CLEAR); 370 out_be32((u32 *)(rmu_regs_win + RIO_OM0SR), OMSR_CLEAR); 371 out_be32((u32 *)(rmu_regs_win + RIO_OM1SR), OMSR_CLEAR); 372 373 out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR); 374 out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR); 375 376 out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR); 377 } 378 379 /** 380 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler 381 * @irq: Linux interrupt number 382 * @dev_instance: Pointer to interrupt-specific data 383 * 384 * Handles port write interrupts. Parses a list of registered 385 * port write event handlers and executes a matching event handler. 386 */ 387 static irqreturn_t 388 fsl_rio_port_write_handler(int irq, void *dev_instance) 389 { 390 u32 ipwmr, ipwsr; 391 struct fsl_rio_pw *pw = (struct fsl_rio_pw *)dev_instance; 392 u32 epwisr, tmp; 393 394 epwisr = in_be32(rio_regs_win + RIO_EPWISR); 395 if (!(epwisr & RIO_EPWISR_PW)) 396 goto pw_done; 397 398 ipwmr = in_be32(&pw->pw_regs->pwmr); 399 ipwsr = in_be32(&pw->pw_regs->pwsr); 400 401 #ifdef DEBUG_PW 402 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); 403 if (ipwsr & RIO_IPWSR_QF) 404 pr_debug(" QF"); 405 if (ipwsr & RIO_IPWSR_TE) 406 pr_debug(" TE"); 407 if (ipwsr & RIO_IPWSR_QFI) 408 pr_debug(" QFI"); 409 if (ipwsr & RIO_IPWSR_PWD) 410 pr_debug(" PWD"); 411 if (ipwsr & RIO_IPWSR_PWB) 412 pr_debug(" PWB"); 413 pr_debug(" )\n"); 414 #endif 415 /* Schedule deferred processing if PW was received */ 416 if (ipwsr & RIO_IPWSR_QFI) { 417 /* Save PW message (if there is room in FIFO), 418 * otherwise discard it. 419 */ 420 if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) { 421 pw->port_write_msg.msg_count++; 422 kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt, 423 RIO_PW_MSG_SIZE); 424 } else { 425 pw->port_write_msg.discard_count++; 426 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", 427 pw->port_write_msg.discard_count); 428 } 429 /* Clear interrupt and issue Clear Queue command. This allows 430 * another port-write to be received. 431 */ 432 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_QFI); 433 out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ); 434 435 schedule_work(&pw->pw_work); 436 } 437 438 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { 439 pw->port_write_msg.err_count++; 440 pr_debug("RIO: Port-Write Transaction Err (%d)\n", 441 pw->port_write_msg.err_count); 442 /* Clear Transaction Error: port-write controller should be 443 * disabled when clearing this error 444 */ 445 out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); 446 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_TE); 447 out_be32(&pw->pw_regs->pwmr, ipwmr); 448 } 449 450 if (ipwsr & RIO_IPWSR_PWD) { 451 pw->port_write_msg.discard_count++; 452 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", 453 pw->port_write_msg.discard_count); 454 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD); 455 } 456 457 pw_done: 458 if (epwisr & RIO_EPWISR_PINT1) { 459 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); 460 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 461 fsl_rio_port_error_handler(0); 462 } 463 464 if (epwisr & RIO_EPWISR_PINT2) { 465 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); 466 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 467 fsl_rio_port_error_handler(1); 468 } 469 470 if (epwisr & RIO_EPWISR_MU) { 471 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); 472 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 473 msg_unit_error_handler(); 474 } 475 476 return IRQ_HANDLED; 477 } 478 479 static void fsl_pw_dpc(struct work_struct *work) 480 { 481 struct fsl_rio_pw *pw = container_of(work, struct fsl_rio_pw, pw_work); 482 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; 483 484 /* 485 * Process port-write messages 486 */ 487 while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)msg_buffer, 488 RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) { 489 /* Process one message */ 490 #ifdef DEBUG_PW 491 { 492 u32 i; 493 pr_debug("%s : Port-Write Message:", __func__); 494 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { 495 if ((i%4) == 0) 496 pr_debug("\n0x%02x: 0x%08x", i*4, 497 msg_buffer[i]); 498 else 499 pr_debug(" 0x%08x", msg_buffer[i]); 500 } 501 pr_debug("\n"); 502 } 503 #endif 504 /* Pass the port-write message to RIO core for processing */ 505 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); 506 } 507 } 508 509 /** 510 * fsl_rio_pw_enable - enable/disable port-write interface init 511 * @mport: Master port implementing the port write unit 512 * @enable: 1=enable; 0=disable port-write message handling 513 */ 514 int fsl_rio_pw_enable(struct rio_mport *mport, int enable) 515 { 516 u32 rval; 517 518 rval = in_be32(&pw->pw_regs->pwmr); 519 520 if (enable) 521 rval |= RIO_IPWMR_PWE; 522 else 523 rval &= ~RIO_IPWMR_PWE; 524 525 out_be32(&pw->pw_regs->pwmr, rval); 526 527 return 0; 528 } 529 530 /** 531 * fsl_rio_port_write_init - MPC85xx port write interface init 532 * @mport: Master port implementing the port write unit 533 * 534 * Initializes port write unit hardware and DMA buffer 535 * ring. Called from fsl_rio_setup(). Returns %0 on success 536 * or %-ENOMEM on failure. 537 */ 538 539 int fsl_rio_port_write_init(struct fsl_rio_pw *pw) 540 { 541 int rc = 0; 542 543 /* Following configurations require a disabled port write controller */ 544 out_be32(&pw->pw_regs->pwmr, 545 in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE); 546 547 /* Initialize port write */ 548 pw->port_write_msg.virt = dma_alloc_coherent(pw->dev, 549 RIO_PW_MSG_SIZE, 550 &pw->port_write_msg.phys, GFP_KERNEL); 551 if (!pw->port_write_msg.virt) { 552 pr_err("RIO: unable allocate port write queue\n"); 553 return -ENOMEM; 554 } 555 556 pw->port_write_msg.err_count = 0; 557 pw->port_write_msg.discard_count = 0; 558 559 /* Point dequeue/enqueue pointers at first entry */ 560 out_be32(&pw->pw_regs->epwqbar, 0); 561 out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys); 562 563 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", 564 in_be32(&pw->pw_regs->epwqbar), 565 in_be32(&pw->pw_regs->pwqbar)); 566 567 /* Clear interrupt status IPWSR */ 568 out_be32(&pw->pw_regs->pwsr, 569 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); 570 571 /* Configure port write contoller for snooping enable all reporting, 572 clear queue full */ 573 out_be32(&pw->pw_regs->pwmr, 574 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); 575 576 577 /* Hook up port-write handler */ 578 rc = request_irq(IRQ_RIO_PW(pw), fsl_rio_port_write_handler, 579 IRQF_SHARED, "port-write", (void *)pw); 580 if (rc < 0) { 581 pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); 582 goto err_out; 583 } 584 /* Enable Error Interrupt */ 585 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL); 586 587 INIT_WORK(&pw->pw_work, fsl_pw_dpc); 588 spin_lock_init(&pw->pw_fifo_lock); 589 if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { 590 pr_err("FIFO allocation failed\n"); 591 rc = -ENOMEM; 592 goto err_out_irq; 593 } 594 595 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", 596 in_be32(&pw->pw_regs->pwmr), 597 in_be32(&pw->pw_regs->pwsr)); 598 599 return rc; 600 601 err_out_irq: 602 free_irq(IRQ_RIO_PW(pw), (void *)pw); 603 err_out: 604 dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE, 605 pw->port_write_msg.virt, 606 pw->port_write_msg.phys); 607 return rc; 608 } 609 610 /** 611 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message 612 * @mport: RapidIO master port info 613 * @index: ID of RapidIO interface 614 * @destid: Destination ID of target device 615 * @data: 16-bit info field of RapidIO doorbell message 616 * 617 * Sends a MPC85xx doorbell message. Returns %0 on success or 618 * %-EINVAL on failure. 619 */ 620 int fsl_rio_doorbell_send(struct rio_mport *mport, 621 int index, u16 destid, u16 data) 622 { 623 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", 624 index, destid, data); 625 626 /* In the serial version silicons, such as MPC8548, MPC8641, 627 * below operations is must be. 628 */ 629 out_be32(&dbell->dbell_regs->odmr, 0x00000000); 630 out_be32(&dbell->dbell_regs->odretcr, 0x00000004); 631 out_be32(&dbell->dbell_regs->oddpr, destid << 16); 632 out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data); 633 out_be32(&dbell->dbell_regs->odmr, 0x00000001); 634 635 return 0; 636 } 637 638 /** 639 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue 640 * @mport: Master port with outbound message queue 641 * @rdev: Target of outbound message 642 * @mbox: Outbound mailbox 643 * @buffer: Message to add to outbound queue 644 * @len: Length of message 645 * 646 * Adds the @buffer message to the MPC85xx outbound message queue. Returns 647 * %0 on success or %-EINVAL on failure. 648 */ 649 int 650 fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 651 void *buffer, size_t len) 652 { 653 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 654 u32 omr; 655 struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt 656 + rmu->msg_tx_ring.tx_slot; 657 int ret = 0; 658 659 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ 660 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); 661 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 662 ret = -EINVAL; 663 goto out; 664 } 665 666 /* Copy and clear rest of buffer */ 667 memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer, 668 len); 669 if (len < (RIO_MAX_MSG_SIZE - 4)) 670 memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot] 671 + len, 0, RIO_MAX_MSG_SIZE - len); 672 673 /* Set mbox field for message, and set destid */ 674 desc->dport = (rdev->destid << 16) | (mbox & 0x3); 675 676 /* Enable EOMI interrupt and priority */ 677 desc->dattr = 0x28000000 | ((mport->index) << 20); 678 679 /* Set transfer size aligned to next power of 2 (in double words) */ 680 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); 681 682 /* Set snooping and source buffer address */ 683 desc->saddr = 0x00000004 684 | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot]; 685 686 /* Increment enqueue pointer */ 687 omr = in_be32(&rmu->msg_regs->omr); 688 out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI); 689 690 /* Go to next descriptor */ 691 if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size) 692 rmu->msg_tx_ring.tx_slot = 0; 693 694 out: 695 return ret; 696 } 697 698 /** 699 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox 700 * @mport: Master port implementing the outbound message unit 701 * @dev_id: Device specific pointer to pass on event 702 * @mbox: Mailbox to open 703 * @entries: Number of entries in the outbound mailbox ring 704 * 705 * Initializes buffer ring, request the outbound message interrupt, 706 * and enables the outbound message unit. Returns %0 on success and 707 * %-EINVAL or %-ENOMEM on failure. 708 */ 709 int 710 fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 711 { 712 int i, j, rc = 0; 713 struct rio_priv *priv = mport->priv; 714 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 715 716 if ((entries < RIO_MIN_TX_RING_SIZE) || 717 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { 718 rc = -EINVAL; 719 goto out; 720 } 721 722 /* Initialize shadow copy ring */ 723 rmu->msg_tx_ring.dev_id = dev_id; 724 rmu->msg_tx_ring.size = entries; 725 726 for (i = 0; i < rmu->msg_tx_ring.size; i++) { 727 rmu->msg_tx_ring.virt_buffer[i] = 728 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 729 &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL); 730 if (!rmu->msg_tx_ring.virt_buffer[i]) { 731 rc = -ENOMEM; 732 for (j = 0; j < rmu->msg_tx_ring.size; j++) 733 if (rmu->msg_tx_ring.virt_buffer[j]) 734 dma_free_coherent(priv->dev, 735 RIO_MSG_BUFFER_SIZE, 736 rmu->msg_tx_ring. 737 virt_buffer[j], 738 rmu->msg_tx_ring. 739 phys_buffer[j]); 740 goto out; 741 } 742 } 743 744 /* Initialize outbound message descriptor ring */ 745 rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, 746 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 747 &rmu->msg_tx_ring.phys, GFP_KERNEL); 748 if (!rmu->msg_tx_ring.virt) { 749 rc = -ENOMEM; 750 goto out_dma; 751 } 752 memset(rmu->msg_tx_ring.virt, 0, 753 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE); 754 rmu->msg_tx_ring.tx_slot = 0; 755 756 /* Point dequeue/enqueue pointers at first entry in ring */ 757 out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys); 758 out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys); 759 760 /* Configure for snooping */ 761 out_be32(&rmu->msg_regs->osar, 0x00000004); 762 763 /* Clear interrupt status */ 764 out_be32(&rmu->msg_regs->osr, 0x000000b3); 765 766 /* Hook up outbound message handler */ 767 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, 768 "msg_tx", (void *)mport); 769 if (rc < 0) 770 goto out_irq; 771 772 /* 773 * Configure outbound message unit 774 * Snooping 775 * Interrupts (all enabled, except QEIE) 776 * Chaining mode 777 * Disable 778 */ 779 out_be32(&rmu->msg_regs->omr, 0x00100220); 780 781 /* Set number of entries */ 782 out_be32(&rmu->msg_regs->omr, 783 in_be32(&rmu->msg_regs->omr) | 784 ((get_bitmask_order(entries) - 2) << 12)); 785 786 /* Now enable the unit */ 787 out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1); 788 789 out: 790 return rc; 791 792 out_irq: 793 dma_free_coherent(priv->dev, 794 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 795 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); 796 797 out_dma: 798 for (i = 0; i < rmu->msg_tx_ring.size; i++) 799 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 800 rmu->msg_tx_ring.virt_buffer[i], 801 rmu->msg_tx_ring.phys_buffer[i]); 802 803 return rc; 804 } 805 806 /** 807 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox 808 * @mport: Master port implementing the outbound message unit 809 * @mbox: Mailbox to close 810 * 811 * Disables the outbound message unit, free all buffers, and 812 * frees the outbound message interrupt. 813 */ 814 void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) 815 { 816 struct rio_priv *priv = mport->priv; 817 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 818 819 /* Disable inbound message unit */ 820 out_be32(&rmu->msg_regs->omr, 0); 821 822 /* Free ring */ 823 dma_free_coherent(priv->dev, 824 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 825 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); 826 827 /* Free interrupt */ 828 free_irq(IRQ_RIO_TX(mport), (void *)mport); 829 } 830 831 /** 832 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox 833 * @mport: Master port implementing the inbound message unit 834 * @dev_id: Device specific pointer to pass on event 835 * @mbox: Mailbox to open 836 * @entries: Number of entries in the inbound mailbox ring 837 * 838 * Initializes buffer ring, request the inbound message interrupt, 839 * and enables the inbound message unit. Returns %0 on success 840 * and %-EINVAL or %-ENOMEM on failure. 841 */ 842 int 843 fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 844 { 845 int i, rc = 0; 846 struct rio_priv *priv = mport->priv; 847 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 848 849 if ((entries < RIO_MIN_RX_RING_SIZE) || 850 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { 851 rc = -EINVAL; 852 goto out; 853 } 854 855 /* Initialize client buffer ring */ 856 rmu->msg_rx_ring.dev_id = dev_id; 857 rmu->msg_rx_ring.size = entries; 858 rmu->msg_rx_ring.rx_slot = 0; 859 for (i = 0; i < rmu->msg_rx_ring.size; i++) 860 rmu->msg_rx_ring.virt_buffer[i] = NULL; 861 862 /* Initialize inbound message ring */ 863 rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, 864 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 865 &rmu->msg_rx_ring.phys, GFP_KERNEL); 866 if (!rmu->msg_rx_ring.virt) { 867 rc = -ENOMEM; 868 goto out; 869 } 870 871 /* Point dequeue/enqueue pointers at first entry in ring */ 872 out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys); 873 out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys); 874 875 /* Clear interrupt status */ 876 out_be32(&rmu->msg_regs->isr, 0x00000091); 877 878 /* Hook up inbound message handler */ 879 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 880 "msg_rx", (void *)mport); 881 if (rc < 0) { 882 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 883 rmu->msg_tx_ring.virt_buffer[i], 884 rmu->msg_tx_ring.phys_buffer[i]); 885 goto out; 886 } 887 888 /* 889 * Configure inbound message unit: 890 * Snooping 891 * 4KB max message size 892 * Unmask all interrupt sources 893 * Disable 894 */ 895 out_be32(&rmu->msg_regs->imr, 0x001b0060); 896 897 /* Set number of queue entries */ 898 setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); 899 900 /* Now enable the unit */ 901 setbits32(&rmu->msg_regs->imr, 0x1); 902 903 out: 904 return rc; 905 } 906 907 /** 908 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox 909 * @mport: Master port implementing the inbound message unit 910 * @mbox: Mailbox to close 911 * 912 * Disables the inbound message unit, free all buffers, and 913 * frees the inbound message interrupt. 914 */ 915 void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) 916 { 917 struct rio_priv *priv = mport->priv; 918 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 919 920 /* Disable inbound message unit */ 921 out_be32(&rmu->msg_regs->imr, 0); 922 923 /* Free ring */ 924 dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 925 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); 926 927 /* Free interrupt */ 928 free_irq(IRQ_RIO_RX(mport), (void *)mport); 929 } 930 931 /** 932 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 933 * @mport: Master port implementing the inbound message unit 934 * @mbox: Inbound mailbox number 935 * @buf: Buffer to add to inbound queue 936 * 937 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 938 * %0 on success or %-EINVAL on failure. 939 */ 940 int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 941 { 942 int rc = 0; 943 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 944 945 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 946 rmu->msg_rx_ring.rx_slot); 947 948 if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) { 949 printk(KERN_ERR 950 "RIO: error adding inbound buffer %d, buffer exists\n", 951 rmu->msg_rx_ring.rx_slot); 952 rc = -EINVAL; 953 goto out; 954 } 955 956 rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf; 957 if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size) 958 rmu->msg_rx_ring.rx_slot = 0; 959 960 out: 961 return rc; 962 } 963 964 /** 965 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit 966 * @mport: Master port implementing the inbound message unit 967 * @mbox: Inbound mailbox number 968 * 969 * Gets the next available inbound message from the inbound message queue. 970 * A pointer to the message is returned on success or NULL on failure. 971 */ 972 void *fsl_get_inb_message(struct rio_mport *mport, int mbox) 973 { 974 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 975 u32 phys_buf, virt_buf; 976 void *buf = NULL; 977 int buf_idx; 978 979 phys_buf = in_be32(&rmu->msg_regs->ifqdpar); 980 981 /* If no more messages, then bail out */ 982 if (phys_buf == in_be32(&rmu->msg_regs->ifqepar)) 983 goto out2; 984 985 virt_buf = (u32) rmu->msg_rx_ring.virt + (phys_buf 986 - rmu->msg_rx_ring.phys); 987 buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 988 buf = rmu->msg_rx_ring.virt_buffer[buf_idx]; 989 990 if (!buf) { 991 printk(KERN_ERR 992 "RIO: inbound message copy failed, no buffers\n"); 993 goto out1; 994 } 995 996 /* Copy max message size, caller is expected to allocate that big */ 997 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); 998 999 /* Clear the available buffer */ 1000 rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; 1001 1002 out1: 1003 setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); 1004 1005 out2: 1006 return buf; 1007 } 1008 1009 /** 1010 * fsl_rio_doorbell_init - MPC85xx doorbell interface init 1011 * @mport: Master port implementing the inbound doorbell unit 1012 * 1013 * Initializes doorbell unit hardware and inbound DMA buffer 1014 * ring. Called from fsl_rio_setup(). Returns %0 on success 1015 * or %-ENOMEM on failure. 1016 */ 1017 int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell) 1018 { 1019 int rc = 0; 1020 1021 /* Initialize inbound doorbells */ 1022 dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 * 1023 DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL); 1024 if (!dbell->dbell_ring.virt) { 1025 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); 1026 rc = -ENOMEM; 1027 goto out; 1028 } 1029 1030 /* Point dequeue/enqueue pointers at first entry in ring */ 1031 out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys); 1032 out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys); 1033 1034 /* Clear interrupt status */ 1035 out_be32(&dbell->dbell_regs->dsr, 0x00000091); 1036 1037 /* Hook up doorbell handler */ 1038 rc = request_irq(IRQ_RIO_BELL(dbell), fsl_rio_dbell_handler, 0, 1039 "dbell_rx", (void *)dbell); 1040 if (rc < 0) { 1041 dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE, 1042 dbell->dbell_ring.virt, dbell->dbell_ring.phys); 1043 printk(KERN_ERR 1044 "MPC85xx RIO: unable to request inbound doorbell irq"); 1045 goto out; 1046 } 1047 1048 /* Configure doorbells for snooping, 512 entries, and enable */ 1049 out_be32(&dbell->dbell_regs->dmr, 0x00108161); 1050 1051 out: 1052 return rc; 1053 } 1054 1055 int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node) 1056 { 1057 struct rio_priv *priv; 1058 struct fsl_rmu *rmu; 1059 u64 msg_start; 1060 const u32 *msg_addr; 1061 int mlen; 1062 int aw; 1063 1064 if (!mport || !mport->priv) 1065 return -EINVAL; 1066 1067 priv = mport->priv; 1068 1069 if (!node) { 1070 dev_warn(priv->dev, "Can't get %s property 'fsl,rmu'\n", 1071 priv->dev->of_node->full_name); 1072 return -EINVAL; 1073 } 1074 1075 rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL); 1076 if (!rmu) 1077 return -ENOMEM; 1078 1079 aw = of_n_addr_cells(node); 1080 msg_addr = of_get_property(node, "reg", &mlen); 1081 if (!msg_addr) { 1082 pr_err("%s: unable to find 'reg' property of message-unit\n", 1083 node->full_name); 1084 kfree(rmu); 1085 return -ENOMEM; 1086 } 1087 msg_start = of_read_number(msg_addr, aw); 1088 1089 rmu->msg_regs = (struct rio_msg_regs *) 1090 (rmu_regs_win + (u32)msg_start); 1091 1092 rmu->txirq = irq_of_parse_and_map(node, 0); 1093 rmu->rxirq = irq_of_parse_and_map(node, 1); 1094 printk(KERN_INFO "%s: txirq: %d, rxirq %d\n", 1095 node->full_name, rmu->txirq, rmu->rxirq); 1096 1097 priv->rmm_handle = rmu; 1098 1099 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 1100 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 1101 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 1102 1103 return 0; 1104 } 1105