1 /* 2 * Freescale MPC85xx/MPC86xx RapidIO support 3 * 4 * Copyright 2009 Sysgo AG 5 * Thomas Moll <thomas.moll@sysgo.com> 6 * - fixed maintenance access routines, check for aligned access 7 * 8 * Copyright 2009 Integrated Device Technology, Inc. 9 * Alex Bounine <alexandre.bounine@idt.com> 10 * - Added Port-Write message handling 11 * - Added Machine Check exception handling 12 * 13 * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc. 14 * Zhang Wei <wei.zhang@freescale.com> 15 * 16 * Copyright 2005 MontaVista Software, Inc. 17 * Matt Porter <mporter@kernel.crashing.org> 18 * 19 * This program is free software; you can redistribute it and/or modify it 20 * under the terms of the GNU General Public License as published by the 21 * Free Software Foundation; either version 2 of the License, or (at your 22 * option) any later version. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/export.h> 27 #include <linux/types.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/interrupt.h> 30 #include <linux/device.h> 31 #include <linux/rio.h> 32 #include <linux/rio_drv.h> 33 #include <linux/of_platform.h> 34 #include <linux/delay.h> 35 #include <linux/slab.h> 36 #include <linux/kfifo.h> 37 38 #include <asm/io.h> 39 #include <asm/machdep.h> 40 #include <asm/uaccess.h> 41 42 #undef DEBUG_PW /* Port-Write debugging */ 43 44 /* RapidIO definition irq, which read from OF-tree */ 45 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) 46 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) 47 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) 48 #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) 49 50 #define IPWSR_CLEAR 0x98 51 #define OMSR_CLEAR 0x1cb3 52 #define IMSR_CLEAR 0x491 53 #define IDSR_CLEAR 0x91 54 #define ODSR_CLEAR 0x1c00 55 #define LTLEECSR_ENABLE_ALL 0xFFC000FC 56 #define ESCSR_CLEAR 0x07120204 57 #define IECSR_CLEAR 0x80000000 58 59 #define RIO_PORT1_EDCSR 0x0640 60 #define RIO_PORT2_EDCSR 0x0680 61 #define RIO_PORT1_IECSR 0x10130 62 #define RIO_PORT2_IECSR 0x101B0 63 #define RIO_IM0SR 0x13064 64 #define RIO_IM1SR 0x13164 65 #define RIO_OM0SR 0x13004 66 #define RIO_OM1SR 0x13104 67 68 #define RIO_ATMU_REGS_OFFSET 0x10c00 69 #define RIO_P_MSG_REGS_OFFSET 0x11000 70 #define RIO_S_MSG_REGS_OFFSET 0x13000 71 #define RIO_GCCSR 0x13c 72 #define RIO_ESCSR 0x158 73 #define RIO_PORT2_ESCSR 0x178 74 #define RIO_CCSR 0x15c 75 #define RIO_LTLEDCSR 0x0608 76 #define RIO_LTLEDCSR_IER 0x80000000 77 #define RIO_LTLEDCSR_PRT 0x01000000 78 #define RIO_LTLEECSR 0x060c 79 #define RIO_EPWISR 0x10010 80 #define RIO_ISR_AACR 0x10120 81 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 82 #define RIO_MAINT_WIN_SIZE 0x400000 83 #define RIO_DBELL_WIN_SIZE 0x1000 84 85 #define RIO_MSG_OMR_MUI 0x00000002 86 #define RIO_MSG_OSR_TE 0x00000080 87 #define RIO_MSG_OSR_QOI 0x00000020 88 #define RIO_MSG_OSR_QFI 0x00000010 89 #define RIO_MSG_OSR_MUB 0x00000004 90 #define RIO_MSG_OSR_EOMI 0x00000002 91 #define RIO_MSG_OSR_QEI 0x00000001 92 93 #define RIO_MSG_IMR_MI 0x00000002 94 #define RIO_MSG_ISR_TE 0x00000080 95 #define RIO_MSG_ISR_QFI 0x00000010 96 #define RIO_MSG_ISR_DIQI 0x00000001 97 98 #define RIO_IPWMR_SEN 0x00100000 99 #define RIO_IPWMR_QFIE 0x00000100 100 #define RIO_IPWMR_EIE 0x00000020 101 #define RIO_IPWMR_CQ 0x00000002 102 #define RIO_IPWMR_PWE 0x00000001 103 104 #define RIO_IPWSR_QF 0x00100000 105 #define RIO_IPWSR_TE 0x00000080 106 #define RIO_IPWSR_QFI 0x00000010 107 #define RIO_IPWSR_PWD 0x00000008 108 #define RIO_IPWSR_PWB 0x00000004 109 110 /* EPWISR Error match value */ 111 #define RIO_EPWISR_PINT1 0x80000000 112 #define RIO_EPWISR_PINT2 0x40000000 113 #define RIO_EPWISR_MU 0x00000002 114 #define RIO_EPWISR_PW 0x00000001 115 116 #define RIO_MSG_DESC_SIZE 32 117 #define RIO_MSG_BUFFER_SIZE 4096 118 #define RIO_MIN_TX_RING_SIZE 2 119 #define RIO_MAX_TX_RING_SIZE 2048 120 #define RIO_MIN_RX_RING_SIZE 2 121 #define RIO_MAX_RX_RING_SIZE 2048 122 123 #define DOORBELL_DMR_DI 0x00000002 124 #define DOORBELL_DSR_TE 0x00000080 125 #define DOORBELL_DSR_QFI 0x00000010 126 #define DOORBELL_DSR_DIQI 0x00000001 127 #define DOORBELL_TID_OFFSET 0x02 128 #define DOORBELL_SID_OFFSET 0x04 129 #define DOORBELL_INFO_OFFSET 0x06 130 131 #define DOORBELL_MESSAGE_SIZE 0x08 132 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) 133 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) 134 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) 135 136 struct rio_atmu_regs { 137 u32 rowtar; 138 u32 rowtear; 139 u32 rowbar; 140 u32 pad2; 141 u32 rowar; 142 u32 pad3[3]; 143 }; 144 145 struct rio_msg_regs { 146 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */ 147 u32 osr; /* 0xD_3004 - Outbound message 0 status register */ 148 u32 pad1; 149 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue 150 dequeue pointer address register */ 151 u32 pad2; 152 u32 osar; /* 0xD_3014 - Outbound message 0 source address 153 register */ 154 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port 155 register */ 156 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes 157 Register*/ 158 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count 159 register */ 160 u32 pad3; 161 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue 162 enqueue pointer address register */ 163 u32 pad4[13]; 164 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */ 165 u32 isr; /* 0xD_3064 - Inbound message 0 status register */ 166 u32 pad5; 167 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue 168 pointer address register*/ 169 u32 pad6; 170 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue 171 pointer address register */ 172 u32 pad7[226]; 173 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */ 174 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */ 175 u32 res0[4]; 176 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port 177 register */ 178 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes 179 register */ 180 u32 res1[3]; 181 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold 182 configuration register */ 183 u32 res2[12]; 184 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */ 185 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */ 186 u32 pad8; 187 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer 188 address register */ 189 u32 pad9; 190 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer 191 address register */ 192 u32 pad10[26]; 193 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */ 194 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */ 195 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address 196 register */ 197 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address 198 register */ 199 }; 200 201 struct rio_tx_desc { 202 u32 res1; 203 u32 saddr; 204 u32 dport; 205 u32 dattr; 206 u32 res2; 207 u32 res3; 208 u32 dwcnt; 209 u32 res4; 210 }; 211 212 struct rio_dbell_ring { 213 void *virt; 214 dma_addr_t phys; 215 }; 216 217 struct rio_msg_tx_ring { 218 void *virt; 219 dma_addr_t phys; 220 void *virt_buffer[RIO_MAX_TX_RING_SIZE]; 221 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; 222 int tx_slot; 223 int size; 224 void *dev_id; 225 }; 226 227 struct rio_msg_rx_ring { 228 void *virt; 229 dma_addr_t phys; 230 void *virt_buffer[RIO_MAX_RX_RING_SIZE]; 231 int rx_slot; 232 int size; 233 void *dev_id; 234 }; 235 236 struct rio_port_write_msg { 237 void *virt; 238 dma_addr_t phys; 239 u32 msg_count; 240 u32 err_count; 241 u32 discard_count; 242 }; 243 244 struct rio_priv { 245 struct device *dev; 246 void __iomem *regs_win; 247 struct rio_atmu_regs __iomem *atmu_regs; 248 struct rio_atmu_regs __iomem *maint_atmu_regs; 249 struct rio_atmu_regs __iomem *dbell_atmu_regs; 250 void __iomem *dbell_win; 251 void __iomem *maint_win; 252 struct rio_msg_regs __iomem *msg_regs; 253 struct rio_dbell_ring dbell_ring; 254 struct rio_msg_tx_ring msg_tx_ring; 255 struct rio_msg_rx_ring msg_rx_ring; 256 struct rio_port_write_msg port_write_msg; 257 int bellirq; 258 int txirq; 259 int rxirq; 260 int pwirq; 261 struct work_struct pw_work; 262 struct kfifo pw_fifo; 263 spinlock_t pw_fifo_lock; 264 }; 265 266 #define __fsl_read_rio_config(x, addr, err, op) \ 267 __asm__ __volatile__( \ 268 "1: "op" %1,0(%2)\n" \ 269 " eieio\n" \ 270 "2:\n" \ 271 ".section .fixup,\"ax\"\n" \ 272 "3: li %1,-1\n" \ 273 " li %0,%3\n" \ 274 " b 2b\n" \ 275 ".section __ex_table,\"a\"\n" \ 276 " .align 2\n" \ 277 " .long 1b,3b\n" \ 278 ".text" \ 279 : "=r" (err), "=r" (x) \ 280 : "b" (addr), "i" (-EFAULT), "0" (err)) 281 282 static void __iomem *rio_regs_win; 283 284 #ifdef CONFIG_E500 285 int fsl_rio_mcheck_exception(struct pt_regs *regs) 286 { 287 const struct exception_table_entry *entry; 288 unsigned long reason; 289 290 if (!rio_regs_win) 291 return 0; 292 293 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR)); 294 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) { 295 /* Check if we are prepared to handle this fault */ 296 entry = search_exception_tables(regs->nip); 297 if (entry) { 298 pr_debug("RIO: %s - MC Exception handled\n", 299 __func__); 300 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 301 0); 302 regs->msr |= MSR_RI; 303 regs->nip = entry->fixup; 304 return 1; 305 } 306 } 307 308 return 0; 309 } 310 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception); 311 #endif 312 313 /** 314 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message 315 * @mport: RapidIO master port info 316 * @index: ID of RapidIO interface 317 * @destid: Destination ID of target device 318 * @data: 16-bit info field of RapidIO doorbell message 319 * 320 * Sends a MPC85xx doorbell message. Returns %0 on success or 321 * %-EINVAL on failure. 322 */ 323 static int fsl_rio_doorbell_send(struct rio_mport *mport, 324 int index, u16 destid, u16 data) 325 { 326 struct rio_priv *priv = mport->priv; 327 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", 328 index, destid, data); 329 switch (mport->phy_type) { 330 case RIO_PHY_PARALLEL: 331 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22); 332 out_be16(priv->dbell_win, data); 333 break; 334 case RIO_PHY_SERIAL: 335 /* In the serial version silicons, such as MPC8548, MPC8641, 336 * below operations is must be. 337 */ 338 out_be32(&priv->msg_regs->odmr, 0x00000000); 339 out_be32(&priv->msg_regs->odretcr, 0x00000004); 340 out_be32(&priv->msg_regs->oddpr, destid << 16); 341 out_be32(&priv->msg_regs->oddatr, data); 342 out_be32(&priv->msg_regs->odmr, 0x00000001); 343 break; 344 } 345 346 return 0; 347 } 348 349 /** 350 * fsl_local_config_read - Generate a MPC85xx local config space read 351 * @mport: RapidIO master port info 352 * @index: ID of RapdiIO interface 353 * @offset: Offset into configuration space 354 * @len: Length (in bytes) of the maintenance transaction 355 * @data: Value to be read into 356 * 357 * Generates a MPC85xx local configuration space read. Returns %0 on 358 * success or %-EINVAL on failure. 359 */ 360 static int fsl_local_config_read(struct rio_mport *mport, 361 int index, u32 offset, int len, u32 *data) 362 { 363 struct rio_priv *priv = mport->priv; 364 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, 365 offset); 366 *data = in_be32(priv->regs_win + offset); 367 368 return 0; 369 } 370 371 /** 372 * fsl_local_config_write - Generate a MPC85xx local config space write 373 * @mport: RapidIO master port info 374 * @index: ID of RapdiIO interface 375 * @offset: Offset into configuration space 376 * @len: Length (in bytes) of the maintenance transaction 377 * @data: Value to be written 378 * 379 * Generates a MPC85xx local configuration space write. Returns %0 on 380 * success or %-EINVAL on failure. 381 */ 382 static int fsl_local_config_write(struct rio_mport *mport, 383 int index, u32 offset, int len, u32 data) 384 { 385 struct rio_priv *priv = mport->priv; 386 pr_debug 387 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 388 index, offset, data); 389 out_be32(priv->regs_win + offset, data); 390 391 return 0; 392 } 393 394 /** 395 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction 396 * @mport: RapidIO master port info 397 * @index: ID of RapdiIO interface 398 * @destid: Destination ID of transaction 399 * @hopcount: Number of hops to target device 400 * @offset: Offset into configuration space 401 * @len: Length (in bytes) of the maintenance transaction 402 * @val: Location to be read into 403 * 404 * Generates a MPC85xx read maintenance transaction. Returns %0 on 405 * success or %-EINVAL on failure. 406 */ 407 static int 408 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, 409 u8 hopcount, u32 offset, int len, u32 *val) 410 { 411 struct rio_priv *priv = mport->priv; 412 u8 *data; 413 u32 rval, err = 0; 414 415 pr_debug 416 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", 417 index, destid, hopcount, offset, len); 418 419 /* 16MB maintenance window possible */ 420 /* allow only aligned access to maintenance registers */ 421 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) 422 return -EINVAL; 423 424 out_be32(&priv->maint_atmu_regs->rowtar, 425 (destid << 22) | (hopcount << 12) | (offset >> 12)); 426 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 427 428 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 429 switch (len) { 430 case 1: 431 __fsl_read_rio_config(rval, data, err, "lbz"); 432 break; 433 case 2: 434 __fsl_read_rio_config(rval, data, err, "lhz"); 435 break; 436 case 4: 437 __fsl_read_rio_config(rval, data, err, "lwz"); 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 if (err) { 444 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n", 445 err, destid, hopcount, offset); 446 } 447 448 *val = rval; 449 450 return err; 451 } 452 453 /** 454 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction 455 * @mport: RapidIO master port info 456 * @index: ID of RapdiIO interface 457 * @destid: Destination ID of transaction 458 * @hopcount: Number of hops to target device 459 * @offset: Offset into configuration space 460 * @len: Length (in bytes) of the maintenance transaction 461 * @val: Value to be written 462 * 463 * Generates an MPC85xx write maintenance transaction. Returns %0 on 464 * success or %-EINVAL on failure. 465 */ 466 static int 467 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, 468 u8 hopcount, u32 offset, int len, u32 val) 469 { 470 struct rio_priv *priv = mport->priv; 471 u8 *data; 472 pr_debug 473 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 474 index, destid, hopcount, offset, len, val); 475 476 /* 16MB maintenance windows possible */ 477 /* allow only aligned access to maintenance registers */ 478 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) 479 return -EINVAL; 480 481 out_be32(&priv->maint_atmu_regs->rowtar, 482 (destid << 22) | (hopcount << 12) | (offset >> 12)); 483 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 484 485 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 486 switch (len) { 487 case 1: 488 out_8((u8 *) data, val); 489 break; 490 case 2: 491 out_be16((u16 *) data, val); 492 break; 493 case 4: 494 out_be32((u32 *) data, val); 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 return 0; 501 } 502 503 /** 504 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue 505 * @mport: Master port with outbound message queue 506 * @rdev: Target of outbound message 507 * @mbox: Outbound mailbox 508 * @buffer: Message to add to outbound queue 509 * @len: Length of message 510 * 511 * Adds the @buffer message to the MPC85xx outbound message queue. Returns 512 * %0 on success or %-EINVAL on failure. 513 */ 514 static int 515 fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 516 void *buffer, size_t len) 517 { 518 struct rio_priv *priv = mport->priv; 519 u32 omr; 520 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt 521 + priv->msg_tx_ring.tx_slot; 522 int ret = 0; 523 524 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ 525 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); 526 527 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 528 ret = -EINVAL; 529 goto out; 530 } 531 532 /* Copy and clear rest of buffer */ 533 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer, 534 len); 535 if (len < (RIO_MAX_MSG_SIZE - 4)) 536 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot] 537 + len, 0, RIO_MAX_MSG_SIZE - len); 538 539 switch (mport->phy_type) { 540 case RIO_PHY_PARALLEL: 541 /* Set mbox field for message */ 542 desc->dport = mbox & 0x3; 543 544 /* Enable EOMI interrupt, set priority, and set destid */ 545 desc->dattr = 0x28000000 | (rdev->destid << 2); 546 break; 547 case RIO_PHY_SERIAL: 548 /* Set mbox field for message, and set destid */ 549 desc->dport = (rdev->destid << 16) | (mbox & 0x3); 550 551 /* Enable EOMI interrupt and priority */ 552 desc->dattr = 0x28000000; 553 break; 554 } 555 556 /* Set transfer size aligned to next power of 2 (in double words) */ 557 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); 558 559 /* Set snooping and source buffer address */ 560 desc->saddr = 0x00000004 561 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot]; 562 563 /* Increment enqueue pointer */ 564 omr = in_be32(&priv->msg_regs->omr); 565 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI); 566 567 /* Go to next descriptor */ 568 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size) 569 priv->msg_tx_ring.tx_slot = 0; 570 571 out: 572 return ret; 573 } 574 575 /** 576 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 577 * @irq: Linux interrupt number 578 * @dev_instance: Pointer to interrupt-specific data 579 * 580 * Handles outbound message interrupts. Executes a register outbound 581 * mailbox event handler and acks the interrupt occurrence. 582 */ 583 static irqreturn_t 584 fsl_rio_tx_handler(int irq, void *dev_instance) 585 { 586 int osr; 587 struct rio_mport *port = (struct rio_mport *)dev_instance; 588 struct rio_priv *priv = port->priv; 589 590 osr = in_be32(&priv->msg_regs->osr); 591 592 if (osr & RIO_MSG_OSR_TE) { 593 pr_info("RIO: outbound message transmission error\n"); 594 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE); 595 goto out; 596 } 597 598 if (osr & RIO_MSG_OSR_QOI) { 599 pr_info("RIO: outbound message queue overflow\n"); 600 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI); 601 goto out; 602 } 603 604 if (osr & RIO_MSG_OSR_EOMI) { 605 u32 dqp = in_be32(&priv->msg_regs->odqdpar); 606 int slot = (dqp - priv->msg_tx_ring.phys) >> 5; 607 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1, 608 slot); 609 610 /* Ack the end-of-message interrupt */ 611 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI); 612 } 613 614 out: 615 return IRQ_HANDLED; 616 } 617 618 /** 619 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox 620 * @mport: Master port implementing the outbound message unit 621 * @dev_id: Device specific pointer to pass on event 622 * @mbox: Mailbox to open 623 * @entries: Number of entries in the outbound mailbox ring 624 * 625 * Initializes buffer ring, request the outbound message interrupt, 626 * and enables the outbound message unit. Returns %0 on success and 627 * %-EINVAL or %-ENOMEM on failure. 628 */ 629 static int 630 fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 631 { 632 int i, j, rc = 0; 633 struct rio_priv *priv = mport->priv; 634 635 if ((entries < RIO_MIN_TX_RING_SIZE) || 636 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { 637 rc = -EINVAL; 638 goto out; 639 } 640 641 /* Initialize shadow copy ring */ 642 priv->msg_tx_ring.dev_id = dev_id; 643 priv->msg_tx_ring.size = entries; 644 645 for (i = 0; i < priv->msg_tx_ring.size; i++) { 646 priv->msg_tx_ring.virt_buffer[i] = 647 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 648 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL); 649 if (!priv->msg_tx_ring.virt_buffer[i]) { 650 rc = -ENOMEM; 651 for (j = 0; j < priv->msg_tx_ring.size; j++) 652 if (priv->msg_tx_ring.virt_buffer[j]) 653 dma_free_coherent(priv->dev, 654 RIO_MSG_BUFFER_SIZE, 655 priv->msg_tx_ring. 656 virt_buffer[j], 657 priv->msg_tx_ring. 658 phys_buffer[j]); 659 goto out; 660 } 661 } 662 663 /* Initialize outbound message descriptor ring */ 664 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, 665 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 666 &priv->msg_tx_ring.phys, GFP_KERNEL); 667 if (!priv->msg_tx_ring.virt) { 668 rc = -ENOMEM; 669 goto out_dma; 670 } 671 memset(priv->msg_tx_ring.virt, 0, 672 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE); 673 priv->msg_tx_ring.tx_slot = 0; 674 675 /* Point dequeue/enqueue pointers at first entry in ring */ 676 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys); 677 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys); 678 679 /* Configure for snooping */ 680 out_be32(&priv->msg_regs->osar, 0x00000004); 681 682 /* Clear interrupt status */ 683 out_be32(&priv->msg_regs->osr, 0x000000b3); 684 685 /* Hook up outbound message handler */ 686 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, 687 "msg_tx", (void *)mport); 688 if (rc < 0) 689 goto out_irq; 690 691 /* 692 * Configure outbound message unit 693 * Snooping 694 * Interrupts (all enabled, except QEIE) 695 * Chaining mode 696 * Disable 697 */ 698 out_be32(&priv->msg_regs->omr, 0x00100220); 699 700 /* Set number of entries */ 701 out_be32(&priv->msg_regs->omr, 702 in_be32(&priv->msg_regs->omr) | 703 ((get_bitmask_order(entries) - 2) << 12)); 704 705 /* Now enable the unit */ 706 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1); 707 708 out: 709 return rc; 710 711 out_irq: 712 dma_free_coherent(priv->dev, 713 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 714 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 715 716 out_dma: 717 for (i = 0; i < priv->msg_tx_ring.size; i++) 718 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 719 priv->msg_tx_ring.virt_buffer[i], 720 priv->msg_tx_ring.phys_buffer[i]); 721 722 return rc; 723 } 724 725 /** 726 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox 727 * @mport: Master port implementing the outbound message unit 728 * @mbox: Mailbox to close 729 * 730 * Disables the outbound message unit, free all buffers, and 731 * frees the outbound message interrupt. 732 */ 733 static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) 734 { 735 struct rio_priv *priv = mport->priv; 736 /* Disable inbound message unit */ 737 out_be32(&priv->msg_regs->omr, 0); 738 739 /* Free ring */ 740 dma_free_coherent(priv->dev, 741 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 742 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 743 744 /* Free interrupt */ 745 free_irq(IRQ_RIO_TX(mport), (void *)mport); 746 } 747 748 /** 749 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler 750 * @irq: Linux interrupt number 751 * @dev_instance: Pointer to interrupt-specific data 752 * 753 * Handles inbound message interrupts. Executes a registered inbound 754 * mailbox event handler and acks the interrupt occurrence. 755 */ 756 static irqreturn_t 757 fsl_rio_rx_handler(int irq, void *dev_instance) 758 { 759 int isr; 760 struct rio_mport *port = (struct rio_mport *)dev_instance; 761 struct rio_priv *priv = port->priv; 762 763 isr = in_be32(&priv->msg_regs->isr); 764 765 if (isr & RIO_MSG_ISR_TE) { 766 pr_info("RIO: inbound message reception error\n"); 767 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE); 768 goto out; 769 } 770 771 /* XXX Need to check/dispatch until queue empty */ 772 if (isr & RIO_MSG_ISR_DIQI) { 773 /* 774 * We implement *only* mailbox 0, but can receive messages 775 * for any mailbox/letter to that mailbox destination. So, 776 * make the callback with an unknown/invalid mailbox number 777 * argument. 778 */ 779 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1); 780 781 /* Ack the queueing interrupt */ 782 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI); 783 } 784 785 out: 786 return IRQ_HANDLED; 787 } 788 789 /** 790 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox 791 * @mport: Master port implementing the inbound message unit 792 * @dev_id: Device specific pointer to pass on event 793 * @mbox: Mailbox to open 794 * @entries: Number of entries in the inbound mailbox ring 795 * 796 * Initializes buffer ring, request the inbound message interrupt, 797 * and enables the inbound message unit. Returns %0 on success 798 * and %-EINVAL or %-ENOMEM on failure. 799 */ 800 static int 801 fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 802 { 803 int i, rc = 0; 804 struct rio_priv *priv = mport->priv; 805 806 if ((entries < RIO_MIN_RX_RING_SIZE) || 807 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { 808 rc = -EINVAL; 809 goto out; 810 } 811 812 /* Initialize client buffer ring */ 813 priv->msg_rx_ring.dev_id = dev_id; 814 priv->msg_rx_ring.size = entries; 815 priv->msg_rx_ring.rx_slot = 0; 816 for (i = 0; i < priv->msg_rx_ring.size; i++) 817 priv->msg_rx_ring.virt_buffer[i] = NULL; 818 819 /* Initialize inbound message ring */ 820 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, 821 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 822 &priv->msg_rx_ring.phys, GFP_KERNEL); 823 if (!priv->msg_rx_ring.virt) { 824 rc = -ENOMEM; 825 goto out; 826 } 827 828 /* Point dequeue/enqueue pointers at first entry in ring */ 829 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys); 830 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys); 831 832 /* Clear interrupt status */ 833 out_be32(&priv->msg_regs->isr, 0x00000091); 834 835 /* Hook up inbound message handler */ 836 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 837 "msg_rx", (void *)mport); 838 if (rc < 0) { 839 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 840 priv->msg_tx_ring.virt_buffer[i], 841 priv->msg_tx_ring.phys_buffer[i]); 842 goto out; 843 } 844 845 /* 846 * Configure inbound message unit: 847 * Snooping 848 * 4KB max message size 849 * Unmask all interrupt sources 850 * Disable 851 */ 852 out_be32(&priv->msg_regs->imr, 0x001b0060); 853 854 /* Set number of queue entries */ 855 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); 856 857 /* Now enable the unit */ 858 setbits32(&priv->msg_regs->imr, 0x1); 859 860 out: 861 return rc; 862 } 863 864 /** 865 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox 866 * @mport: Master port implementing the inbound message unit 867 * @mbox: Mailbox to close 868 * 869 * Disables the inbound message unit, free all buffers, and 870 * frees the inbound message interrupt. 871 */ 872 static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) 873 { 874 struct rio_priv *priv = mport->priv; 875 /* Disable inbound message unit */ 876 out_be32(&priv->msg_regs->imr, 0); 877 878 /* Free ring */ 879 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 880 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys); 881 882 /* Free interrupt */ 883 free_irq(IRQ_RIO_RX(mport), (void *)mport); 884 } 885 886 /** 887 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 888 * @mport: Master port implementing the inbound message unit 889 * @mbox: Inbound mailbox number 890 * @buf: Buffer to add to inbound queue 891 * 892 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 893 * %0 on success or %-EINVAL on failure. 894 */ 895 static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 896 { 897 int rc = 0; 898 struct rio_priv *priv = mport->priv; 899 900 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 901 priv->msg_rx_ring.rx_slot); 902 903 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { 904 printk(KERN_ERR 905 "RIO: error adding inbound buffer %d, buffer exists\n", 906 priv->msg_rx_ring.rx_slot); 907 rc = -EINVAL; 908 goto out; 909 } 910 911 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf; 912 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size) 913 priv->msg_rx_ring.rx_slot = 0; 914 915 out: 916 return rc; 917 } 918 919 /** 920 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit 921 * @mport: Master port implementing the inbound message unit 922 * @mbox: Inbound mailbox number 923 * 924 * Gets the next available inbound message from the inbound message queue. 925 * A pointer to the message is returned on success or NULL on failure. 926 */ 927 static void *fsl_get_inb_message(struct rio_mport *mport, int mbox) 928 { 929 struct rio_priv *priv = mport->priv; 930 u32 phys_buf, virt_buf; 931 void *buf = NULL; 932 int buf_idx; 933 934 phys_buf = in_be32(&priv->msg_regs->ifqdpar); 935 936 /* If no more messages, then bail out */ 937 if (phys_buf == in_be32(&priv->msg_regs->ifqepar)) 938 goto out2; 939 940 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf 941 - priv->msg_rx_ring.phys); 942 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 943 buf = priv->msg_rx_ring.virt_buffer[buf_idx]; 944 945 if (!buf) { 946 printk(KERN_ERR 947 "RIO: inbound message copy failed, no buffers\n"); 948 goto out1; 949 } 950 951 /* Copy max message size, caller is expected to allocate that big */ 952 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); 953 954 /* Clear the available buffer */ 955 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL; 956 957 out1: 958 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI); 959 960 out2: 961 return buf; 962 } 963 964 /** 965 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 966 * @irq: Linux interrupt number 967 * @dev_instance: Pointer to interrupt-specific data 968 * 969 * Handles doorbell interrupts. Parses a list of registered 970 * doorbell event handlers and executes a matching event handler. 971 */ 972 static irqreturn_t 973 fsl_rio_dbell_handler(int irq, void *dev_instance) 974 { 975 int dsr; 976 struct rio_mport *port = (struct rio_mport *)dev_instance; 977 struct rio_priv *priv = port->priv; 978 979 dsr = in_be32(&priv->msg_regs->dsr); 980 981 if (dsr & DOORBELL_DSR_TE) { 982 pr_info("RIO: doorbell reception error\n"); 983 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE); 984 goto out; 985 } 986 987 if (dsr & DOORBELL_DSR_QFI) { 988 pr_info("RIO: doorbell queue full\n"); 989 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI); 990 } 991 992 /* XXX Need to check/dispatch until queue empty */ 993 if (dsr & DOORBELL_DSR_DIQI) { 994 u32 dmsg = 995 (u32) priv->dbell_ring.virt + 996 (in_be32(&priv->msg_regs->dqdpar) & 0xfff); 997 struct rio_dbell *dbell; 998 int found = 0; 999 1000 pr_debug 1001 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", 1002 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 1003 1004 list_for_each_entry(dbell, &port->dbells, node) { 1005 if ((dbell->res->start <= DBELL_INF(dmsg)) && 1006 (dbell->res->end >= DBELL_INF(dmsg))) { 1007 found = 1; 1008 break; 1009 } 1010 } 1011 if (found) { 1012 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), 1013 DBELL_INF(dmsg)); 1014 } else { 1015 pr_debug 1016 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", 1017 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 1018 } 1019 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI); 1020 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI); 1021 } 1022 1023 out: 1024 return IRQ_HANDLED; 1025 } 1026 1027 /** 1028 * fsl_rio_doorbell_init - MPC85xx doorbell interface init 1029 * @mport: Master port implementing the inbound doorbell unit 1030 * 1031 * Initializes doorbell unit hardware and inbound DMA buffer 1032 * ring. Called from fsl_rio_setup(). Returns %0 on success 1033 * or %-ENOMEM on failure. 1034 */ 1035 static int fsl_rio_doorbell_init(struct rio_mport *mport) 1036 { 1037 struct rio_priv *priv = mport->priv; 1038 int rc = 0; 1039 1040 /* Map outbound doorbell window immediately after maintenance window */ 1041 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, 1042 RIO_DBELL_WIN_SIZE); 1043 if (!priv->dbell_win) { 1044 printk(KERN_ERR 1045 "RIO: unable to map outbound doorbell window\n"); 1046 rc = -ENOMEM; 1047 goto out; 1048 } 1049 1050 /* Initialize inbound doorbells */ 1051 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 * 1052 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL); 1053 if (!priv->dbell_ring.virt) { 1054 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); 1055 rc = -ENOMEM; 1056 iounmap(priv->dbell_win); 1057 goto out; 1058 } 1059 1060 /* Point dequeue/enqueue pointers at first entry in ring */ 1061 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys); 1062 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys); 1063 1064 /* Clear interrupt status */ 1065 out_be32(&priv->msg_regs->dsr, 0x00000091); 1066 1067 /* Hook up doorbell handler */ 1068 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, 1069 "dbell_rx", (void *)mport); 1070 if (rc < 0) { 1071 iounmap(priv->dbell_win); 1072 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE, 1073 priv->dbell_ring.virt, priv->dbell_ring.phys); 1074 printk(KERN_ERR 1075 "MPC85xx RIO: unable to request inbound doorbell irq"); 1076 goto out; 1077 } 1078 1079 /* Configure doorbells for snooping, 512 entries, and enable */ 1080 out_be32(&priv->msg_regs->dmr, 0x00108161); 1081 1082 out: 1083 return rc; 1084 } 1085 1086 static void port_error_handler(struct rio_mport *port, int offset) 1087 { 1088 /*XXX: Error recovery is not implemented, we just clear errors */ 1089 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 1090 1091 if (offset == 0) { 1092 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0); 1093 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR); 1094 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR); 1095 } else { 1096 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0); 1097 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR); 1098 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); 1099 } 1100 } 1101 1102 static void msg_unit_error_handler(struct rio_mport *port) 1103 { 1104 struct rio_priv *priv = port->priv; 1105 1106 /*XXX: Error recovery is not implemented, we just clear errors */ 1107 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 1108 1109 out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR); 1110 out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR); 1111 out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR); 1112 out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR); 1113 1114 out_be32(&priv->msg_regs->odsr, ODSR_CLEAR); 1115 out_be32(&priv->msg_regs->dsr, IDSR_CLEAR); 1116 1117 out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR); 1118 } 1119 1120 /** 1121 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler 1122 * @irq: Linux interrupt number 1123 * @dev_instance: Pointer to interrupt-specific data 1124 * 1125 * Handles port write interrupts. Parses a list of registered 1126 * port write event handlers and executes a matching event handler. 1127 */ 1128 static irqreturn_t 1129 fsl_rio_port_write_handler(int irq, void *dev_instance) 1130 { 1131 u32 ipwmr, ipwsr; 1132 struct rio_mport *port = (struct rio_mport *)dev_instance; 1133 struct rio_priv *priv = port->priv; 1134 u32 epwisr, tmp; 1135 1136 epwisr = in_be32(priv->regs_win + RIO_EPWISR); 1137 if (!(epwisr & RIO_EPWISR_PW)) 1138 goto pw_done; 1139 1140 ipwmr = in_be32(&priv->msg_regs->pwmr); 1141 ipwsr = in_be32(&priv->msg_regs->pwsr); 1142 1143 #ifdef DEBUG_PW 1144 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); 1145 if (ipwsr & RIO_IPWSR_QF) 1146 pr_debug(" QF"); 1147 if (ipwsr & RIO_IPWSR_TE) 1148 pr_debug(" TE"); 1149 if (ipwsr & RIO_IPWSR_QFI) 1150 pr_debug(" QFI"); 1151 if (ipwsr & RIO_IPWSR_PWD) 1152 pr_debug(" PWD"); 1153 if (ipwsr & RIO_IPWSR_PWB) 1154 pr_debug(" PWB"); 1155 pr_debug(" )\n"); 1156 #endif 1157 /* Schedule deferred processing if PW was received */ 1158 if (ipwsr & RIO_IPWSR_QFI) { 1159 /* Save PW message (if there is room in FIFO), 1160 * otherwise discard it. 1161 */ 1162 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) { 1163 priv->port_write_msg.msg_count++; 1164 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt, 1165 RIO_PW_MSG_SIZE); 1166 } else { 1167 priv->port_write_msg.discard_count++; 1168 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", 1169 priv->port_write_msg.discard_count); 1170 } 1171 /* Clear interrupt and issue Clear Queue command. This allows 1172 * another port-write to be received. 1173 */ 1174 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI); 1175 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ); 1176 1177 schedule_work(&priv->pw_work); 1178 } 1179 1180 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { 1181 priv->port_write_msg.err_count++; 1182 pr_debug("RIO: Port-Write Transaction Err (%d)\n", 1183 priv->port_write_msg.err_count); 1184 /* Clear Transaction Error: port-write controller should be 1185 * disabled when clearing this error 1186 */ 1187 out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); 1188 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE); 1189 out_be32(&priv->msg_regs->pwmr, ipwmr); 1190 } 1191 1192 if (ipwsr & RIO_IPWSR_PWD) { 1193 priv->port_write_msg.discard_count++; 1194 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", 1195 priv->port_write_msg.discard_count); 1196 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD); 1197 } 1198 1199 pw_done: 1200 if (epwisr & RIO_EPWISR_PINT1) { 1201 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 1202 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 1203 port_error_handler(port, 0); 1204 } 1205 1206 if (epwisr & RIO_EPWISR_PINT2) { 1207 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 1208 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 1209 port_error_handler(port, 1); 1210 } 1211 1212 if (epwisr & RIO_EPWISR_MU) { 1213 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 1214 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 1215 msg_unit_error_handler(port); 1216 } 1217 1218 return IRQ_HANDLED; 1219 } 1220 1221 static void fsl_pw_dpc(struct work_struct *work) 1222 { 1223 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work); 1224 unsigned long flags; 1225 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; 1226 1227 /* 1228 * Process port-write messages 1229 */ 1230 spin_lock_irqsave(&priv->pw_fifo_lock, flags); 1231 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer, 1232 RIO_PW_MSG_SIZE)) { 1233 /* Process one message */ 1234 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 1235 #ifdef DEBUG_PW 1236 { 1237 u32 i; 1238 pr_debug("%s : Port-Write Message:", __func__); 1239 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { 1240 if ((i%4) == 0) 1241 pr_debug("\n0x%02x: 0x%08x", i*4, 1242 msg_buffer[i]); 1243 else 1244 pr_debug(" 0x%08x", msg_buffer[i]); 1245 } 1246 pr_debug("\n"); 1247 } 1248 #endif 1249 /* Pass the port-write message to RIO core for processing */ 1250 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); 1251 spin_lock_irqsave(&priv->pw_fifo_lock, flags); 1252 } 1253 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 1254 } 1255 1256 /** 1257 * fsl_rio_pw_enable - enable/disable port-write interface init 1258 * @mport: Master port implementing the port write unit 1259 * @enable: 1=enable; 0=disable port-write message handling 1260 */ 1261 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable) 1262 { 1263 struct rio_priv *priv = mport->priv; 1264 u32 rval; 1265 1266 rval = in_be32(&priv->msg_regs->pwmr); 1267 1268 if (enable) 1269 rval |= RIO_IPWMR_PWE; 1270 else 1271 rval &= ~RIO_IPWMR_PWE; 1272 1273 out_be32(&priv->msg_regs->pwmr, rval); 1274 1275 return 0; 1276 } 1277 1278 /** 1279 * fsl_rio_port_write_init - MPC85xx port write interface init 1280 * @mport: Master port implementing the port write unit 1281 * 1282 * Initializes port write unit hardware and DMA buffer 1283 * ring. Called from fsl_rio_setup(). Returns %0 on success 1284 * or %-ENOMEM on failure. 1285 */ 1286 static int fsl_rio_port_write_init(struct rio_mport *mport) 1287 { 1288 struct rio_priv *priv = mport->priv; 1289 int rc = 0; 1290 1291 /* Following configurations require a disabled port write controller */ 1292 out_be32(&priv->msg_regs->pwmr, 1293 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE); 1294 1295 /* Initialize port write */ 1296 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev, 1297 RIO_PW_MSG_SIZE, 1298 &priv->port_write_msg.phys, GFP_KERNEL); 1299 if (!priv->port_write_msg.virt) { 1300 pr_err("RIO: unable allocate port write queue\n"); 1301 return -ENOMEM; 1302 } 1303 1304 priv->port_write_msg.err_count = 0; 1305 priv->port_write_msg.discard_count = 0; 1306 1307 /* Point dequeue/enqueue pointers at first entry */ 1308 out_be32(&priv->msg_regs->epwqbar, 0); 1309 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys); 1310 1311 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", 1312 in_be32(&priv->msg_regs->epwqbar), 1313 in_be32(&priv->msg_regs->pwqbar)); 1314 1315 /* Clear interrupt status IPWSR */ 1316 out_be32(&priv->msg_regs->pwsr, 1317 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); 1318 1319 /* Configure port write contoller for snooping enable all reporting, 1320 clear queue full */ 1321 out_be32(&priv->msg_regs->pwmr, 1322 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); 1323 1324 1325 /* Hook up port-write handler */ 1326 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 1327 IRQF_SHARED, "port-write", (void *)mport); 1328 if (rc < 0) { 1329 pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); 1330 goto err_out; 1331 } 1332 /* Enable Error Interrupt */ 1333 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL); 1334 1335 INIT_WORK(&priv->pw_work, fsl_pw_dpc); 1336 spin_lock_init(&priv->pw_fifo_lock); 1337 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { 1338 pr_err("FIFO allocation failed\n"); 1339 rc = -ENOMEM; 1340 goto err_out_irq; 1341 } 1342 1343 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", 1344 in_be32(&priv->msg_regs->pwmr), 1345 in_be32(&priv->msg_regs->pwsr)); 1346 1347 return rc; 1348 1349 err_out_irq: 1350 free_irq(IRQ_RIO_PW(mport), (void *)mport); 1351 err_out: 1352 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE, 1353 priv->port_write_msg.virt, 1354 priv->port_write_msg.phys); 1355 return rc; 1356 } 1357 1358 static inline void fsl_rio_info(struct device *dev, u32 ccsr) 1359 { 1360 const char *str; 1361 if (ccsr & 1) { 1362 /* Serial phy */ 1363 switch (ccsr >> 30) { 1364 case 0: 1365 str = "1"; 1366 break; 1367 case 1: 1368 str = "4"; 1369 break; 1370 default: 1371 str = "Unknown"; 1372 break; 1373 } 1374 dev_info(dev, "Hardware port width: %s\n", str); 1375 1376 switch ((ccsr >> 27) & 7) { 1377 case 0: 1378 str = "Single-lane 0"; 1379 break; 1380 case 1: 1381 str = "Single-lane 2"; 1382 break; 1383 case 2: 1384 str = "Four-lane"; 1385 break; 1386 default: 1387 str = "Unknown"; 1388 break; 1389 } 1390 dev_info(dev, "Training connection status: %s\n", str); 1391 } else { 1392 /* Parallel phy */ 1393 if (!(ccsr & 0x80000000)) 1394 dev_info(dev, "Output port operating in 8-bit mode\n"); 1395 if (!(ccsr & 0x08000000)) 1396 dev_info(dev, "Input port operating in 8-bit mode\n"); 1397 } 1398 } 1399 1400 /** 1401 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface 1402 * @dev: platform_device pointer 1403 * 1404 * Initializes MPC85xx RapidIO hardware interface, configures 1405 * master port with system-specific info, and registers the 1406 * master port with the RapidIO subsystem. 1407 */ 1408 int fsl_rio_setup(struct platform_device *dev) 1409 { 1410 struct rio_ops *ops; 1411 struct rio_mport *port; 1412 struct rio_priv *priv; 1413 int rc = 0; 1414 const u32 *dt_range, *cell; 1415 struct resource regs; 1416 int rlen; 1417 u32 ccsr; 1418 u64 law_start, law_size; 1419 int paw, aw, sw; 1420 1421 if (!dev->dev.of_node) { 1422 dev_err(&dev->dev, "Device OF-Node is NULL"); 1423 return -EFAULT; 1424 } 1425 1426 rc = of_address_to_resource(dev->dev.of_node, 0, ®s); 1427 if (rc) { 1428 dev_err(&dev->dev, "Can't get %s property 'reg'\n", 1429 dev->dev.of_node->full_name); 1430 return -EFAULT; 1431 } 1432 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); 1433 dev_info(&dev->dev, "Regs: %pR\n", ®s); 1434 1435 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); 1436 if (!dt_range) { 1437 dev_err(&dev->dev, "Can't get %s property 'ranges'\n", 1438 dev->dev.of_node->full_name); 1439 return -EFAULT; 1440 } 1441 1442 /* Get node address wide */ 1443 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL); 1444 if (cell) 1445 aw = *cell; 1446 else 1447 aw = of_n_addr_cells(dev->dev.of_node); 1448 /* Get node size wide */ 1449 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL); 1450 if (cell) 1451 sw = *cell; 1452 else 1453 sw = of_n_size_cells(dev->dev.of_node); 1454 /* Get parent address wide wide */ 1455 paw = of_n_addr_cells(dev->dev.of_node); 1456 1457 law_start = of_read_number(dt_range + aw, paw); 1458 law_size = of_read_number(dt_range + aw + paw, sw); 1459 1460 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n", 1461 law_start, law_size); 1462 1463 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); 1464 if (!ops) { 1465 rc = -ENOMEM; 1466 goto err_ops; 1467 } 1468 ops->lcread = fsl_local_config_read; 1469 ops->lcwrite = fsl_local_config_write; 1470 ops->cread = fsl_rio_config_read; 1471 ops->cwrite = fsl_rio_config_write; 1472 ops->dsend = fsl_rio_doorbell_send; 1473 ops->pwenable = fsl_rio_pw_enable; 1474 ops->open_outb_mbox = fsl_open_outb_mbox; 1475 ops->open_inb_mbox = fsl_open_inb_mbox; 1476 ops->close_outb_mbox = fsl_close_outb_mbox; 1477 ops->close_inb_mbox = fsl_close_inb_mbox; 1478 ops->add_outb_message = fsl_add_outb_message; 1479 ops->add_inb_buffer = fsl_add_inb_buffer; 1480 ops->get_inb_message = fsl_get_inb_message; 1481 1482 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 1483 if (!port) { 1484 rc = -ENOMEM; 1485 goto err_port; 1486 } 1487 port->index = 0; 1488 1489 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); 1490 if (!priv) { 1491 printk(KERN_ERR "Can't alloc memory for 'priv'\n"); 1492 rc = -ENOMEM; 1493 goto err_priv; 1494 } 1495 1496 INIT_LIST_HEAD(&port->dbells); 1497 port->iores.start = law_start; 1498 port->iores.end = law_start + law_size - 1; 1499 port->iores.flags = IORESOURCE_MEM; 1500 port->iores.name = "rio_io_win"; 1501 1502 if (request_resource(&iomem_resource, &port->iores) < 0) { 1503 dev_err(&dev->dev, "RIO: Error requesting master port region" 1504 " 0x%016llx-0x%016llx\n", 1505 (u64)port->iores.start, (u64)port->iores.end); 1506 rc = -ENOMEM; 1507 goto err_res; 1508 } 1509 1510 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 1511 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 1512 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); 1513 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); 1514 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n", 1515 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq); 1516 1517 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 1518 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 1519 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 1520 strcpy(port->name, "RIO0 mport"); 1521 1522 priv->dev = &dev->dev; 1523 1524 port->ops = ops; 1525 port->priv = priv; 1526 port->phys_efptr = 0x100; 1527 1528 priv->regs_win = ioremap(regs.start, resource_size(®s)); 1529 rio_regs_win = priv->regs_win; 1530 1531 /* Probe the master port phy type */ 1532 ccsr = in_be32(priv->regs_win + RIO_CCSR); 1533 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; 1534 dev_info(&dev->dev, "RapidIO PHY type: %s\n", 1535 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" : 1536 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" : 1537 "unknown")); 1538 /* Checking the port training status */ 1539 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 1540 dev_err(&dev->dev, "Port is not ready. " 1541 "Try to restart connection...\n"); 1542 switch (port->phy_type) { 1543 case RIO_PHY_SERIAL: 1544 /* Disable ports */ 1545 out_be32(priv->regs_win + RIO_CCSR, 0); 1546 /* Set 1x lane */ 1547 setbits32(priv->regs_win + RIO_CCSR, 0x02000000); 1548 /* Enable ports */ 1549 setbits32(priv->regs_win + RIO_CCSR, 0x00600000); 1550 break; 1551 case RIO_PHY_PARALLEL: 1552 /* Disable ports */ 1553 out_be32(priv->regs_win + RIO_CCSR, 0x22000000); 1554 /* Enable ports */ 1555 out_be32(priv->regs_win + RIO_CCSR, 0x44000000); 1556 break; 1557 } 1558 msleep(100); 1559 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 1560 dev_err(&dev->dev, "Port restart failed.\n"); 1561 rc = -ENOLINK; 1562 goto err; 1563 } 1564 dev_info(&dev->dev, "Port restart success!\n"); 1565 } 1566 fsl_rio_info(&dev->dev, ccsr); 1567 1568 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 1569 & RIO_PEF_CTLS) >> 4; 1570 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 1571 port->sys_size ? 65536 : 256); 1572 1573 if (rio_register_mport(port)) 1574 goto err; 1575 1576 if (port->host_deviceid >= 0) 1577 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | 1578 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED); 1579 else 1580 out_be32(priv->regs_win + RIO_GCCSR, 0x00000000); 1581 1582 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 1583 + RIO_ATMU_REGS_OFFSET); 1584 priv->maint_atmu_regs = priv->atmu_regs + 1; 1585 priv->dbell_atmu_regs = priv->atmu_regs + 2; 1586 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + 1587 ((port->phy_type == RIO_PHY_SERIAL) ? 1588 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); 1589 1590 /* Set to receive any dist ID for serial RapidIO controller. */ 1591 if (port->phy_type == RIO_PHY_SERIAL) 1592 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); 1593 1594 /* Configure maintenance transaction window */ 1595 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12); 1596 out_be32(&priv->maint_atmu_regs->rowar, 1597 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); 1598 1599 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); 1600 1601 /* Configure outbound doorbell window */ 1602 out_be32(&priv->dbell_atmu_regs->rowbar, 1603 (law_start + RIO_MAINT_WIN_SIZE) >> 12); 1604 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ 1605 fsl_rio_doorbell_init(port); 1606 fsl_rio_port_write_init(port); 1607 1608 return 0; 1609 err: 1610 iounmap(priv->regs_win); 1611 release_resource(&port->iores); 1612 err_res: 1613 kfree(priv); 1614 err_priv: 1615 kfree(port); 1616 err_port: 1617 kfree(ops); 1618 err_ops: 1619 return rc; 1620 } 1621 1622 /* The probe function for RapidIO peer-to-peer network. 1623 */ 1624 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev) 1625 { 1626 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", 1627 dev->dev.of_node->full_name); 1628 1629 return fsl_rio_setup(dev); 1630 }; 1631 1632 static const struct of_device_id fsl_of_rio_rpn_ids[] = { 1633 { 1634 .compatible = "fsl,rapidio-delta", 1635 }, 1636 {}, 1637 }; 1638 1639 static struct platform_driver fsl_of_rio_rpn_driver = { 1640 .driver = { 1641 .name = "fsl-of-rio", 1642 .owner = THIS_MODULE, 1643 .of_match_table = fsl_of_rio_rpn_ids, 1644 }, 1645 .probe = fsl_of_rio_rpn_probe, 1646 }; 1647 1648 static __init int fsl_of_rio_rpn_init(void) 1649 { 1650 return platform_driver_register(&fsl_of_rio_rpn_driver); 1651 } 1652 1653 subsys_initcall(fsl_of_rio_rpn_init); 1654