1 /* 2 * Freescale MPC85xx/MPC86xx RapidIO support 3 * 4 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc. 5 * Zhang Wei <wei.zhang@freescale.com> 6 * 7 * Copyright 2005 MontaVista Software, Inc. 8 * Matt Porter <mporter@kernel.crashing.org> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/types.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/interrupt.h> 21 #include <linux/device.h> 22 #include <linux/rio.h> 23 #include <linux/rio_drv.h> 24 #include <linux/of_platform.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 28 #include <asm/io.h> 29 30 /* RapidIO definition irq, which read from OF-tree */ 31 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) 32 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) 33 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) 34 35 #define RIO_ATMU_REGS_OFFSET 0x10c00 36 #define RIO_P_MSG_REGS_OFFSET 0x11000 37 #define RIO_S_MSG_REGS_OFFSET 0x13000 38 #define RIO_ESCSR 0x158 39 #define RIO_CCSR 0x15c 40 #define RIO_ISR_AACR 0x10120 41 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 42 #define RIO_MAINT_WIN_SIZE 0x400000 43 #define RIO_DBELL_WIN_SIZE 0x1000 44 45 #define RIO_MSG_OMR_MUI 0x00000002 46 #define RIO_MSG_OSR_TE 0x00000080 47 #define RIO_MSG_OSR_QOI 0x00000020 48 #define RIO_MSG_OSR_QFI 0x00000010 49 #define RIO_MSG_OSR_MUB 0x00000004 50 #define RIO_MSG_OSR_EOMI 0x00000002 51 #define RIO_MSG_OSR_QEI 0x00000001 52 53 #define RIO_MSG_IMR_MI 0x00000002 54 #define RIO_MSG_ISR_TE 0x00000080 55 #define RIO_MSG_ISR_QFI 0x00000010 56 #define RIO_MSG_ISR_DIQI 0x00000001 57 58 #define RIO_MSG_DESC_SIZE 32 59 #define RIO_MSG_BUFFER_SIZE 4096 60 #define RIO_MIN_TX_RING_SIZE 2 61 #define RIO_MAX_TX_RING_SIZE 2048 62 #define RIO_MIN_RX_RING_SIZE 2 63 #define RIO_MAX_RX_RING_SIZE 2048 64 65 #define DOORBELL_DMR_DI 0x00000002 66 #define DOORBELL_DSR_TE 0x00000080 67 #define DOORBELL_DSR_QFI 0x00000010 68 #define DOORBELL_DSR_DIQI 0x00000001 69 #define DOORBELL_TID_OFFSET 0x02 70 #define DOORBELL_SID_OFFSET 0x04 71 #define DOORBELL_INFO_OFFSET 0x06 72 73 #define DOORBELL_MESSAGE_SIZE 0x08 74 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) 75 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) 76 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) 77 78 struct rio_atmu_regs { 79 u32 rowtar; 80 u32 rowtear; 81 u32 rowbar; 82 u32 pad2; 83 u32 rowar; 84 u32 pad3[3]; 85 }; 86 87 struct rio_msg_regs { 88 u32 omr; 89 u32 osr; 90 u32 pad1; 91 u32 odqdpar; 92 u32 pad2; 93 u32 osar; 94 u32 odpr; 95 u32 odatr; 96 u32 odcr; 97 u32 pad3; 98 u32 odqepar; 99 u32 pad4[13]; 100 u32 imr; 101 u32 isr; 102 u32 pad5; 103 u32 ifqdpar; 104 u32 pad6; 105 u32 ifqepar; 106 u32 pad7[226]; 107 u32 odmr; 108 u32 odsr; 109 u32 res0[4]; 110 u32 oddpr; 111 u32 oddatr; 112 u32 res1[3]; 113 u32 odretcr; 114 u32 res2[12]; 115 u32 dmr; 116 u32 dsr; 117 u32 pad8; 118 u32 dqdpar; 119 u32 pad9; 120 u32 dqepar; 121 u32 pad10[26]; 122 u32 pwmr; 123 u32 pwsr; 124 u32 pad11; 125 u32 pwqbar; 126 }; 127 128 struct rio_tx_desc { 129 u32 res1; 130 u32 saddr; 131 u32 dport; 132 u32 dattr; 133 u32 res2; 134 u32 res3; 135 u32 dwcnt; 136 u32 res4; 137 }; 138 139 struct rio_dbell_ring { 140 void *virt; 141 dma_addr_t phys; 142 }; 143 144 struct rio_msg_tx_ring { 145 void *virt; 146 dma_addr_t phys; 147 void *virt_buffer[RIO_MAX_TX_RING_SIZE]; 148 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; 149 int tx_slot; 150 int size; 151 void *dev_id; 152 }; 153 154 struct rio_msg_rx_ring { 155 void *virt; 156 dma_addr_t phys; 157 void *virt_buffer[RIO_MAX_RX_RING_SIZE]; 158 int rx_slot; 159 int size; 160 void *dev_id; 161 }; 162 163 struct rio_priv { 164 struct device *dev; 165 void __iomem *regs_win; 166 struct rio_atmu_regs __iomem *atmu_regs; 167 struct rio_atmu_regs __iomem *maint_atmu_regs; 168 struct rio_atmu_regs __iomem *dbell_atmu_regs; 169 void __iomem *dbell_win; 170 void __iomem *maint_win; 171 struct rio_msg_regs __iomem *msg_regs; 172 struct rio_dbell_ring dbell_ring; 173 struct rio_msg_tx_ring msg_tx_ring; 174 struct rio_msg_rx_ring msg_rx_ring; 175 int bellirq; 176 int txirq; 177 int rxirq; 178 }; 179 180 /** 181 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message 182 * @mport: RapidIO master port info 183 * @index: ID of RapidIO interface 184 * @destid: Destination ID of target device 185 * @data: 16-bit info field of RapidIO doorbell message 186 * 187 * Sends a MPC85xx doorbell message. Returns %0 on success or 188 * %-EINVAL on failure. 189 */ 190 static int fsl_rio_doorbell_send(struct rio_mport *mport, 191 int index, u16 destid, u16 data) 192 { 193 struct rio_priv *priv = mport->priv; 194 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", 195 index, destid, data); 196 switch (mport->phy_type) { 197 case RIO_PHY_PARALLEL: 198 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22); 199 out_be16(priv->dbell_win, data); 200 break; 201 case RIO_PHY_SERIAL: 202 /* In the serial version silicons, such as MPC8548, MPC8641, 203 * below operations is must be. 204 */ 205 out_be32(&priv->msg_regs->odmr, 0x00000000); 206 out_be32(&priv->msg_regs->odretcr, 0x00000004); 207 out_be32(&priv->msg_regs->oddpr, destid << 16); 208 out_be32(&priv->msg_regs->oddatr, data); 209 out_be32(&priv->msg_regs->odmr, 0x00000001); 210 break; 211 } 212 213 return 0; 214 } 215 216 /** 217 * fsl_local_config_read - Generate a MPC85xx local config space read 218 * @mport: RapidIO master port info 219 * @index: ID of RapdiIO interface 220 * @offset: Offset into configuration space 221 * @len: Length (in bytes) of the maintenance transaction 222 * @data: Value to be read into 223 * 224 * Generates a MPC85xx local configuration space read. Returns %0 on 225 * success or %-EINVAL on failure. 226 */ 227 static int fsl_local_config_read(struct rio_mport *mport, 228 int index, u32 offset, int len, u32 *data) 229 { 230 struct rio_priv *priv = mport->priv; 231 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, 232 offset); 233 *data = in_be32(priv->regs_win + offset); 234 235 return 0; 236 } 237 238 /** 239 * fsl_local_config_write - Generate a MPC85xx local config space write 240 * @mport: RapidIO master port info 241 * @index: ID of RapdiIO interface 242 * @offset: Offset into configuration space 243 * @len: Length (in bytes) of the maintenance transaction 244 * @data: Value to be written 245 * 246 * Generates a MPC85xx local configuration space write. Returns %0 on 247 * success or %-EINVAL on failure. 248 */ 249 static int fsl_local_config_write(struct rio_mport *mport, 250 int index, u32 offset, int len, u32 data) 251 { 252 struct rio_priv *priv = mport->priv; 253 pr_debug 254 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 255 index, offset, data); 256 out_be32(priv->regs_win + offset, data); 257 258 return 0; 259 } 260 261 /** 262 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction 263 * @mport: RapidIO master port info 264 * @index: ID of RapdiIO interface 265 * @destid: Destination ID of transaction 266 * @hopcount: Number of hops to target device 267 * @offset: Offset into configuration space 268 * @len: Length (in bytes) of the maintenance transaction 269 * @val: Location to be read into 270 * 271 * Generates a MPC85xx read maintenance transaction. Returns %0 on 272 * success or %-EINVAL on failure. 273 */ 274 static int 275 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, 276 u8 hopcount, u32 offset, int len, u32 *val) 277 { 278 struct rio_priv *priv = mport->priv; 279 u8 *data; 280 281 pr_debug 282 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", 283 index, destid, hopcount, offset, len); 284 out_be32(&priv->maint_atmu_regs->rowtar, 285 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); 286 287 data = (u8 *) priv->maint_win + offset; 288 switch (len) { 289 case 1: 290 *val = in_8((u8 *) data); 291 break; 292 case 2: 293 *val = in_be16((u16 *) data); 294 break; 295 default: 296 *val = in_be32((u32 *) data); 297 break; 298 } 299 300 return 0; 301 } 302 303 /** 304 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction 305 * @mport: RapidIO master port info 306 * @index: ID of RapdiIO interface 307 * @destid: Destination ID of transaction 308 * @hopcount: Number of hops to target device 309 * @offset: Offset into configuration space 310 * @len: Length (in bytes) of the maintenance transaction 311 * @val: Value to be written 312 * 313 * Generates an MPC85xx write maintenance transaction. Returns %0 on 314 * success or %-EINVAL on failure. 315 */ 316 static int 317 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, 318 u8 hopcount, u32 offset, int len, u32 val) 319 { 320 struct rio_priv *priv = mport->priv; 321 u8 *data; 322 pr_debug 323 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 324 index, destid, hopcount, offset, len, val); 325 out_be32(&priv->maint_atmu_regs->rowtar, 326 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); 327 328 data = (u8 *) priv->maint_win + offset; 329 switch (len) { 330 case 1: 331 out_8((u8 *) data, val); 332 break; 333 case 2: 334 out_be16((u16 *) data, val); 335 break; 336 default: 337 out_be32((u32 *) data, val); 338 break; 339 } 340 341 return 0; 342 } 343 344 /** 345 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue 346 * @mport: Master port with outbound message queue 347 * @rdev: Target of outbound message 348 * @mbox: Outbound mailbox 349 * @buffer: Message to add to outbound queue 350 * @len: Length of message 351 * 352 * Adds the @buffer message to the MPC85xx outbound message queue. Returns 353 * %0 on success or %-EINVAL on failure. 354 */ 355 int 356 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 357 void *buffer, size_t len) 358 { 359 struct rio_priv *priv = mport->priv; 360 u32 omr; 361 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt 362 + priv->msg_tx_ring.tx_slot; 363 int ret = 0; 364 365 pr_debug 366 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n", 367 rdev->destid, mbox, (int)buffer, len); 368 369 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 370 ret = -EINVAL; 371 goto out; 372 } 373 374 /* Copy and clear rest of buffer */ 375 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer, 376 len); 377 if (len < (RIO_MAX_MSG_SIZE - 4)) 378 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot] 379 + len, 0, RIO_MAX_MSG_SIZE - len); 380 381 switch (mport->phy_type) { 382 case RIO_PHY_PARALLEL: 383 /* Set mbox field for message */ 384 desc->dport = mbox & 0x3; 385 386 /* Enable EOMI interrupt, set priority, and set destid */ 387 desc->dattr = 0x28000000 | (rdev->destid << 2); 388 break; 389 case RIO_PHY_SERIAL: 390 /* Set mbox field for message, and set destid */ 391 desc->dport = (rdev->destid << 16) | (mbox & 0x3); 392 393 /* Enable EOMI interrupt and priority */ 394 desc->dattr = 0x28000000; 395 break; 396 } 397 398 /* Set transfer size aligned to next power of 2 (in double words) */ 399 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); 400 401 /* Set snooping and source buffer address */ 402 desc->saddr = 0x00000004 403 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot]; 404 405 /* Increment enqueue pointer */ 406 omr = in_be32(&priv->msg_regs->omr); 407 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI); 408 409 /* Go to next descriptor */ 410 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size) 411 priv->msg_tx_ring.tx_slot = 0; 412 413 out: 414 return ret; 415 } 416 417 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message); 418 419 /** 420 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 421 * @irq: Linux interrupt number 422 * @dev_instance: Pointer to interrupt-specific data 423 * 424 * Handles outbound message interrupts. Executes a register outbound 425 * mailbox event handler and acks the interrupt occurrence. 426 */ 427 static irqreturn_t 428 fsl_rio_tx_handler(int irq, void *dev_instance) 429 { 430 int osr; 431 struct rio_mport *port = (struct rio_mport *)dev_instance; 432 struct rio_priv *priv = port->priv; 433 434 osr = in_be32(&priv->msg_regs->osr); 435 436 if (osr & RIO_MSG_OSR_TE) { 437 pr_info("RIO: outbound message transmission error\n"); 438 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE); 439 goto out; 440 } 441 442 if (osr & RIO_MSG_OSR_QOI) { 443 pr_info("RIO: outbound message queue overflow\n"); 444 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI); 445 goto out; 446 } 447 448 if (osr & RIO_MSG_OSR_EOMI) { 449 u32 dqp = in_be32(&priv->msg_regs->odqdpar); 450 int slot = (dqp - priv->msg_tx_ring.phys) >> 5; 451 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1, 452 slot); 453 454 /* Ack the end-of-message interrupt */ 455 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI); 456 } 457 458 out: 459 return IRQ_HANDLED; 460 } 461 462 /** 463 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox 464 * @mport: Master port implementing the outbound message unit 465 * @dev_id: Device specific pointer to pass on event 466 * @mbox: Mailbox to open 467 * @entries: Number of entries in the outbound mailbox ring 468 * 469 * Initializes buffer ring, request the outbound message interrupt, 470 * and enables the outbound message unit. Returns %0 on success and 471 * %-EINVAL or %-ENOMEM on failure. 472 */ 473 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 474 { 475 int i, j, rc = 0; 476 struct rio_priv *priv = mport->priv; 477 478 if ((entries < RIO_MIN_TX_RING_SIZE) || 479 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { 480 rc = -EINVAL; 481 goto out; 482 } 483 484 /* Initialize shadow copy ring */ 485 priv->msg_tx_ring.dev_id = dev_id; 486 priv->msg_tx_ring.size = entries; 487 488 for (i = 0; i < priv->msg_tx_ring.size; i++) { 489 priv->msg_tx_ring.virt_buffer[i] = 490 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 491 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL); 492 if (!priv->msg_tx_ring.virt_buffer[i]) { 493 rc = -ENOMEM; 494 for (j = 0; j < priv->msg_tx_ring.size; j++) 495 if (priv->msg_tx_ring.virt_buffer[j]) 496 dma_free_coherent(priv->dev, 497 RIO_MSG_BUFFER_SIZE, 498 priv->msg_tx_ring. 499 virt_buffer[j], 500 priv->msg_tx_ring. 501 phys_buffer[j]); 502 goto out; 503 } 504 } 505 506 /* Initialize outbound message descriptor ring */ 507 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, 508 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 509 &priv->msg_tx_ring.phys, GFP_KERNEL); 510 if (!priv->msg_tx_ring.virt) { 511 rc = -ENOMEM; 512 goto out_dma; 513 } 514 memset(priv->msg_tx_ring.virt, 0, 515 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE); 516 priv->msg_tx_ring.tx_slot = 0; 517 518 /* Point dequeue/enqueue pointers at first entry in ring */ 519 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys); 520 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys); 521 522 /* Configure for snooping */ 523 out_be32(&priv->msg_regs->osar, 0x00000004); 524 525 /* Clear interrupt status */ 526 out_be32(&priv->msg_regs->osr, 0x000000b3); 527 528 /* Hook up outbound message handler */ 529 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, 530 "msg_tx", (void *)mport); 531 if (rc < 0) 532 goto out_irq; 533 534 /* 535 * Configure outbound message unit 536 * Snooping 537 * Interrupts (all enabled, except QEIE) 538 * Chaining mode 539 * Disable 540 */ 541 out_be32(&priv->msg_regs->omr, 0x00100220); 542 543 /* Set number of entries */ 544 out_be32(&priv->msg_regs->omr, 545 in_be32(&priv->msg_regs->omr) | 546 ((get_bitmask_order(entries) - 2) << 12)); 547 548 /* Now enable the unit */ 549 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1); 550 551 out: 552 return rc; 553 554 out_irq: 555 dma_free_coherent(priv->dev, 556 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 557 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 558 559 out_dma: 560 for (i = 0; i < priv->msg_tx_ring.size; i++) 561 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 562 priv->msg_tx_ring.virt_buffer[i], 563 priv->msg_tx_ring.phys_buffer[i]); 564 565 return rc; 566 } 567 568 /** 569 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox 570 * @mport: Master port implementing the outbound message unit 571 * @mbox: Mailbox to close 572 * 573 * Disables the outbound message unit, free all buffers, and 574 * frees the outbound message interrupt. 575 */ 576 void rio_close_outb_mbox(struct rio_mport *mport, int mbox) 577 { 578 struct rio_priv *priv = mport->priv; 579 /* Disable inbound message unit */ 580 out_be32(&priv->msg_regs->omr, 0); 581 582 /* Free ring */ 583 dma_free_coherent(priv->dev, 584 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 585 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 586 587 /* Free interrupt */ 588 free_irq(IRQ_RIO_TX(mport), (void *)mport); 589 } 590 591 /** 592 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler 593 * @irq: Linux interrupt number 594 * @dev_instance: Pointer to interrupt-specific data 595 * 596 * Handles inbound message interrupts. Executes a registered inbound 597 * mailbox event handler and acks the interrupt occurrence. 598 */ 599 static irqreturn_t 600 fsl_rio_rx_handler(int irq, void *dev_instance) 601 { 602 int isr; 603 struct rio_mport *port = (struct rio_mport *)dev_instance; 604 struct rio_priv *priv = port->priv; 605 606 isr = in_be32(&priv->msg_regs->isr); 607 608 if (isr & RIO_MSG_ISR_TE) { 609 pr_info("RIO: inbound message reception error\n"); 610 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE); 611 goto out; 612 } 613 614 /* XXX Need to check/dispatch until queue empty */ 615 if (isr & RIO_MSG_ISR_DIQI) { 616 /* 617 * We implement *only* mailbox 0, but can receive messages 618 * for any mailbox/letter to that mailbox destination. So, 619 * make the callback with an unknown/invalid mailbox number 620 * argument. 621 */ 622 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1); 623 624 /* Ack the queueing interrupt */ 625 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI); 626 } 627 628 out: 629 return IRQ_HANDLED; 630 } 631 632 /** 633 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox 634 * @mport: Master port implementing the inbound message unit 635 * @dev_id: Device specific pointer to pass on event 636 * @mbox: Mailbox to open 637 * @entries: Number of entries in the inbound mailbox ring 638 * 639 * Initializes buffer ring, request the inbound message interrupt, 640 * and enables the inbound message unit. Returns %0 on success 641 * and %-EINVAL or %-ENOMEM on failure. 642 */ 643 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 644 { 645 int i, rc = 0; 646 struct rio_priv *priv = mport->priv; 647 648 if ((entries < RIO_MIN_RX_RING_SIZE) || 649 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { 650 rc = -EINVAL; 651 goto out; 652 } 653 654 /* Initialize client buffer ring */ 655 priv->msg_rx_ring.dev_id = dev_id; 656 priv->msg_rx_ring.size = entries; 657 priv->msg_rx_ring.rx_slot = 0; 658 for (i = 0; i < priv->msg_rx_ring.size; i++) 659 priv->msg_rx_ring.virt_buffer[i] = NULL; 660 661 /* Initialize inbound message ring */ 662 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, 663 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 664 &priv->msg_rx_ring.phys, GFP_KERNEL); 665 if (!priv->msg_rx_ring.virt) { 666 rc = -ENOMEM; 667 goto out; 668 } 669 670 /* Point dequeue/enqueue pointers at first entry in ring */ 671 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys); 672 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys); 673 674 /* Clear interrupt status */ 675 out_be32(&priv->msg_regs->isr, 0x00000091); 676 677 /* Hook up inbound message handler */ 678 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 679 "msg_rx", (void *)mport); 680 if (rc < 0) { 681 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 682 priv->msg_tx_ring.virt_buffer[i], 683 priv->msg_tx_ring.phys_buffer[i]); 684 goto out; 685 } 686 687 /* 688 * Configure inbound message unit: 689 * Snooping 690 * 4KB max message size 691 * Unmask all interrupt sources 692 * Disable 693 */ 694 out_be32(&priv->msg_regs->imr, 0x001b0060); 695 696 /* Set number of queue entries */ 697 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); 698 699 /* Now enable the unit */ 700 setbits32(&priv->msg_regs->imr, 0x1); 701 702 out: 703 return rc; 704 } 705 706 /** 707 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox 708 * @mport: Master port implementing the inbound message unit 709 * @mbox: Mailbox to close 710 * 711 * Disables the inbound message unit, free all buffers, and 712 * frees the inbound message interrupt. 713 */ 714 void rio_close_inb_mbox(struct rio_mport *mport, int mbox) 715 { 716 struct rio_priv *priv = mport->priv; 717 /* Disable inbound message unit */ 718 out_be32(&priv->msg_regs->imr, 0); 719 720 /* Free ring */ 721 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 722 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys); 723 724 /* Free interrupt */ 725 free_irq(IRQ_RIO_RX(mport), (void *)mport); 726 } 727 728 /** 729 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 730 * @mport: Master port implementing the inbound message unit 731 * @mbox: Inbound mailbox number 732 * @buf: Buffer to add to inbound queue 733 * 734 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 735 * %0 on success or %-EINVAL on failure. 736 */ 737 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 738 { 739 int rc = 0; 740 struct rio_priv *priv = mport->priv; 741 742 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 743 priv->msg_rx_ring.rx_slot); 744 745 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { 746 printk(KERN_ERR 747 "RIO: error adding inbound buffer %d, buffer exists\n", 748 priv->msg_rx_ring.rx_slot); 749 rc = -EINVAL; 750 goto out; 751 } 752 753 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf; 754 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size) 755 priv->msg_rx_ring.rx_slot = 0; 756 757 out: 758 return rc; 759 } 760 761 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer); 762 763 /** 764 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit 765 * @mport: Master port implementing the inbound message unit 766 * @mbox: Inbound mailbox number 767 * 768 * Gets the next available inbound message from the inbound message queue. 769 * A pointer to the message is returned on success or NULL on failure. 770 */ 771 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) 772 { 773 struct rio_priv *priv = mport->priv; 774 u32 phys_buf, virt_buf; 775 void *buf = NULL; 776 int buf_idx; 777 778 phys_buf = in_be32(&priv->msg_regs->ifqdpar); 779 780 /* If no more messages, then bail out */ 781 if (phys_buf == in_be32(&priv->msg_regs->ifqepar)) 782 goto out2; 783 784 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf 785 - priv->msg_rx_ring.phys); 786 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 787 buf = priv->msg_rx_ring.virt_buffer[buf_idx]; 788 789 if (!buf) { 790 printk(KERN_ERR 791 "RIO: inbound message copy failed, no buffers\n"); 792 goto out1; 793 } 794 795 /* Copy max message size, caller is expected to allocate that big */ 796 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); 797 798 /* Clear the available buffer */ 799 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL; 800 801 out1: 802 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI); 803 804 out2: 805 return buf; 806 } 807 808 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message); 809 810 /** 811 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 812 * @irq: Linux interrupt number 813 * @dev_instance: Pointer to interrupt-specific data 814 * 815 * Handles doorbell interrupts. Parses a list of registered 816 * doorbell event handlers and executes a matching event handler. 817 */ 818 static irqreturn_t 819 fsl_rio_dbell_handler(int irq, void *dev_instance) 820 { 821 int dsr; 822 struct rio_mport *port = (struct rio_mport *)dev_instance; 823 struct rio_priv *priv = port->priv; 824 825 dsr = in_be32(&priv->msg_regs->dsr); 826 827 if (dsr & DOORBELL_DSR_TE) { 828 pr_info("RIO: doorbell reception error\n"); 829 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE); 830 goto out; 831 } 832 833 if (dsr & DOORBELL_DSR_QFI) { 834 pr_info("RIO: doorbell queue full\n"); 835 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI); 836 goto out; 837 } 838 839 /* XXX Need to check/dispatch until queue empty */ 840 if (dsr & DOORBELL_DSR_DIQI) { 841 u32 dmsg = 842 (u32) priv->dbell_ring.virt + 843 (in_be32(&priv->msg_regs->dqdpar) & 0xfff); 844 struct rio_dbell *dbell; 845 int found = 0; 846 847 pr_debug 848 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", 849 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 850 851 list_for_each_entry(dbell, &port->dbells, node) { 852 if ((dbell->res->start <= DBELL_INF(dmsg)) && 853 (dbell->res->end >= DBELL_INF(dmsg))) { 854 found = 1; 855 break; 856 } 857 } 858 if (found) { 859 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), 860 DBELL_INF(dmsg)); 861 } else { 862 pr_debug 863 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", 864 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 865 } 866 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI); 867 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI); 868 } 869 870 out: 871 return IRQ_HANDLED; 872 } 873 874 /** 875 * fsl_rio_doorbell_init - MPC85xx doorbell interface init 876 * @mport: Master port implementing the inbound doorbell unit 877 * 878 * Initializes doorbell unit hardware and inbound DMA buffer 879 * ring. Called from fsl_rio_setup(). Returns %0 on success 880 * or %-ENOMEM on failure. 881 */ 882 static int fsl_rio_doorbell_init(struct rio_mport *mport) 883 { 884 struct rio_priv *priv = mport->priv; 885 int rc = 0; 886 887 /* Map outbound doorbell window immediately after maintenance window */ 888 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, 889 RIO_DBELL_WIN_SIZE); 890 if (!priv->dbell_win) { 891 printk(KERN_ERR 892 "RIO: unable to map outbound doorbell window\n"); 893 rc = -ENOMEM; 894 goto out; 895 } 896 897 /* Initialize inbound doorbells */ 898 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 * 899 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL); 900 if (!priv->dbell_ring.virt) { 901 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); 902 rc = -ENOMEM; 903 iounmap(priv->dbell_win); 904 goto out; 905 } 906 907 /* Point dequeue/enqueue pointers at first entry in ring */ 908 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys); 909 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys); 910 911 /* Clear interrupt status */ 912 out_be32(&priv->msg_regs->dsr, 0x00000091); 913 914 /* Hook up doorbell handler */ 915 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, 916 "dbell_rx", (void *)mport); 917 if (rc < 0) { 918 iounmap(priv->dbell_win); 919 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE, 920 priv->dbell_ring.virt, priv->dbell_ring.phys); 921 printk(KERN_ERR 922 "MPC85xx RIO: unable to request inbound doorbell irq"); 923 goto out; 924 } 925 926 /* Configure doorbells for snooping, 512 entries, and enable */ 927 out_be32(&priv->msg_regs->dmr, 0x00108161); 928 929 out: 930 return rc; 931 } 932 933 static char *cmdline = NULL; 934 935 static int fsl_rio_get_hdid(int index) 936 { 937 /* XXX Need to parse multiple entries in some format */ 938 if (!cmdline) 939 return -1; 940 941 return simple_strtol(cmdline, NULL, 0); 942 } 943 944 static int fsl_rio_get_cmdline(char *s) 945 { 946 if (!s) 947 return 0; 948 949 cmdline = s; 950 return 1; 951 } 952 953 __setup("riohdid=", fsl_rio_get_cmdline); 954 955 static inline void fsl_rio_info(struct device *dev, u32 ccsr) 956 { 957 const char *str; 958 if (ccsr & 1) { 959 /* Serial phy */ 960 switch (ccsr >> 30) { 961 case 0: 962 str = "1"; 963 break; 964 case 1: 965 str = "4"; 966 break; 967 default: 968 str = "Unknown"; 969 break; 970 } 971 dev_info(dev, "Hardware port width: %s\n", str); 972 973 switch ((ccsr >> 27) & 7) { 974 case 0: 975 str = "Single-lane 0"; 976 break; 977 case 1: 978 str = "Single-lane 2"; 979 break; 980 case 2: 981 str = "Four-lane"; 982 break; 983 default: 984 str = "Unknown"; 985 break; 986 } 987 dev_info(dev, "Training connection status: %s\n", str); 988 } else { 989 /* Parallel phy */ 990 if (!(ccsr & 0x80000000)) 991 dev_info(dev, "Output port operating in 8-bit mode\n"); 992 if (!(ccsr & 0x08000000)) 993 dev_info(dev, "Input port operating in 8-bit mode\n"); 994 } 995 } 996 997 /** 998 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface 999 * @dev: of_device pointer 1000 * 1001 * Initializes MPC85xx RapidIO hardware interface, configures 1002 * master port with system-specific info, and registers the 1003 * master port with the RapidIO subsystem. 1004 */ 1005 int fsl_rio_setup(struct of_device *dev) 1006 { 1007 struct rio_ops *ops; 1008 struct rio_mport *port; 1009 struct rio_priv *priv; 1010 int rc = 0; 1011 const u32 *dt_range, *cell; 1012 struct resource regs; 1013 int rlen; 1014 u32 ccsr; 1015 u64 law_start, law_size; 1016 int paw, aw, sw; 1017 1018 if (!dev->dev.of_node) { 1019 dev_err(&dev->dev, "Device OF-Node is NULL"); 1020 return -EFAULT; 1021 } 1022 1023 rc = of_address_to_resource(dev->dev.of_node, 0, ®s); 1024 if (rc) { 1025 dev_err(&dev->dev, "Can't get %s property 'reg'\n", 1026 dev->dev.of_node->full_name); 1027 return -EFAULT; 1028 } 1029 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); 1030 dev_info(&dev->dev, "Regs: %pR\n", ®s); 1031 1032 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); 1033 if (!dt_range) { 1034 dev_err(&dev->dev, "Can't get %s property 'ranges'\n", 1035 dev->dev.of_node->full_name); 1036 return -EFAULT; 1037 } 1038 1039 /* Get node address wide */ 1040 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL); 1041 if (cell) 1042 aw = *cell; 1043 else 1044 aw = of_n_addr_cells(dev->dev.of_node); 1045 /* Get node size wide */ 1046 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL); 1047 if (cell) 1048 sw = *cell; 1049 else 1050 sw = of_n_size_cells(dev->dev.of_node); 1051 /* Get parent address wide wide */ 1052 paw = of_n_addr_cells(dev->dev.of_node); 1053 1054 law_start = of_read_number(dt_range + aw, paw); 1055 law_size = of_read_number(dt_range + aw + paw, sw); 1056 1057 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n", 1058 law_start, law_size); 1059 1060 ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL); 1061 if (!ops) { 1062 rc = -ENOMEM; 1063 goto err_ops; 1064 } 1065 ops->lcread = fsl_local_config_read; 1066 ops->lcwrite = fsl_local_config_write; 1067 ops->cread = fsl_rio_config_read; 1068 ops->cwrite = fsl_rio_config_write; 1069 ops->dsend = fsl_rio_doorbell_send; 1070 1071 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 1072 if (!port) { 1073 rc = -ENOMEM; 1074 goto err_port; 1075 } 1076 port->id = 0; 1077 port->index = 0; 1078 1079 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); 1080 if (!priv) { 1081 printk(KERN_ERR "Can't alloc memory for 'priv'\n"); 1082 rc = -ENOMEM; 1083 goto err_priv; 1084 } 1085 1086 INIT_LIST_HEAD(&port->dbells); 1087 port->iores.start = law_start; 1088 port->iores.end = law_start + law_size - 1; 1089 port->iores.flags = IORESOURCE_MEM; 1090 port->iores.name = "rio_io_win"; 1091 1092 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 1093 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); 1094 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); 1095 dev_info(&dev->dev, "bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq, 1096 priv->txirq, priv->rxirq); 1097 1098 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 1099 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 1100 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 1101 strcpy(port->name, "RIO0 mport"); 1102 1103 priv->dev = &dev->dev; 1104 1105 port->ops = ops; 1106 port->host_deviceid = fsl_rio_get_hdid(port->id); 1107 1108 port->priv = priv; 1109 rio_register_mport(port); 1110 1111 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); 1112 1113 /* Probe the master port phy type */ 1114 ccsr = in_be32(priv->regs_win + RIO_CCSR); 1115 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; 1116 dev_info(&dev->dev, "RapidIO PHY type: %s\n", 1117 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" : 1118 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" : 1119 "unknown")); 1120 /* Checking the port training status */ 1121 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 1122 dev_err(&dev->dev, "Port is not ready. " 1123 "Try to restart connection...\n"); 1124 switch (port->phy_type) { 1125 case RIO_PHY_SERIAL: 1126 /* Disable ports */ 1127 out_be32(priv->regs_win + RIO_CCSR, 0); 1128 /* Set 1x lane */ 1129 setbits32(priv->regs_win + RIO_CCSR, 0x02000000); 1130 /* Enable ports */ 1131 setbits32(priv->regs_win + RIO_CCSR, 0x00600000); 1132 break; 1133 case RIO_PHY_PARALLEL: 1134 /* Disable ports */ 1135 out_be32(priv->regs_win + RIO_CCSR, 0x22000000); 1136 /* Enable ports */ 1137 out_be32(priv->regs_win + RIO_CCSR, 0x44000000); 1138 break; 1139 } 1140 msleep(100); 1141 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 1142 dev_err(&dev->dev, "Port restart failed.\n"); 1143 rc = -ENOLINK; 1144 goto err; 1145 } 1146 dev_info(&dev->dev, "Port restart success!\n"); 1147 } 1148 fsl_rio_info(&dev->dev, ccsr); 1149 1150 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 1151 & RIO_PEF_CTLS) >> 4; 1152 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 1153 port->sys_size ? 65536 : 256); 1154 1155 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 1156 + RIO_ATMU_REGS_OFFSET); 1157 priv->maint_atmu_regs = priv->atmu_regs + 1; 1158 priv->dbell_atmu_regs = priv->atmu_regs + 2; 1159 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + 1160 ((port->phy_type == RIO_PHY_SERIAL) ? 1161 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); 1162 1163 /* Set to receive any dist ID for serial RapidIO controller. */ 1164 if (port->phy_type == RIO_PHY_SERIAL) 1165 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); 1166 1167 /* Configure maintenance transaction window */ 1168 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12); 1169 out_be32(&priv->maint_atmu_regs->rowar, 0x80077015); /* 4M */ 1170 1171 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); 1172 1173 /* Configure outbound doorbell window */ 1174 out_be32(&priv->dbell_atmu_regs->rowbar, 1175 (law_start + RIO_MAINT_WIN_SIZE) >> 12); 1176 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ 1177 fsl_rio_doorbell_init(port); 1178 1179 return 0; 1180 err: 1181 iounmap(priv->regs_win); 1182 kfree(priv); 1183 err_priv: 1184 kfree(port); 1185 err_port: 1186 kfree(ops); 1187 err_ops: 1188 return rc; 1189 } 1190 1191 /* The probe function for RapidIO peer-to-peer network. 1192 */ 1193 static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev, 1194 const struct of_device_id *match) 1195 { 1196 int rc; 1197 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", 1198 dev->dev.of_node->full_name); 1199 1200 rc = fsl_rio_setup(dev); 1201 if (rc) 1202 goto out; 1203 1204 /* Enumerate all registered ports */ 1205 rc = rio_init_mports(); 1206 out: 1207 return rc; 1208 }; 1209 1210 static const struct of_device_id fsl_of_rio_rpn_ids[] = { 1211 { 1212 .compatible = "fsl,rapidio-delta", 1213 }, 1214 {}, 1215 }; 1216 1217 static struct of_platform_driver fsl_of_rio_rpn_driver = { 1218 .driver = { 1219 .name = "fsl-of-rio", 1220 .owner = THIS_MODULE, 1221 .of_match_table = fsl_of_rio_rpn_ids, 1222 }, 1223 .probe = fsl_of_rio_rpn_probe, 1224 }; 1225 1226 static __init int fsl_of_rio_rpn_init(void) 1227 { 1228 return of_register_platform_driver(&fsl_of_rio_rpn_driver); 1229 } 1230 1231 subsys_initcall(fsl_of_rio_rpn_init); 1232