1 /* 2 * Freescale MPC85xx/MPC86xx RapidIO support 3 * 4 * Copyright 2009 Sysgo AG 5 * Thomas Moll <thomas.moll@sysgo.com> 6 * - fixed maintenance access routines, check for aligned access 7 * 8 * Copyright 2009 Integrated Device Technology, Inc. 9 * Alex Bounine <alexandre.bounine@idt.com> 10 * - Added Port-Write message handling 11 * - Added Machine Check exception handling 12 * 13 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc. 14 * Zhang Wei <wei.zhang@freescale.com> 15 * 16 * Copyright 2005 MontaVista Software, Inc. 17 * Matt Porter <mporter@kernel.crashing.org> 18 * 19 * This program is free software; you can redistribute it and/or modify it 20 * under the terms of the GNU General Public License as published by the 21 * Free Software Foundation; either version 2 of the License, or (at your 22 * option) any later version. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/interrupt.h> 30 #include <linux/device.h> 31 #include <linux/rio.h> 32 #include <linux/rio_drv.h> 33 #include <linux/of_platform.h> 34 #include <linux/delay.h> 35 #include <linux/slab.h> 36 #include <linux/kfifo.h> 37 38 #include <asm/io.h> 39 #include <asm/machdep.h> 40 #include <asm/uaccess.h> 41 42 #undef DEBUG_PW /* Port-Write debugging */ 43 44 /* RapidIO definition irq, which read from OF-tree */ 45 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) 46 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) 47 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) 48 #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) 49 50 #define RIO_ATMU_REGS_OFFSET 0x10c00 51 #define RIO_P_MSG_REGS_OFFSET 0x11000 52 #define RIO_S_MSG_REGS_OFFSET 0x13000 53 #define RIO_ESCSR 0x158 54 #define RIO_CCSR 0x15c 55 #define RIO_LTLEDCSR 0x0608 56 #define RIO_LTLEDCSR_IER 0x80000000 57 #define RIO_LTLEDCSR_PRT 0x01000000 58 #define RIO_LTLEECSR 0x060c 59 #define RIO_EPWISR 0x10010 60 #define RIO_ISR_AACR 0x10120 61 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 62 #define RIO_MAINT_WIN_SIZE 0x400000 63 #define RIO_DBELL_WIN_SIZE 0x1000 64 65 #define RIO_MSG_OMR_MUI 0x00000002 66 #define RIO_MSG_OSR_TE 0x00000080 67 #define RIO_MSG_OSR_QOI 0x00000020 68 #define RIO_MSG_OSR_QFI 0x00000010 69 #define RIO_MSG_OSR_MUB 0x00000004 70 #define RIO_MSG_OSR_EOMI 0x00000002 71 #define RIO_MSG_OSR_QEI 0x00000001 72 73 #define RIO_MSG_IMR_MI 0x00000002 74 #define RIO_MSG_ISR_TE 0x00000080 75 #define RIO_MSG_ISR_QFI 0x00000010 76 #define RIO_MSG_ISR_DIQI 0x00000001 77 78 #define RIO_IPWMR_SEN 0x00100000 79 #define RIO_IPWMR_QFIE 0x00000100 80 #define RIO_IPWMR_EIE 0x00000020 81 #define RIO_IPWMR_CQ 0x00000002 82 #define RIO_IPWMR_PWE 0x00000001 83 84 #define RIO_IPWSR_QF 0x00100000 85 #define RIO_IPWSR_TE 0x00000080 86 #define RIO_IPWSR_QFI 0x00000010 87 #define RIO_IPWSR_PWD 0x00000008 88 #define RIO_IPWSR_PWB 0x00000004 89 90 #define RIO_MSG_DESC_SIZE 32 91 #define RIO_MSG_BUFFER_SIZE 4096 92 #define RIO_MIN_TX_RING_SIZE 2 93 #define RIO_MAX_TX_RING_SIZE 2048 94 #define RIO_MIN_RX_RING_SIZE 2 95 #define RIO_MAX_RX_RING_SIZE 2048 96 97 #define DOORBELL_DMR_DI 0x00000002 98 #define DOORBELL_DSR_TE 0x00000080 99 #define DOORBELL_DSR_QFI 0x00000010 100 #define DOORBELL_DSR_DIQI 0x00000001 101 #define DOORBELL_TID_OFFSET 0x02 102 #define DOORBELL_SID_OFFSET 0x04 103 #define DOORBELL_INFO_OFFSET 0x06 104 105 #define DOORBELL_MESSAGE_SIZE 0x08 106 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) 107 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) 108 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) 109 110 struct rio_atmu_regs { 111 u32 rowtar; 112 u32 rowtear; 113 u32 rowbar; 114 u32 pad2; 115 u32 rowar; 116 u32 pad3[3]; 117 }; 118 119 struct rio_msg_regs { 120 u32 omr; 121 u32 osr; 122 u32 pad1; 123 u32 odqdpar; 124 u32 pad2; 125 u32 osar; 126 u32 odpr; 127 u32 odatr; 128 u32 odcr; 129 u32 pad3; 130 u32 odqepar; 131 u32 pad4[13]; 132 u32 imr; 133 u32 isr; 134 u32 pad5; 135 u32 ifqdpar; 136 u32 pad6; 137 u32 ifqepar; 138 u32 pad7[226]; 139 u32 odmr; 140 u32 odsr; 141 u32 res0[4]; 142 u32 oddpr; 143 u32 oddatr; 144 u32 res1[3]; 145 u32 odretcr; 146 u32 res2[12]; 147 u32 dmr; 148 u32 dsr; 149 u32 pad8; 150 u32 dqdpar; 151 u32 pad9; 152 u32 dqepar; 153 u32 pad10[26]; 154 u32 pwmr; 155 u32 pwsr; 156 u32 epwqbar; 157 u32 pwqbar; 158 }; 159 160 struct rio_tx_desc { 161 u32 res1; 162 u32 saddr; 163 u32 dport; 164 u32 dattr; 165 u32 res2; 166 u32 res3; 167 u32 dwcnt; 168 u32 res4; 169 }; 170 171 struct rio_dbell_ring { 172 void *virt; 173 dma_addr_t phys; 174 }; 175 176 struct rio_msg_tx_ring { 177 void *virt; 178 dma_addr_t phys; 179 void *virt_buffer[RIO_MAX_TX_RING_SIZE]; 180 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; 181 int tx_slot; 182 int size; 183 void *dev_id; 184 }; 185 186 struct rio_msg_rx_ring { 187 void *virt; 188 dma_addr_t phys; 189 void *virt_buffer[RIO_MAX_RX_RING_SIZE]; 190 int rx_slot; 191 int size; 192 void *dev_id; 193 }; 194 195 struct rio_port_write_msg { 196 void *virt; 197 dma_addr_t phys; 198 u32 msg_count; 199 u32 err_count; 200 u32 discard_count; 201 }; 202 203 struct rio_priv { 204 struct device *dev; 205 void __iomem *regs_win; 206 struct rio_atmu_regs __iomem *atmu_regs; 207 struct rio_atmu_regs __iomem *maint_atmu_regs; 208 struct rio_atmu_regs __iomem *dbell_atmu_regs; 209 void __iomem *dbell_win; 210 void __iomem *maint_win; 211 struct rio_msg_regs __iomem *msg_regs; 212 struct rio_dbell_ring dbell_ring; 213 struct rio_msg_tx_ring msg_tx_ring; 214 struct rio_msg_rx_ring msg_rx_ring; 215 struct rio_port_write_msg port_write_msg; 216 int bellirq; 217 int txirq; 218 int rxirq; 219 int pwirq; 220 struct work_struct pw_work; 221 struct kfifo pw_fifo; 222 spinlock_t pw_fifo_lock; 223 }; 224 225 #define __fsl_read_rio_config(x, addr, err, op) \ 226 __asm__ __volatile__( \ 227 "1: "op" %1,0(%2)\n" \ 228 " eieio\n" \ 229 "2:\n" \ 230 ".section .fixup,\"ax\"\n" \ 231 "3: li %1,-1\n" \ 232 " li %0,%3\n" \ 233 " b 2b\n" \ 234 ".section __ex_table,\"a\"\n" \ 235 " .align 2\n" \ 236 " .long 1b,3b\n" \ 237 ".text" \ 238 : "=r" (err), "=r" (x) \ 239 : "b" (addr), "i" (-EFAULT), "0" (err)) 240 241 static void __iomem *rio_regs_win; 242 243 #ifdef CONFIG_E500 244 static int (*saved_mcheck_exception)(struct pt_regs *regs); 245 246 static int fsl_rio_mcheck_exception(struct pt_regs *regs) 247 { 248 const struct exception_table_entry *entry = NULL; 249 unsigned long reason = mfspr(SPRN_MCSR); 250 251 if (reason & MCSR_BUS_RBERR) { 252 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR)); 253 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) { 254 /* Check if we are prepared to handle this fault */ 255 entry = search_exception_tables(regs->nip); 256 if (entry) { 257 pr_debug("RIO: %s - MC Exception handled\n", 258 __func__); 259 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 260 0); 261 regs->msr |= MSR_RI; 262 regs->nip = entry->fixup; 263 return 1; 264 } 265 } 266 } 267 268 if (saved_mcheck_exception) 269 return saved_mcheck_exception(regs); 270 else 271 return cur_cpu_spec->machine_check(regs); 272 } 273 #endif 274 275 /** 276 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message 277 * @mport: RapidIO master port info 278 * @index: ID of RapidIO interface 279 * @destid: Destination ID of target device 280 * @data: 16-bit info field of RapidIO doorbell message 281 * 282 * Sends a MPC85xx doorbell message. Returns %0 on success or 283 * %-EINVAL on failure. 284 */ 285 static int fsl_rio_doorbell_send(struct rio_mport *mport, 286 int index, u16 destid, u16 data) 287 { 288 struct rio_priv *priv = mport->priv; 289 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", 290 index, destid, data); 291 switch (mport->phy_type) { 292 case RIO_PHY_PARALLEL: 293 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22); 294 out_be16(priv->dbell_win, data); 295 break; 296 case RIO_PHY_SERIAL: 297 /* In the serial version silicons, such as MPC8548, MPC8641, 298 * below operations is must be. 299 */ 300 out_be32(&priv->msg_regs->odmr, 0x00000000); 301 out_be32(&priv->msg_regs->odretcr, 0x00000004); 302 out_be32(&priv->msg_regs->oddpr, destid << 16); 303 out_be32(&priv->msg_regs->oddatr, data); 304 out_be32(&priv->msg_regs->odmr, 0x00000001); 305 break; 306 } 307 308 return 0; 309 } 310 311 /** 312 * fsl_local_config_read - Generate a MPC85xx local config space read 313 * @mport: RapidIO master port info 314 * @index: ID of RapdiIO interface 315 * @offset: Offset into configuration space 316 * @len: Length (in bytes) of the maintenance transaction 317 * @data: Value to be read into 318 * 319 * Generates a MPC85xx local configuration space read. Returns %0 on 320 * success or %-EINVAL on failure. 321 */ 322 static int fsl_local_config_read(struct rio_mport *mport, 323 int index, u32 offset, int len, u32 *data) 324 { 325 struct rio_priv *priv = mport->priv; 326 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, 327 offset); 328 *data = in_be32(priv->regs_win + offset); 329 330 return 0; 331 } 332 333 /** 334 * fsl_local_config_write - Generate a MPC85xx local config space write 335 * @mport: RapidIO master port info 336 * @index: ID of RapdiIO interface 337 * @offset: Offset into configuration space 338 * @len: Length (in bytes) of the maintenance transaction 339 * @data: Value to be written 340 * 341 * Generates a MPC85xx local configuration space write. Returns %0 on 342 * success or %-EINVAL on failure. 343 */ 344 static int fsl_local_config_write(struct rio_mport *mport, 345 int index, u32 offset, int len, u32 data) 346 { 347 struct rio_priv *priv = mport->priv; 348 pr_debug 349 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 350 index, offset, data); 351 out_be32(priv->regs_win + offset, data); 352 353 return 0; 354 } 355 356 /** 357 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction 358 * @mport: RapidIO master port info 359 * @index: ID of RapdiIO interface 360 * @destid: Destination ID of transaction 361 * @hopcount: Number of hops to target device 362 * @offset: Offset into configuration space 363 * @len: Length (in bytes) of the maintenance transaction 364 * @val: Location to be read into 365 * 366 * Generates a MPC85xx read maintenance transaction. Returns %0 on 367 * success or %-EINVAL on failure. 368 */ 369 static int 370 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, 371 u8 hopcount, u32 offset, int len, u32 *val) 372 { 373 struct rio_priv *priv = mport->priv; 374 u8 *data; 375 u32 rval, err = 0; 376 377 pr_debug 378 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", 379 index, destid, hopcount, offset, len); 380 381 /* 16MB maintenance window possible */ 382 /* allow only aligned access to maintenance registers */ 383 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) 384 return -EINVAL; 385 386 out_be32(&priv->maint_atmu_regs->rowtar, 387 (destid << 22) | (hopcount << 12) | (offset >> 12)); 388 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 389 390 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 391 switch (len) { 392 case 1: 393 __fsl_read_rio_config(rval, data, err, "lbz"); 394 break; 395 case 2: 396 __fsl_read_rio_config(rval, data, err, "lhz"); 397 break; 398 case 4: 399 __fsl_read_rio_config(rval, data, err, "lwz"); 400 break; 401 default: 402 return -EINVAL; 403 } 404 405 if (err) { 406 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n", 407 err, destid, hopcount, offset); 408 } 409 410 *val = rval; 411 412 return err; 413 } 414 415 /** 416 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction 417 * @mport: RapidIO master port info 418 * @index: ID of RapdiIO interface 419 * @destid: Destination ID of transaction 420 * @hopcount: Number of hops to target device 421 * @offset: Offset into configuration space 422 * @len: Length (in bytes) of the maintenance transaction 423 * @val: Value to be written 424 * 425 * Generates an MPC85xx write maintenance transaction. Returns %0 on 426 * success or %-EINVAL on failure. 427 */ 428 static int 429 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, 430 u8 hopcount, u32 offset, int len, u32 val) 431 { 432 struct rio_priv *priv = mport->priv; 433 u8 *data; 434 pr_debug 435 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 436 index, destid, hopcount, offset, len, val); 437 438 /* 16MB maintenance windows possible */ 439 /* allow only aligned access to maintenance registers */ 440 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) 441 return -EINVAL; 442 443 out_be32(&priv->maint_atmu_regs->rowtar, 444 (destid << 22) | (hopcount << 12) | (offset >> 12)); 445 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 446 447 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 448 switch (len) { 449 case 1: 450 out_8((u8 *) data, val); 451 break; 452 case 2: 453 out_be16((u16 *) data, val); 454 break; 455 case 4: 456 out_be32((u32 *) data, val); 457 break; 458 default: 459 return -EINVAL; 460 } 461 462 return 0; 463 } 464 465 /** 466 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue 467 * @mport: Master port with outbound message queue 468 * @rdev: Target of outbound message 469 * @mbox: Outbound mailbox 470 * @buffer: Message to add to outbound queue 471 * @len: Length of message 472 * 473 * Adds the @buffer message to the MPC85xx outbound message queue. Returns 474 * %0 on success or %-EINVAL on failure. 475 */ 476 int 477 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 478 void *buffer, size_t len) 479 { 480 struct rio_priv *priv = mport->priv; 481 u32 omr; 482 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt 483 + priv->msg_tx_ring.tx_slot; 484 int ret = 0; 485 486 pr_debug 487 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n", 488 rdev->destid, mbox, (int)buffer, len); 489 490 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 491 ret = -EINVAL; 492 goto out; 493 } 494 495 /* Copy and clear rest of buffer */ 496 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer, 497 len); 498 if (len < (RIO_MAX_MSG_SIZE - 4)) 499 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot] 500 + len, 0, RIO_MAX_MSG_SIZE - len); 501 502 switch (mport->phy_type) { 503 case RIO_PHY_PARALLEL: 504 /* Set mbox field for message */ 505 desc->dport = mbox & 0x3; 506 507 /* Enable EOMI interrupt, set priority, and set destid */ 508 desc->dattr = 0x28000000 | (rdev->destid << 2); 509 break; 510 case RIO_PHY_SERIAL: 511 /* Set mbox field for message, and set destid */ 512 desc->dport = (rdev->destid << 16) | (mbox & 0x3); 513 514 /* Enable EOMI interrupt and priority */ 515 desc->dattr = 0x28000000; 516 break; 517 } 518 519 /* Set transfer size aligned to next power of 2 (in double words) */ 520 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); 521 522 /* Set snooping and source buffer address */ 523 desc->saddr = 0x00000004 524 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot]; 525 526 /* Increment enqueue pointer */ 527 omr = in_be32(&priv->msg_regs->omr); 528 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI); 529 530 /* Go to next descriptor */ 531 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size) 532 priv->msg_tx_ring.tx_slot = 0; 533 534 out: 535 return ret; 536 } 537 538 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message); 539 540 /** 541 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 542 * @irq: Linux interrupt number 543 * @dev_instance: Pointer to interrupt-specific data 544 * 545 * Handles outbound message interrupts. Executes a register outbound 546 * mailbox event handler and acks the interrupt occurrence. 547 */ 548 static irqreturn_t 549 fsl_rio_tx_handler(int irq, void *dev_instance) 550 { 551 int osr; 552 struct rio_mport *port = (struct rio_mport *)dev_instance; 553 struct rio_priv *priv = port->priv; 554 555 osr = in_be32(&priv->msg_regs->osr); 556 557 if (osr & RIO_MSG_OSR_TE) { 558 pr_info("RIO: outbound message transmission error\n"); 559 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE); 560 goto out; 561 } 562 563 if (osr & RIO_MSG_OSR_QOI) { 564 pr_info("RIO: outbound message queue overflow\n"); 565 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI); 566 goto out; 567 } 568 569 if (osr & RIO_MSG_OSR_EOMI) { 570 u32 dqp = in_be32(&priv->msg_regs->odqdpar); 571 int slot = (dqp - priv->msg_tx_ring.phys) >> 5; 572 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1, 573 slot); 574 575 /* Ack the end-of-message interrupt */ 576 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI); 577 } 578 579 out: 580 return IRQ_HANDLED; 581 } 582 583 /** 584 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox 585 * @mport: Master port implementing the outbound message unit 586 * @dev_id: Device specific pointer to pass on event 587 * @mbox: Mailbox to open 588 * @entries: Number of entries in the outbound mailbox ring 589 * 590 * Initializes buffer ring, request the outbound message interrupt, 591 * and enables the outbound message unit. Returns %0 on success and 592 * %-EINVAL or %-ENOMEM on failure. 593 */ 594 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 595 { 596 int i, j, rc = 0; 597 struct rio_priv *priv = mport->priv; 598 599 if ((entries < RIO_MIN_TX_RING_SIZE) || 600 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { 601 rc = -EINVAL; 602 goto out; 603 } 604 605 /* Initialize shadow copy ring */ 606 priv->msg_tx_ring.dev_id = dev_id; 607 priv->msg_tx_ring.size = entries; 608 609 for (i = 0; i < priv->msg_tx_ring.size; i++) { 610 priv->msg_tx_ring.virt_buffer[i] = 611 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 612 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL); 613 if (!priv->msg_tx_ring.virt_buffer[i]) { 614 rc = -ENOMEM; 615 for (j = 0; j < priv->msg_tx_ring.size; j++) 616 if (priv->msg_tx_ring.virt_buffer[j]) 617 dma_free_coherent(priv->dev, 618 RIO_MSG_BUFFER_SIZE, 619 priv->msg_tx_ring. 620 virt_buffer[j], 621 priv->msg_tx_ring. 622 phys_buffer[j]); 623 goto out; 624 } 625 } 626 627 /* Initialize outbound message descriptor ring */ 628 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, 629 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 630 &priv->msg_tx_ring.phys, GFP_KERNEL); 631 if (!priv->msg_tx_ring.virt) { 632 rc = -ENOMEM; 633 goto out_dma; 634 } 635 memset(priv->msg_tx_ring.virt, 0, 636 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE); 637 priv->msg_tx_ring.tx_slot = 0; 638 639 /* Point dequeue/enqueue pointers at first entry in ring */ 640 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys); 641 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys); 642 643 /* Configure for snooping */ 644 out_be32(&priv->msg_regs->osar, 0x00000004); 645 646 /* Clear interrupt status */ 647 out_be32(&priv->msg_regs->osr, 0x000000b3); 648 649 /* Hook up outbound message handler */ 650 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, 651 "msg_tx", (void *)mport); 652 if (rc < 0) 653 goto out_irq; 654 655 /* 656 * Configure outbound message unit 657 * Snooping 658 * Interrupts (all enabled, except QEIE) 659 * Chaining mode 660 * Disable 661 */ 662 out_be32(&priv->msg_regs->omr, 0x00100220); 663 664 /* Set number of entries */ 665 out_be32(&priv->msg_regs->omr, 666 in_be32(&priv->msg_regs->omr) | 667 ((get_bitmask_order(entries) - 2) << 12)); 668 669 /* Now enable the unit */ 670 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1); 671 672 out: 673 return rc; 674 675 out_irq: 676 dma_free_coherent(priv->dev, 677 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 678 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 679 680 out_dma: 681 for (i = 0; i < priv->msg_tx_ring.size; i++) 682 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 683 priv->msg_tx_ring.virt_buffer[i], 684 priv->msg_tx_ring.phys_buffer[i]); 685 686 return rc; 687 } 688 689 /** 690 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox 691 * @mport: Master port implementing the outbound message unit 692 * @mbox: Mailbox to close 693 * 694 * Disables the outbound message unit, free all buffers, and 695 * frees the outbound message interrupt. 696 */ 697 void rio_close_outb_mbox(struct rio_mport *mport, int mbox) 698 { 699 struct rio_priv *priv = mport->priv; 700 /* Disable inbound message unit */ 701 out_be32(&priv->msg_regs->omr, 0); 702 703 /* Free ring */ 704 dma_free_coherent(priv->dev, 705 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 706 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 707 708 /* Free interrupt */ 709 free_irq(IRQ_RIO_TX(mport), (void *)mport); 710 } 711 712 /** 713 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler 714 * @irq: Linux interrupt number 715 * @dev_instance: Pointer to interrupt-specific data 716 * 717 * Handles inbound message interrupts. Executes a registered inbound 718 * mailbox event handler and acks the interrupt occurrence. 719 */ 720 static irqreturn_t 721 fsl_rio_rx_handler(int irq, void *dev_instance) 722 { 723 int isr; 724 struct rio_mport *port = (struct rio_mport *)dev_instance; 725 struct rio_priv *priv = port->priv; 726 727 isr = in_be32(&priv->msg_regs->isr); 728 729 if (isr & RIO_MSG_ISR_TE) { 730 pr_info("RIO: inbound message reception error\n"); 731 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE); 732 goto out; 733 } 734 735 /* XXX Need to check/dispatch until queue empty */ 736 if (isr & RIO_MSG_ISR_DIQI) { 737 /* 738 * We implement *only* mailbox 0, but can receive messages 739 * for any mailbox/letter to that mailbox destination. So, 740 * make the callback with an unknown/invalid mailbox number 741 * argument. 742 */ 743 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1); 744 745 /* Ack the queueing interrupt */ 746 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI); 747 } 748 749 out: 750 return IRQ_HANDLED; 751 } 752 753 /** 754 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox 755 * @mport: Master port implementing the inbound message unit 756 * @dev_id: Device specific pointer to pass on event 757 * @mbox: Mailbox to open 758 * @entries: Number of entries in the inbound mailbox ring 759 * 760 * Initializes buffer ring, request the inbound message interrupt, 761 * and enables the inbound message unit. Returns %0 on success 762 * and %-EINVAL or %-ENOMEM on failure. 763 */ 764 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 765 { 766 int i, rc = 0; 767 struct rio_priv *priv = mport->priv; 768 769 if ((entries < RIO_MIN_RX_RING_SIZE) || 770 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { 771 rc = -EINVAL; 772 goto out; 773 } 774 775 /* Initialize client buffer ring */ 776 priv->msg_rx_ring.dev_id = dev_id; 777 priv->msg_rx_ring.size = entries; 778 priv->msg_rx_ring.rx_slot = 0; 779 for (i = 0; i < priv->msg_rx_ring.size; i++) 780 priv->msg_rx_ring.virt_buffer[i] = NULL; 781 782 /* Initialize inbound message ring */ 783 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, 784 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 785 &priv->msg_rx_ring.phys, GFP_KERNEL); 786 if (!priv->msg_rx_ring.virt) { 787 rc = -ENOMEM; 788 goto out; 789 } 790 791 /* Point dequeue/enqueue pointers at first entry in ring */ 792 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys); 793 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys); 794 795 /* Clear interrupt status */ 796 out_be32(&priv->msg_regs->isr, 0x00000091); 797 798 /* Hook up inbound message handler */ 799 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 800 "msg_rx", (void *)mport); 801 if (rc < 0) { 802 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 803 priv->msg_tx_ring.virt_buffer[i], 804 priv->msg_tx_ring.phys_buffer[i]); 805 goto out; 806 } 807 808 /* 809 * Configure inbound message unit: 810 * Snooping 811 * 4KB max message size 812 * Unmask all interrupt sources 813 * Disable 814 */ 815 out_be32(&priv->msg_regs->imr, 0x001b0060); 816 817 /* Set number of queue entries */ 818 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); 819 820 /* Now enable the unit */ 821 setbits32(&priv->msg_regs->imr, 0x1); 822 823 out: 824 return rc; 825 } 826 827 /** 828 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox 829 * @mport: Master port implementing the inbound message unit 830 * @mbox: Mailbox to close 831 * 832 * Disables the inbound message unit, free all buffers, and 833 * frees the inbound message interrupt. 834 */ 835 void rio_close_inb_mbox(struct rio_mport *mport, int mbox) 836 { 837 struct rio_priv *priv = mport->priv; 838 /* Disable inbound message unit */ 839 out_be32(&priv->msg_regs->imr, 0); 840 841 /* Free ring */ 842 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 843 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys); 844 845 /* Free interrupt */ 846 free_irq(IRQ_RIO_RX(mport), (void *)mport); 847 } 848 849 /** 850 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 851 * @mport: Master port implementing the inbound message unit 852 * @mbox: Inbound mailbox number 853 * @buf: Buffer to add to inbound queue 854 * 855 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 856 * %0 on success or %-EINVAL on failure. 857 */ 858 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 859 { 860 int rc = 0; 861 struct rio_priv *priv = mport->priv; 862 863 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 864 priv->msg_rx_ring.rx_slot); 865 866 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { 867 printk(KERN_ERR 868 "RIO: error adding inbound buffer %d, buffer exists\n", 869 priv->msg_rx_ring.rx_slot); 870 rc = -EINVAL; 871 goto out; 872 } 873 874 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf; 875 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size) 876 priv->msg_rx_ring.rx_slot = 0; 877 878 out: 879 return rc; 880 } 881 882 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer); 883 884 /** 885 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit 886 * @mport: Master port implementing the inbound message unit 887 * @mbox: Inbound mailbox number 888 * 889 * Gets the next available inbound message from the inbound message queue. 890 * A pointer to the message is returned on success or NULL on failure. 891 */ 892 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) 893 { 894 struct rio_priv *priv = mport->priv; 895 u32 phys_buf, virt_buf; 896 void *buf = NULL; 897 int buf_idx; 898 899 phys_buf = in_be32(&priv->msg_regs->ifqdpar); 900 901 /* If no more messages, then bail out */ 902 if (phys_buf == in_be32(&priv->msg_regs->ifqepar)) 903 goto out2; 904 905 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf 906 - priv->msg_rx_ring.phys); 907 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 908 buf = priv->msg_rx_ring.virt_buffer[buf_idx]; 909 910 if (!buf) { 911 printk(KERN_ERR 912 "RIO: inbound message copy failed, no buffers\n"); 913 goto out1; 914 } 915 916 /* Copy max message size, caller is expected to allocate that big */ 917 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); 918 919 /* Clear the available buffer */ 920 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL; 921 922 out1: 923 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI); 924 925 out2: 926 return buf; 927 } 928 929 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message); 930 931 /** 932 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 933 * @irq: Linux interrupt number 934 * @dev_instance: Pointer to interrupt-specific data 935 * 936 * Handles doorbell interrupts. Parses a list of registered 937 * doorbell event handlers and executes a matching event handler. 938 */ 939 static irqreturn_t 940 fsl_rio_dbell_handler(int irq, void *dev_instance) 941 { 942 int dsr; 943 struct rio_mport *port = (struct rio_mport *)dev_instance; 944 struct rio_priv *priv = port->priv; 945 946 dsr = in_be32(&priv->msg_regs->dsr); 947 948 if (dsr & DOORBELL_DSR_TE) { 949 pr_info("RIO: doorbell reception error\n"); 950 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE); 951 goto out; 952 } 953 954 if (dsr & DOORBELL_DSR_QFI) { 955 pr_info("RIO: doorbell queue full\n"); 956 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI); 957 goto out; 958 } 959 960 /* XXX Need to check/dispatch until queue empty */ 961 if (dsr & DOORBELL_DSR_DIQI) { 962 u32 dmsg = 963 (u32) priv->dbell_ring.virt + 964 (in_be32(&priv->msg_regs->dqdpar) & 0xfff); 965 struct rio_dbell *dbell; 966 int found = 0; 967 968 pr_debug 969 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", 970 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 971 972 list_for_each_entry(dbell, &port->dbells, node) { 973 if ((dbell->res->start <= DBELL_INF(dmsg)) && 974 (dbell->res->end >= DBELL_INF(dmsg))) { 975 found = 1; 976 break; 977 } 978 } 979 if (found) { 980 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), 981 DBELL_INF(dmsg)); 982 } else { 983 pr_debug 984 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", 985 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 986 } 987 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI); 988 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI); 989 } 990 991 out: 992 return IRQ_HANDLED; 993 } 994 995 /** 996 * fsl_rio_doorbell_init - MPC85xx doorbell interface init 997 * @mport: Master port implementing the inbound doorbell unit 998 * 999 * Initializes doorbell unit hardware and inbound DMA buffer 1000 * ring. Called from fsl_rio_setup(). Returns %0 on success 1001 * or %-ENOMEM on failure. 1002 */ 1003 static int fsl_rio_doorbell_init(struct rio_mport *mport) 1004 { 1005 struct rio_priv *priv = mport->priv; 1006 int rc = 0; 1007 1008 /* Map outbound doorbell window immediately after maintenance window */ 1009 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, 1010 RIO_DBELL_WIN_SIZE); 1011 if (!priv->dbell_win) { 1012 printk(KERN_ERR 1013 "RIO: unable to map outbound doorbell window\n"); 1014 rc = -ENOMEM; 1015 goto out; 1016 } 1017 1018 /* Initialize inbound doorbells */ 1019 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 * 1020 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL); 1021 if (!priv->dbell_ring.virt) { 1022 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); 1023 rc = -ENOMEM; 1024 iounmap(priv->dbell_win); 1025 goto out; 1026 } 1027 1028 /* Point dequeue/enqueue pointers at first entry in ring */ 1029 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys); 1030 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys); 1031 1032 /* Clear interrupt status */ 1033 out_be32(&priv->msg_regs->dsr, 0x00000091); 1034 1035 /* Hook up doorbell handler */ 1036 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, 1037 "dbell_rx", (void *)mport); 1038 if (rc < 0) { 1039 iounmap(priv->dbell_win); 1040 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE, 1041 priv->dbell_ring.virt, priv->dbell_ring.phys); 1042 printk(KERN_ERR 1043 "MPC85xx RIO: unable to request inbound doorbell irq"); 1044 goto out; 1045 } 1046 1047 /* Configure doorbells for snooping, 512 entries, and enable */ 1048 out_be32(&priv->msg_regs->dmr, 0x00108161); 1049 1050 out: 1051 return rc; 1052 } 1053 1054 /** 1055 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler 1056 * @irq: Linux interrupt number 1057 * @dev_instance: Pointer to interrupt-specific data 1058 * 1059 * Handles port write interrupts. Parses a list of registered 1060 * port write event handlers and executes a matching event handler. 1061 */ 1062 static irqreturn_t 1063 fsl_rio_port_write_handler(int irq, void *dev_instance) 1064 { 1065 u32 ipwmr, ipwsr; 1066 struct rio_mport *port = (struct rio_mport *)dev_instance; 1067 struct rio_priv *priv = port->priv; 1068 u32 epwisr, tmp; 1069 1070 ipwmr = in_be32(&priv->msg_regs->pwmr); 1071 ipwsr = in_be32(&priv->msg_regs->pwsr); 1072 1073 epwisr = in_be32(priv->regs_win + RIO_EPWISR); 1074 if (epwisr & 0x80000000) { 1075 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 1076 pr_info("RIO_LTLEDCSR = 0x%x\n", tmp); 1077 out_be32(priv->regs_win + RIO_LTLEDCSR, 0); 1078 } 1079 1080 if (!(epwisr & 0x00000001)) 1081 return IRQ_HANDLED; 1082 1083 #ifdef DEBUG_PW 1084 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); 1085 if (ipwsr & RIO_IPWSR_QF) 1086 pr_debug(" QF"); 1087 if (ipwsr & RIO_IPWSR_TE) 1088 pr_debug(" TE"); 1089 if (ipwsr & RIO_IPWSR_QFI) 1090 pr_debug(" QFI"); 1091 if (ipwsr & RIO_IPWSR_PWD) 1092 pr_debug(" PWD"); 1093 if (ipwsr & RIO_IPWSR_PWB) 1094 pr_debug(" PWB"); 1095 pr_debug(" )\n"); 1096 #endif 1097 out_be32(&priv->msg_regs->pwsr, 1098 ipwsr & (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); 1099 1100 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { 1101 priv->port_write_msg.err_count++; 1102 pr_info("RIO: Port-Write Transaction Err (%d)\n", 1103 priv->port_write_msg.err_count); 1104 } 1105 if (ipwsr & RIO_IPWSR_PWD) { 1106 priv->port_write_msg.discard_count++; 1107 pr_info("RIO: Port Discarded Port-Write Msg(s) (%d)\n", 1108 priv->port_write_msg.discard_count); 1109 } 1110 1111 /* Schedule deferred processing if PW was received */ 1112 if (ipwsr & RIO_IPWSR_QFI) { 1113 /* Save PW message (if there is room in FIFO), 1114 * otherwise discard it. 1115 */ 1116 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) { 1117 priv->port_write_msg.msg_count++; 1118 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt, 1119 RIO_PW_MSG_SIZE); 1120 } else { 1121 priv->port_write_msg.discard_count++; 1122 pr_info("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", 1123 priv->port_write_msg.discard_count); 1124 } 1125 schedule_work(&priv->pw_work); 1126 } 1127 1128 /* Issue Clear Queue command. This allows another 1129 * port-write to be received. 1130 */ 1131 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ); 1132 1133 return IRQ_HANDLED; 1134 } 1135 1136 static void fsl_pw_dpc(struct work_struct *work) 1137 { 1138 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work); 1139 unsigned long flags; 1140 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; 1141 1142 /* 1143 * Process port-write messages 1144 */ 1145 spin_lock_irqsave(&priv->pw_fifo_lock, flags); 1146 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer, 1147 RIO_PW_MSG_SIZE)) { 1148 /* Process one message */ 1149 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 1150 #ifdef DEBUG_PW 1151 { 1152 u32 i; 1153 pr_debug("%s : Port-Write Message:", __func__); 1154 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { 1155 if ((i%4) == 0) 1156 pr_debug("\n0x%02x: 0x%08x", i*4, 1157 msg_buffer[i]); 1158 else 1159 pr_debug(" 0x%08x", msg_buffer[i]); 1160 } 1161 pr_debug("\n"); 1162 } 1163 #endif 1164 /* Pass the port-write message to RIO core for processing */ 1165 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); 1166 spin_lock_irqsave(&priv->pw_fifo_lock, flags); 1167 } 1168 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 1169 } 1170 1171 /** 1172 * fsl_rio_pw_enable - enable/disable port-write interface init 1173 * @mport: Master port implementing the port write unit 1174 * @enable: 1=enable; 0=disable port-write message handling 1175 */ 1176 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable) 1177 { 1178 struct rio_priv *priv = mport->priv; 1179 u32 rval; 1180 1181 rval = in_be32(&priv->msg_regs->pwmr); 1182 1183 if (enable) 1184 rval |= RIO_IPWMR_PWE; 1185 else 1186 rval &= ~RIO_IPWMR_PWE; 1187 1188 out_be32(&priv->msg_regs->pwmr, rval); 1189 1190 return 0; 1191 } 1192 1193 /** 1194 * fsl_rio_port_write_init - MPC85xx port write interface init 1195 * @mport: Master port implementing the port write unit 1196 * 1197 * Initializes port write unit hardware and DMA buffer 1198 * ring. Called from fsl_rio_setup(). Returns %0 on success 1199 * or %-ENOMEM on failure. 1200 */ 1201 static int fsl_rio_port_write_init(struct rio_mport *mport) 1202 { 1203 struct rio_priv *priv = mport->priv; 1204 int rc = 0; 1205 1206 /* Following configurations require a disabled port write controller */ 1207 out_be32(&priv->msg_regs->pwmr, 1208 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE); 1209 1210 /* Initialize port write */ 1211 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev, 1212 RIO_PW_MSG_SIZE, 1213 &priv->port_write_msg.phys, GFP_KERNEL); 1214 if (!priv->port_write_msg.virt) { 1215 pr_err("RIO: unable allocate port write queue\n"); 1216 return -ENOMEM; 1217 } 1218 1219 priv->port_write_msg.err_count = 0; 1220 priv->port_write_msg.discard_count = 0; 1221 1222 /* Point dequeue/enqueue pointers at first entry */ 1223 out_be32(&priv->msg_regs->epwqbar, 0); 1224 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys); 1225 1226 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", 1227 in_be32(&priv->msg_regs->epwqbar), 1228 in_be32(&priv->msg_regs->pwqbar)); 1229 1230 /* Clear interrupt status IPWSR */ 1231 out_be32(&priv->msg_regs->pwsr, 1232 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); 1233 1234 /* Configure port write contoller for snooping enable all reporting, 1235 clear queue full */ 1236 out_be32(&priv->msg_regs->pwmr, 1237 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); 1238 1239 1240 /* Hook up port-write handler */ 1241 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0, 1242 "port-write", (void *)mport); 1243 if (rc < 0) { 1244 pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); 1245 goto err_out; 1246 } 1247 1248 INIT_WORK(&priv->pw_work, fsl_pw_dpc); 1249 spin_lock_init(&priv->pw_fifo_lock); 1250 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { 1251 pr_err("FIFO allocation failed\n"); 1252 rc = -ENOMEM; 1253 goto err_out_irq; 1254 } 1255 1256 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", 1257 in_be32(&priv->msg_regs->pwmr), 1258 in_be32(&priv->msg_regs->pwsr)); 1259 1260 return rc; 1261 1262 err_out_irq: 1263 free_irq(IRQ_RIO_PW(mport), (void *)mport); 1264 err_out: 1265 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE, 1266 priv->port_write_msg.virt, 1267 priv->port_write_msg.phys); 1268 return rc; 1269 } 1270 1271 static char *cmdline = NULL; 1272 1273 static int fsl_rio_get_hdid(int index) 1274 { 1275 /* XXX Need to parse multiple entries in some format */ 1276 if (!cmdline) 1277 return -1; 1278 1279 return simple_strtol(cmdline, NULL, 0); 1280 } 1281 1282 static int fsl_rio_get_cmdline(char *s) 1283 { 1284 if (!s) 1285 return 0; 1286 1287 cmdline = s; 1288 return 1; 1289 } 1290 1291 __setup("riohdid=", fsl_rio_get_cmdline); 1292 1293 static inline void fsl_rio_info(struct device *dev, u32 ccsr) 1294 { 1295 const char *str; 1296 if (ccsr & 1) { 1297 /* Serial phy */ 1298 switch (ccsr >> 30) { 1299 case 0: 1300 str = "1"; 1301 break; 1302 case 1: 1303 str = "4"; 1304 break; 1305 default: 1306 str = "Unknown"; 1307 break; 1308 } 1309 dev_info(dev, "Hardware port width: %s\n", str); 1310 1311 switch ((ccsr >> 27) & 7) { 1312 case 0: 1313 str = "Single-lane 0"; 1314 break; 1315 case 1: 1316 str = "Single-lane 2"; 1317 break; 1318 case 2: 1319 str = "Four-lane"; 1320 break; 1321 default: 1322 str = "Unknown"; 1323 break; 1324 } 1325 dev_info(dev, "Training connection status: %s\n", str); 1326 } else { 1327 /* Parallel phy */ 1328 if (!(ccsr & 0x80000000)) 1329 dev_info(dev, "Output port operating in 8-bit mode\n"); 1330 if (!(ccsr & 0x08000000)) 1331 dev_info(dev, "Input port operating in 8-bit mode\n"); 1332 } 1333 } 1334 1335 /** 1336 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface 1337 * @dev: platform_device pointer 1338 * 1339 * Initializes MPC85xx RapidIO hardware interface, configures 1340 * master port with system-specific info, and registers the 1341 * master port with the RapidIO subsystem. 1342 */ 1343 int fsl_rio_setup(struct platform_device *dev) 1344 { 1345 struct rio_ops *ops; 1346 struct rio_mport *port; 1347 struct rio_priv *priv; 1348 int rc = 0; 1349 const u32 *dt_range, *cell; 1350 struct resource regs; 1351 int rlen; 1352 u32 ccsr; 1353 u64 law_start, law_size; 1354 int paw, aw, sw; 1355 1356 if (!dev->dev.of_node) { 1357 dev_err(&dev->dev, "Device OF-Node is NULL"); 1358 return -EFAULT; 1359 } 1360 1361 rc = of_address_to_resource(dev->dev.of_node, 0, ®s); 1362 if (rc) { 1363 dev_err(&dev->dev, "Can't get %s property 'reg'\n", 1364 dev->dev.of_node->full_name); 1365 return -EFAULT; 1366 } 1367 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); 1368 dev_info(&dev->dev, "Regs: %pR\n", ®s); 1369 1370 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); 1371 if (!dt_range) { 1372 dev_err(&dev->dev, "Can't get %s property 'ranges'\n", 1373 dev->dev.of_node->full_name); 1374 return -EFAULT; 1375 } 1376 1377 /* Get node address wide */ 1378 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL); 1379 if (cell) 1380 aw = *cell; 1381 else 1382 aw = of_n_addr_cells(dev->dev.of_node); 1383 /* Get node size wide */ 1384 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL); 1385 if (cell) 1386 sw = *cell; 1387 else 1388 sw = of_n_size_cells(dev->dev.of_node); 1389 /* Get parent address wide wide */ 1390 paw = of_n_addr_cells(dev->dev.of_node); 1391 1392 law_start = of_read_number(dt_range + aw, paw); 1393 law_size = of_read_number(dt_range + aw + paw, sw); 1394 1395 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n", 1396 law_start, law_size); 1397 1398 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); 1399 if (!ops) { 1400 rc = -ENOMEM; 1401 goto err_ops; 1402 } 1403 ops->lcread = fsl_local_config_read; 1404 ops->lcwrite = fsl_local_config_write; 1405 ops->cread = fsl_rio_config_read; 1406 ops->cwrite = fsl_rio_config_write; 1407 ops->dsend = fsl_rio_doorbell_send; 1408 ops->pwenable = fsl_rio_pw_enable; 1409 1410 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 1411 if (!port) { 1412 rc = -ENOMEM; 1413 goto err_port; 1414 } 1415 port->id = 0; 1416 port->index = 0; 1417 1418 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); 1419 if (!priv) { 1420 printk(KERN_ERR "Can't alloc memory for 'priv'\n"); 1421 rc = -ENOMEM; 1422 goto err_priv; 1423 } 1424 1425 INIT_LIST_HEAD(&port->dbells); 1426 port->iores.start = law_start; 1427 port->iores.end = law_start + law_size - 1; 1428 port->iores.flags = IORESOURCE_MEM; 1429 port->iores.name = "rio_io_win"; 1430 1431 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 1432 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 1433 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); 1434 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); 1435 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n", 1436 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq); 1437 1438 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 1439 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 1440 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 1441 strcpy(port->name, "RIO0 mport"); 1442 1443 priv->dev = &dev->dev; 1444 1445 port->ops = ops; 1446 port->host_deviceid = fsl_rio_get_hdid(port->id); 1447 1448 port->priv = priv; 1449 rio_register_mport(port); 1450 1451 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); 1452 rio_regs_win = priv->regs_win; 1453 1454 /* Probe the master port phy type */ 1455 ccsr = in_be32(priv->regs_win + RIO_CCSR); 1456 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; 1457 dev_info(&dev->dev, "RapidIO PHY type: %s\n", 1458 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" : 1459 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" : 1460 "unknown")); 1461 /* Checking the port training status */ 1462 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 1463 dev_err(&dev->dev, "Port is not ready. " 1464 "Try to restart connection...\n"); 1465 switch (port->phy_type) { 1466 case RIO_PHY_SERIAL: 1467 /* Disable ports */ 1468 out_be32(priv->regs_win + RIO_CCSR, 0); 1469 /* Set 1x lane */ 1470 setbits32(priv->regs_win + RIO_CCSR, 0x02000000); 1471 /* Enable ports */ 1472 setbits32(priv->regs_win + RIO_CCSR, 0x00600000); 1473 break; 1474 case RIO_PHY_PARALLEL: 1475 /* Disable ports */ 1476 out_be32(priv->regs_win + RIO_CCSR, 0x22000000); 1477 /* Enable ports */ 1478 out_be32(priv->regs_win + RIO_CCSR, 0x44000000); 1479 break; 1480 } 1481 msleep(100); 1482 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 1483 dev_err(&dev->dev, "Port restart failed.\n"); 1484 rc = -ENOLINK; 1485 goto err; 1486 } 1487 dev_info(&dev->dev, "Port restart success!\n"); 1488 } 1489 fsl_rio_info(&dev->dev, ccsr); 1490 1491 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 1492 & RIO_PEF_CTLS) >> 4; 1493 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 1494 port->sys_size ? 65536 : 256); 1495 1496 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 1497 + RIO_ATMU_REGS_OFFSET); 1498 priv->maint_atmu_regs = priv->atmu_regs + 1; 1499 priv->dbell_atmu_regs = priv->atmu_regs + 2; 1500 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + 1501 ((port->phy_type == RIO_PHY_SERIAL) ? 1502 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); 1503 1504 /* Set to receive any dist ID for serial RapidIO controller. */ 1505 if (port->phy_type == RIO_PHY_SERIAL) 1506 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); 1507 1508 /* Configure maintenance transaction window */ 1509 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12); 1510 out_be32(&priv->maint_atmu_regs->rowar, 1511 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); 1512 1513 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); 1514 1515 /* Configure outbound doorbell window */ 1516 out_be32(&priv->dbell_atmu_regs->rowbar, 1517 (law_start + RIO_MAINT_WIN_SIZE) >> 12); 1518 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ 1519 fsl_rio_doorbell_init(port); 1520 fsl_rio_port_write_init(port); 1521 1522 #ifdef CONFIG_E500 1523 saved_mcheck_exception = ppc_md.machine_check_exception; 1524 ppc_md.machine_check_exception = fsl_rio_mcheck_exception; 1525 #endif 1526 /* Ensure that RFXE is set */ 1527 mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000)); 1528 1529 return 0; 1530 err: 1531 iounmap(priv->regs_win); 1532 kfree(priv); 1533 err_priv: 1534 kfree(port); 1535 err_port: 1536 kfree(ops); 1537 err_ops: 1538 return rc; 1539 } 1540 1541 /* The probe function for RapidIO peer-to-peer network. 1542 */ 1543 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev, 1544 const struct of_device_id *match) 1545 { 1546 int rc; 1547 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", 1548 dev->dev.of_node->full_name); 1549 1550 rc = fsl_rio_setup(dev); 1551 if (rc) 1552 goto out; 1553 1554 /* Enumerate all registered ports */ 1555 rc = rio_init_mports(); 1556 out: 1557 return rc; 1558 }; 1559 1560 static const struct of_device_id fsl_of_rio_rpn_ids[] = { 1561 { 1562 .compatible = "fsl,rapidio-delta", 1563 }, 1564 {}, 1565 }; 1566 1567 static struct of_platform_driver fsl_of_rio_rpn_driver = { 1568 .driver = { 1569 .name = "fsl-of-rio", 1570 .owner = THIS_MODULE, 1571 .of_match_table = fsl_of_rio_rpn_ids, 1572 }, 1573 .probe = fsl_of_rio_rpn_probe, 1574 }; 1575 1576 static __init int fsl_of_rio_rpn_init(void) 1577 { 1578 return of_register_platform_driver(&fsl_of_rio_rpn_driver); 1579 } 1580 1581 subsys_initcall(fsl_of_rio_rpn_init); 1582