1 /* 2 * Freescale MPC85xx/MPC86xx RapidIO support 3 * 4 * Copyright 2009 Sysgo AG 5 * Thomas Moll <thomas.moll@sysgo.com> 6 * - fixed maintenance access routines, check for aligned access 7 * 8 * Copyright 2009 Integrated Device Technology, Inc. 9 * Alex Bounine <alexandre.bounine@idt.com> 10 * - Added Port-Write message handling 11 * - Added Machine Check exception handling 12 * 13 * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc. 14 * Zhang Wei <wei.zhang@freescale.com> 15 * 16 * Copyright 2005 MontaVista Software, Inc. 17 * Matt Porter <mporter@kernel.crashing.org> 18 * 19 * This program is free software; you can redistribute it and/or modify it 20 * under the terms of the GNU General Public License as published by the 21 * Free Software Foundation; either version 2 of the License, or (at your 22 * option) any later version. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/interrupt.h> 30 #include <linux/device.h> 31 #include <linux/rio.h> 32 #include <linux/rio_drv.h> 33 #include <linux/of_platform.h> 34 #include <linux/delay.h> 35 #include <linux/slab.h> 36 #include <linux/kfifo.h> 37 38 #include <asm/io.h> 39 #include <asm/machdep.h> 40 #include <asm/uaccess.h> 41 42 #undef DEBUG_PW /* Port-Write debugging */ 43 44 /* RapidIO definition irq, which read from OF-tree */ 45 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) 46 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) 47 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) 48 #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) 49 50 #define IPWSR_CLEAR 0x98 51 #define OMSR_CLEAR 0x1cb3 52 #define IMSR_CLEAR 0x491 53 #define IDSR_CLEAR 0x91 54 #define ODSR_CLEAR 0x1c00 55 #define LTLEECSR_ENABLE_ALL 0xFFC000FC 56 #define ESCSR_CLEAR 0x07120204 57 58 #define RIO_PORT1_EDCSR 0x0640 59 #define RIO_PORT2_EDCSR 0x0680 60 #define RIO_PORT1_IECSR 0x10130 61 #define RIO_PORT2_IECSR 0x101B0 62 #define RIO_IM0SR 0x13064 63 #define RIO_IM1SR 0x13164 64 #define RIO_OM0SR 0x13004 65 #define RIO_OM1SR 0x13104 66 67 #define RIO_ATMU_REGS_OFFSET 0x10c00 68 #define RIO_P_MSG_REGS_OFFSET 0x11000 69 #define RIO_S_MSG_REGS_OFFSET 0x13000 70 #define RIO_GCCSR 0x13c 71 #define RIO_ESCSR 0x158 72 #define RIO_PORT2_ESCSR 0x178 73 #define RIO_CCSR 0x15c 74 #define RIO_LTLEDCSR 0x0608 75 #define RIO_LTLEDCSR_IER 0x80000000 76 #define RIO_LTLEDCSR_PRT 0x01000000 77 #define RIO_LTLEECSR 0x060c 78 #define RIO_EPWISR 0x10010 79 #define RIO_ISR_AACR 0x10120 80 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 81 #define RIO_MAINT_WIN_SIZE 0x400000 82 #define RIO_DBELL_WIN_SIZE 0x1000 83 84 #define RIO_MSG_OMR_MUI 0x00000002 85 #define RIO_MSG_OSR_TE 0x00000080 86 #define RIO_MSG_OSR_QOI 0x00000020 87 #define RIO_MSG_OSR_QFI 0x00000010 88 #define RIO_MSG_OSR_MUB 0x00000004 89 #define RIO_MSG_OSR_EOMI 0x00000002 90 #define RIO_MSG_OSR_QEI 0x00000001 91 92 #define RIO_MSG_IMR_MI 0x00000002 93 #define RIO_MSG_ISR_TE 0x00000080 94 #define RIO_MSG_ISR_QFI 0x00000010 95 #define RIO_MSG_ISR_DIQI 0x00000001 96 97 #define RIO_IPWMR_SEN 0x00100000 98 #define RIO_IPWMR_QFIE 0x00000100 99 #define RIO_IPWMR_EIE 0x00000020 100 #define RIO_IPWMR_CQ 0x00000002 101 #define RIO_IPWMR_PWE 0x00000001 102 103 #define RIO_IPWSR_QF 0x00100000 104 #define RIO_IPWSR_TE 0x00000080 105 #define RIO_IPWSR_QFI 0x00000010 106 #define RIO_IPWSR_PWD 0x00000008 107 #define RIO_IPWSR_PWB 0x00000004 108 109 /* EPWISR Error match value */ 110 #define RIO_EPWISR_PINT1 0x80000000 111 #define RIO_EPWISR_PINT2 0x40000000 112 #define RIO_EPWISR_MU 0x00000002 113 #define RIO_EPWISR_PW 0x00000001 114 115 #define RIO_MSG_DESC_SIZE 32 116 #define RIO_MSG_BUFFER_SIZE 4096 117 #define RIO_MIN_TX_RING_SIZE 2 118 #define RIO_MAX_TX_RING_SIZE 2048 119 #define RIO_MIN_RX_RING_SIZE 2 120 #define RIO_MAX_RX_RING_SIZE 2048 121 122 #define DOORBELL_DMR_DI 0x00000002 123 #define DOORBELL_DSR_TE 0x00000080 124 #define DOORBELL_DSR_QFI 0x00000010 125 #define DOORBELL_DSR_DIQI 0x00000001 126 #define DOORBELL_TID_OFFSET 0x02 127 #define DOORBELL_SID_OFFSET 0x04 128 #define DOORBELL_INFO_OFFSET 0x06 129 130 #define DOORBELL_MESSAGE_SIZE 0x08 131 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) 132 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) 133 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) 134 135 struct rio_atmu_regs { 136 u32 rowtar; 137 u32 rowtear; 138 u32 rowbar; 139 u32 pad2; 140 u32 rowar; 141 u32 pad3[3]; 142 }; 143 144 struct rio_msg_regs { 145 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */ 146 u32 osr; /* 0xD_3004 - Outbound message 0 status register */ 147 u32 pad1; 148 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue 149 dequeue pointer address register */ 150 u32 pad2; 151 u32 osar; /* 0xD_3014 - Outbound message 0 source address 152 register */ 153 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port 154 register */ 155 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes 156 Register*/ 157 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count 158 register */ 159 u32 pad3; 160 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue 161 enqueue pointer address register */ 162 u32 pad4[13]; 163 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */ 164 u32 isr; /* 0xD_3064 - Inbound message 0 status register */ 165 u32 pad5; 166 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue 167 pointer address register*/ 168 u32 pad6; 169 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue 170 pointer address register */ 171 u32 pad7[226]; 172 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */ 173 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */ 174 u32 res0[4]; 175 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port 176 register */ 177 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes 178 register */ 179 u32 res1[3]; 180 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold 181 configuration register */ 182 u32 res2[12]; 183 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */ 184 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */ 185 u32 pad8; 186 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer 187 address register */ 188 u32 pad9; 189 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer 190 address register */ 191 u32 pad10[26]; 192 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */ 193 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */ 194 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address 195 register */ 196 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address 197 register */ 198 }; 199 200 struct rio_tx_desc { 201 u32 res1; 202 u32 saddr; 203 u32 dport; 204 u32 dattr; 205 u32 res2; 206 u32 res3; 207 u32 dwcnt; 208 u32 res4; 209 }; 210 211 struct rio_dbell_ring { 212 void *virt; 213 dma_addr_t phys; 214 }; 215 216 struct rio_msg_tx_ring { 217 void *virt; 218 dma_addr_t phys; 219 void *virt_buffer[RIO_MAX_TX_RING_SIZE]; 220 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; 221 int tx_slot; 222 int size; 223 void *dev_id; 224 }; 225 226 struct rio_msg_rx_ring { 227 void *virt; 228 dma_addr_t phys; 229 void *virt_buffer[RIO_MAX_RX_RING_SIZE]; 230 int rx_slot; 231 int size; 232 void *dev_id; 233 }; 234 235 struct rio_port_write_msg { 236 void *virt; 237 dma_addr_t phys; 238 u32 msg_count; 239 u32 err_count; 240 u32 discard_count; 241 }; 242 243 struct rio_priv { 244 struct device *dev; 245 void __iomem *regs_win; 246 struct rio_atmu_regs __iomem *atmu_regs; 247 struct rio_atmu_regs __iomem *maint_atmu_regs; 248 struct rio_atmu_regs __iomem *dbell_atmu_regs; 249 void __iomem *dbell_win; 250 void __iomem *maint_win; 251 struct rio_msg_regs __iomem *msg_regs; 252 struct rio_dbell_ring dbell_ring; 253 struct rio_msg_tx_ring msg_tx_ring; 254 struct rio_msg_rx_ring msg_rx_ring; 255 struct rio_port_write_msg port_write_msg; 256 int bellirq; 257 int txirq; 258 int rxirq; 259 int pwirq; 260 struct work_struct pw_work; 261 struct kfifo pw_fifo; 262 spinlock_t pw_fifo_lock; 263 }; 264 265 #define __fsl_read_rio_config(x, addr, err, op) \ 266 __asm__ __volatile__( \ 267 "1: "op" %1,0(%2)\n" \ 268 " eieio\n" \ 269 "2:\n" \ 270 ".section .fixup,\"ax\"\n" \ 271 "3: li %1,-1\n" \ 272 " li %0,%3\n" \ 273 " b 2b\n" \ 274 ".section __ex_table,\"a\"\n" \ 275 " .align 2\n" \ 276 " .long 1b,3b\n" \ 277 ".text" \ 278 : "=r" (err), "=r" (x) \ 279 : "b" (addr), "i" (-EFAULT), "0" (err)) 280 281 static void __iomem *rio_regs_win; 282 283 #ifdef CONFIG_E500 284 int fsl_rio_mcheck_exception(struct pt_regs *regs) 285 { 286 const struct exception_table_entry *entry = NULL; 287 unsigned long reason = mfspr(SPRN_MCSR); 288 289 if (reason & MCSR_BUS_RBERR) { 290 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR)); 291 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) { 292 /* Check if we are prepared to handle this fault */ 293 entry = search_exception_tables(regs->nip); 294 if (entry) { 295 pr_debug("RIO: %s - MC Exception handled\n", 296 __func__); 297 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 298 0); 299 regs->msr |= MSR_RI; 300 regs->nip = entry->fixup; 301 return 1; 302 } 303 } 304 } 305 306 return 0; 307 } 308 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception); 309 #endif 310 311 /** 312 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message 313 * @mport: RapidIO master port info 314 * @index: ID of RapidIO interface 315 * @destid: Destination ID of target device 316 * @data: 16-bit info field of RapidIO doorbell message 317 * 318 * Sends a MPC85xx doorbell message. Returns %0 on success or 319 * %-EINVAL on failure. 320 */ 321 static int fsl_rio_doorbell_send(struct rio_mport *mport, 322 int index, u16 destid, u16 data) 323 { 324 struct rio_priv *priv = mport->priv; 325 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", 326 index, destid, data); 327 switch (mport->phy_type) { 328 case RIO_PHY_PARALLEL: 329 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22); 330 out_be16(priv->dbell_win, data); 331 break; 332 case RIO_PHY_SERIAL: 333 /* In the serial version silicons, such as MPC8548, MPC8641, 334 * below operations is must be. 335 */ 336 out_be32(&priv->msg_regs->odmr, 0x00000000); 337 out_be32(&priv->msg_regs->odretcr, 0x00000004); 338 out_be32(&priv->msg_regs->oddpr, destid << 16); 339 out_be32(&priv->msg_regs->oddatr, data); 340 out_be32(&priv->msg_regs->odmr, 0x00000001); 341 break; 342 } 343 344 return 0; 345 } 346 347 /** 348 * fsl_local_config_read - Generate a MPC85xx local config space read 349 * @mport: RapidIO master port info 350 * @index: ID of RapdiIO interface 351 * @offset: Offset into configuration space 352 * @len: Length (in bytes) of the maintenance transaction 353 * @data: Value to be read into 354 * 355 * Generates a MPC85xx local configuration space read. Returns %0 on 356 * success or %-EINVAL on failure. 357 */ 358 static int fsl_local_config_read(struct rio_mport *mport, 359 int index, u32 offset, int len, u32 *data) 360 { 361 struct rio_priv *priv = mport->priv; 362 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, 363 offset); 364 *data = in_be32(priv->regs_win + offset); 365 366 return 0; 367 } 368 369 /** 370 * fsl_local_config_write - Generate a MPC85xx local config space write 371 * @mport: RapidIO master port info 372 * @index: ID of RapdiIO interface 373 * @offset: Offset into configuration space 374 * @len: Length (in bytes) of the maintenance transaction 375 * @data: Value to be written 376 * 377 * Generates a MPC85xx local configuration space write. Returns %0 on 378 * success or %-EINVAL on failure. 379 */ 380 static int fsl_local_config_write(struct rio_mport *mport, 381 int index, u32 offset, int len, u32 data) 382 { 383 struct rio_priv *priv = mport->priv; 384 pr_debug 385 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 386 index, offset, data); 387 out_be32(priv->regs_win + offset, data); 388 389 return 0; 390 } 391 392 /** 393 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction 394 * @mport: RapidIO master port info 395 * @index: ID of RapdiIO interface 396 * @destid: Destination ID of transaction 397 * @hopcount: Number of hops to target device 398 * @offset: Offset into configuration space 399 * @len: Length (in bytes) of the maintenance transaction 400 * @val: Location to be read into 401 * 402 * Generates a MPC85xx read maintenance transaction. Returns %0 on 403 * success or %-EINVAL on failure. 404 */ 405 static int 406 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, 407 u8 hopcount, u32 offset, int len, u32 *val) 408 { 409 struct rio_priv *priv = mport->priv; 410 u8 *data; 411 u32 rval, err = 0; 412 413 pr_debug 414 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", 415 index, destid, hopcount, offset, len); 416 417 /* 16MB maintenance window possible */ 418 /* allow only aligned access to maintenance registers */ 419 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) 420 return -EINVAL; 421 422 out_be32(&priv->maint_atmu_regs->rowtar, 423 (destid << 22) | (hopcount << 12) | (offset >> 12)); 424 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 425 426 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 427 switch (len) { 428 case 1: 429 __fsl_read_rio_config(rval, data, err, "lbz"); 430 break; 431 case 2: 432 __fsl_read_rio_config(rval, data, err, "lhz"); 433 break; 434 case 4: 435 __fsl_read_rio_config(rval, data, err, "lwz"); 436 break; 437 default: 438 return -EINVAL; 439 } 440 441 if (err) { 442 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n", 443 err, destid, hopcount, offset); 444 } 445 446 *val = rval; 447 448 return err; 449 } 450 451 /** 452 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction 453 * @mport: RapidIO master port info 454 * @index: ID of RapdiIO interface 455 * @destid: Destination ID of transaction 456 * @hopcount: Number of hops to target device 457 * @offset: Offset into configuration space 458 * @len: Length (in bytes) of the maintenance transaction 459 * @val: Value to be written 460 * 461 * Generates an MPC85xx write maintenance transaction. Returns %0 on 462 * success or %-EINVAL on failure. 463 */ 464 static int 465 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, 466 u8 hopcount, u32 offset, int len, u32 val) 467 { 468 struct rio_priv *priv = mport->priv; 469 u8 *data; 470 pr_debug 471 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 472 index, destid, hopcount, offset, len, val); 473 474 /* 16MB maintenance windows possible */ 475 /* allow only aligned access to maintenance registers */ 476 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) 477 return -EINVAL; 478 479 out_be32(&priv->maint_atmu_regs->rowtar, 480 (destid << 22) | (hopcount << 12) | (offset >> 12)); 481 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 482 483 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 484 switch (len) { 485 case 1: 486 out_8((u8 *) data, val); 487 break; 488 case 2: 489 out_be16((u16 *) data, val); 490 break; 491 case 4: 492 out_be32((u32 *) data, val); 493 break; 494 default: 495 return -EINVAL; 496 } 497 498 return 0; 499 } 500 501 /** 502 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue 503 * @mport: Master port with outbound message queue 504 * @rdev: Target of outbound message 505 * @mbox: Outbound mailbox 506 * @buffer: Message to add to outbound queue 507 * @len: Length of message 508 * 509 * Adds the @buffer message to the MPC85xx outbound message queue. Returns 510 * %0 on success or %-EINVAL on failure. 511 */ 512 static int 513 fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 514 void *buffer, size_t len) 515 { 516 struct rio_priv *priv = mport->priv; 517 u32 omr; 518 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt 519 + priv->msg_tx_ring.tx_slot; 520 int ret = 0; 521 522 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ 523 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); 524 525 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 526 ret = -EINVAL; 527 goto out; 528 } 529 530 /* Copy and clear rest of buffer */ 531 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer, 532 len); 533 if (len < (RIO_MAX_MSG_SIZE - 4)) 534 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot] 535 + len, 0, RIO_MAX_MSG_SIZE - len); 536 537 switch (mport->phy_type) { 538 case RIO_PHY_PARALLEL: 539 /* Set mbox field for message */ 540 desc->dport = mbox & 0x3; 541 542 /* Enable EOMI interrupt, set priority, and set destid */ 543 desc->dattr = 0x28000000 | (rdev->destid << 2); 544 break; 545 case RIO_PHY_SERIAL: 546 /* Set mbox field for message, and set destid */ 547 desc->dport = (rdev->destid << 16) | (mbox & 0x3); 548 549 /* Enable EOMI interrupt and priority */ 550 desc->dattr = 0x28000000; 551 break; 552 } 553 554 /* Set transfer size aligned to next power of 2 (in double words) */ 555 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); 556 557 /* Set snooping and source buffer address */ 558 desc->saddr = 0x00000004 559 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot]; 560 561 /* Increment enqueue pointer */ 562 omr = in_be32(&priv->msg_regs->omr); 563 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI); 564 565 /* Go to next descriptor */ 566 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size) 567 priv->msg_tx_ring.tx_slot = 0; 568 569 out: 570 return ret; 571 } 572 573 /** 574 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 575 * @irq: Linux interrupt number 576 * @dev_instance: Pointer to interrupt-specific data 577 * 578 * Handles outbound message interrupts. Executes a register outbound 579 * mailbox event handler and acks the interrupt occurrence. 580 */ 581 static irqreturn_t 582 fsl_rio_tx_handler(int irq, void *dev_instance) 583 { 584 int osr; 585 struct rio_mport *port = (struct rio_mport *)dev_instance; 586 struct rio_priv *priv = port->priv; 587 588 osr = in_be32(&priv->msg_regs->osr); 589 590 if (osr & RIO_MSG_OSR_TE) { 591 pr_info("RIO: outbound message transmission error\n"); 592 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE); 593 goto out; 594 } 595 596 if (osr & RIO_MSG_OSR_QOI) { 597 pr_info("RIO: outbound message queue overflow\n"); 598 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI); 599 goto out; 600 } 601 602 if (osr & RIO_MSG_OSR_EOMI) { 603 u32 dqp = in_be32(&priv->msg_regs->odqdpar); 604 int slot = (dqp - priv->msg_tx_ring.phys) >> 5; 605 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1, 606 slot); 607 608 /* Ack the end-of-message interrupt */ 609 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI); 610 } 611 612 out: 613 return IRQ_HANDLED; 614 } 615 616 /** 617 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox 618 * @mport: Master port implementing the outbound message unit 619 * @dev_id: Device specific pointer to pass on event 620 * @mbox: Mailbox to open 621 * @entries: Number of entries in the outbound mailbox ring 622 * 623 * Initializes buffer ring, request the outbound message interrupt, 624 * and enables the outbound message unit. Returns %0 on success and 625 * %-EINVAL or %-ENOMEM on failure. 626 */ 627 static int 628 fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 629 { 630 int i, j, rc = 0; 631 struct rio_priv *priv = mport->priv; 632 633 if ((entries < RIO_MIN_TX_RING_SIZE) || 634 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { 635 rc = -EINVAL; 636 goto out; 637 } 638 639 /* Initialize shadow copy ring */ 640 priv->msg_tx_ring.dev_id = dev_id; 641 priv->msg_tx_ring.size = entries; 642 643 for (i = 0; i < priv->msg_tx_ring.size; i++) { 644 priv->msg_tx_ring.virt_buffer[i] = 645 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 646 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL); 647 if (!priv->msg_tx_ring.virt_buffer[i]) { 648 rc = -ENOMEM; 649 for (j = 0; j < priv->msg_tx_ring.size; j++) 650 if (priv->msg_tx_ring.virt_buffer[j]) 651 dma_free_coherent(priv->dev, 652 RIO_MSG_BUFFER_SIZE, 653 priv->msg_tx_ring. 654 virt_buffer[j], 655 priv->msg_tx_ring. 656 phys_buffer[j]); 657 goto out; 658 } 659 } 660 661 /* Initialize outbound message descriptor ring */ 662 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, 663 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 664 &priv->msg_tx_ring.phys, GFP_KERNEL); 665 if (!priv->msg_tx_ring.virt) { 666 rc = -ENOMEM; 667 goto out_dma; 668 } 669 memset(priv->msg_tx_ring.virt, 0, 670 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE); 671 priv->msg_tx_ring.tx_slot = 0; 672 673 /* Point dequeue/enqueue pointers at first entry in ring */ 674 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys); 675 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys); 676 677 /* Configure for snooping */ 678 out_be32(&priv->msg_regs->osar, 0x00000004); 679 680 /* Clear interrupt status */ 681 out_be32(&priv->msg_regs->osr, 0x000000b3); 682 683 /* Hook up outbound message handler */ 684 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, 685 "msg_tx", (void *)mport); 686 if (rc < 0) 687 goto out_irq; 688 689 /* 690 * Configure outbound message unit 691 * Snooping 692 * Interrupts (all enabled, except QEIE) 693 * Chaining mode 694 * Disable 695 */ 696 out_be32(&priv->msg_regs->omr, 0x00100220); 697 698 /* Set number of entries */ 699 out_be32(&priv->msg_regs->omr, 700 in_be32(&priv->msg_regs->omr) | 701 ((get_bitmask_order(entries) - 2) << 12)); 702 703 /* Now enable the unit */ 704 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1); 705 706 out: 707 return rc; 708 709 out_irq: 710 dma_free_coherent(priv->dev, 711 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 712 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 713 714 out_dma: 715 for (i = 0; i < priv->msg_tx_ring.size; i++) 716 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 717 priv->msg_tx_ring.virt_buffer[i], 718 priv->msg_tx_ring.phys_buffer[i]); 719 720 return rc; 721 } 722 723 /** 724 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox 725 * @mport: Master port implementing the outbound message unit 726 * @mbox: Mailbox to close 727 * 728 * Disables the outbound message unit, free all buffers, and 729 * frees the outbound message interrupt. 730 */ 731 static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) 732 { 733 struct rio_priv *priv = mport->priv; 734 /* Disable inbound message unit */ 735 out_be32(&priv->msg_regs->omr, 0); 736 737 /* Free ring */ 738 dma_free_coherent(priv->dev, 739 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 740 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 741 742 /* Free interrupt */ 743 free_irq(IRQ_RIO_TX(mport), (void *)mport); 744 } 745 746 /** 747 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler 748 * @irq: Linux interrupt number 749 * @dev_instance: Pointer to interrupt-specific data 750 * 751 * Handles inbound message interrupts. Executes a registered inbound 752 * mailbox event handler and acks the interrupt occurrence. 753 */ 754 static irqreturn_t 755 fsl_rio_rx_handler(int irq, void *dev_instance) 756 { 757 int isr; 758 struct rio_mport *port = (struct rio_mport *)dev_instance; 759 struct rio_priv *priv = port->priv; 760 761 isr = in_be32(&priv->msg_regs->isr); 762 763 if (isr & RIO_MSG_ISR_TE) { 764 pr_info("RIO: inbound message reception error\n"); 765 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE); 766 goto out; 767 } 768 769 /* XXX Need to check/dispatch until queue empty */ 770 if (isr & RIO_MSG_ISR_DIQI) { 771 /* 772 * We implement *only* mailbox 0, but can receive messages 773 * for any mailbox/letter to that mailbox destination. So, 774 * make the callback with an unknown/invalid mailbox number 775 * argument. 776 */ 777 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1); 778 779 /* Ack the queueing interrupt */ 780 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI); 781 } 782 783 out: 784 return IRQ_HANDLED; 785 } 786 787 /** 788 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox 789 * @mport: Master port implementing the inbound message unit 790 * @dev_id: Device specific pointer to pass on event 791 * @mbox: Mailbox to open 792 * @entries: Number of entries in the inbound mailbox ring 793 * 794 * Initializes buffer ring, request the inbound message interrupt, 795 * and enables the inbound message unit. Returns %0 on success 796 * and %-EINVAL or %-ENOMEM on failure. 797 */ 798 static int 799 fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 800 { 801 int i, rc = 0; 802 struct rio_priv *priv = mport->priv; 803 804 if ((entries < RIO_MIN_RX_RING_SIZE) || 805 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { 806 rc = -EINVAL; 807 goto out; 808 } 809 810 /* Initialize client buffer ring */ 811 priv->msg_rx_ring.dev_id = dev_id; 812 priv->msg_rx_ring.size = entries; 813 priv->msg_rx_ring.rx_slot = 0; 814 for (i = 0; i < priv->msg_rx_ring.size; i++) 815 priv->msg_rx_ring.virt_buffer[i] = NULL; 816 817 /* Initialize inbound message ring */ 818 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, 819 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 820 &priv->msg_rx_ring.phys, GFP_KERNEL); 821 if (!priv->msg_rx_ring.virt) { 822 rc = -ENOMEM; 823 goto out; 824 } 825 826 /* Point dequeue/enqueue pointers at first entry in ring */ 827 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys); 828 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys); 829 830 /* Clear interrupt status */ 831 out_be32(&priv->msg_regs->isr, 0x00000091); 832 833 /* Hook up inbound message handler */ 834 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 835 "msg_rx", (void *)mport); 836 if (rc < 0) { 837 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 838 priv->msg_tx_ring.virt_buffer[i], 839 priv->msg_tx_ring.phys_buffer[i]); 840 goto out; 841 } 842 843 /* 844 * Configure inbound message unit: 845 * Snooping 846 * 4KB max message size 847 * Unmask all interrupt sources 848 * Disable 849 */ 850 out_be32(&priv->msg_regs->imr, 0x001b0060); 851 852 /* Set number of queue entries */ 853 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); 854 855 /* Now enable the unit */ 856 setbits32(&priv->msg_regs->imr, 0x1); 857 858 out: 859 return rc; 860 } 861 862 /** 863 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox 864 * @mport: Master port implementing the inbound message unit 865 * @mbox: Mailbox to close 866 * 867 * Disables the inbound message unit, free all buffers, and 868 * frees the inbound message interrupt. 869 */ 870 static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) 871 { 872 struct rio_priv *priv = mport->priv; 873 /* Disable inbound message unit */ 874 out_be32(&priv->msg_regs->imr, 0); 875 876 /* Free ring */ 877 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 878 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys); 879 880 /* Free interrupt */ 881 free_irq(IRQ_RIO_RX(mport), (void *)mport); 882 } 883 884 /** 885 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 886 * @mport: Master port implementing the inbound message unit 887 * @mbox: Inbound mailbox number 888 * @buf: Buffer to add to inbound queue 889 * 890 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 891 * %0 on success or %-EINVAL on failure. 892 */ 893 static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 894 { 895 int rc = 0; 896 struct rio_priv *priv = mport->priv; 897 898 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 899 priv->msg_rx_ring.rx_slot); 900 901 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { 902 printk(KERN_ERR 903 "RIO: error adding inbound buffer %d, buffer exists\n", 904 priv->msg_rx_ring.rx_slot); 905 rc = -EINVAL; 906 goto out; 907 } 908 909 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf; 910 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size) 911 priv->msg_rx_ring.rx_slot = 0; 912 913 out: 914 return rc; 915 } 916 917 /** 918 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit 919 * @mport: Master port implementing the inbound message unit 920 * @mbox: Inbound mailbox number 921 * 922 * Gets the next available inbound message from the inbound message queue. 923 * A pointer to the message is returned on success or NULL on failure. 924 */ 925 static void *fsl_get_inb_message(struct rio_mport *mport, int mbox) 926 { 927 struct rio_priv *priv = mport->priv; 928 u32 phys_buf, virt_buf; 929 void *buf = NULL; 930 int buf_idx; 931 932 phys_buf = in_be32(&priv->msg_regs->ifqdpar); 933 934 /* If no more messages, then bail out */ 935 if (phys_buf == in_be32(&priv->msg_regs->ifqepar)) 936 goto out2; 937 938 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf 939 - priv->msg_rx_ring.phys); 940 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 941 buf = priv->msg_rx_ring.virt_buffer[buf_idx]; 942 943 if (!buf) { 944 printk(KERN_ERR 945 "RIO: inbound message copy failed, no buffers\n"); 946 goto out1; 947 } 948 949 /* Copy max message size, caller is expected to allocate that big */ 950 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); 951 952 /* Clear the available buffer */ 953 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL; 954 955 out1: 956 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI); 957 958 out2: 959 return buf; 960 } 961 962 /** 963 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 964 * @irq: Linux interrupt number 965 * @dev_instance: Pointer to interrupt-specific data 966 * 967 * Handles doorbell interrupts. Parses a list of registered 968 * doorbell event handlers and executes a matching event handler. 969 */ 970 static irqreturn_t 971 fsl_rio_dbell_handler(int irq, void *dev_instance) 972 { 973 int dsr; 974 struct rio_mport *port = (struct rio_mport *)dev_instance; 975 struct rio_priv *priv = port->priv; 976 977 dsr = in_be32(&priv->msg_regs->dsr); 978 979 if (dsr & DOORBELL_DSR_TE) { 980 pr_info("RIO: doorbell reception error\n"); 981 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE); 982 goto out; 983 } 984 985 if (dsr & DOORBELL_DSR_QFI) { 986 pr_info("RIO: doorbell queue full\n"); 987 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI); 988 } 989 990 /* XXX Need to check/dispatch until queue empty */ 991 if (dsr & DOORBELL_DSR_DIQI) { 992 u32 dmsg = 993 (u32) priv->dbell_ring.virt + 994 (in_be32(&priv->msg_regs->dqdpar) & 0xfff); 995 struct rio_dbell *dbell; 996 int found = 0; 997 998 pr_debug 999 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", 1000 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 1001 1002 list_for_each_entry(dbell, &port->dbells, node) { 1003 if ((dbell->res->start <= DBELL_INF(dmsg)) && 1004 (dbell->res->end >= DBELL_INF(dmsg))) { 1005 found = 1; 1006 break; 1007 } 1008 } 1009 if (found) { 1010 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), 1011 DBELL_INF(dmsg)); 1012 } else { 1013 pr_debug 1014 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", 1015 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 1016 } 1017 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI); 1018 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI); 1019 } 1020 1021 out: 1022 return IRQ_HANDLED; 1023 } 1024 1025 /** 1026 * fsl_rio_doorbell_init - MPC85xx doorbell interface init 1027 * @mport: Master port implementing the inbound doorbell unit 1028 * 1029 * Initializes doorbell unit hardware and inbound DMA buffer 1030 * ring. Called from fsl_rio_setup(). Returns %0 on success 1031 * or %-ENOMEM on failure. 1032 */ 1033 static int fsl_rio_doorbell_init(struct rio_mport *mport) 1034 { 1035 struct rio_priv *priv = mport->priv; 1036 int rc = 0; 1037 1038 /* Map outbound doorbell window immediately after maintenance window */ 1039 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, 1040 RIO_DBELL_WIN_SIZE); 1041 if (!priv->dbell_win) { 1042 printk(KERN_ERR 1043 "RIO: unable to map outbound doorbell window\n"); 1044 rc = -ENOMEM; 1045 goto out; 1046 } 1047 1048 /* Initialize inbound doorbells */ 1049 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 * 1050 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL); 1051 if (!priv->dbell_ring.virt) { 1052 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); 1053 rc = -ENOMEM; 1054 iounmap(priv->dbell_win); 1055 goto out; 1056 } 1057 1058 /* Point dequeue/enqueue pointers at first entry in ring */ 1059 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys); 1060 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys); 1061 1062 /* Clear interrupt status */ 1063 out_be32(&priv->msg_regs->dsr, 0x00000091); 1064 1065 /* Hook up doorbell handler */ 1066 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, 1067 "dbell_rx", (void *)mport); 1068 if (rc < 0) { 1069 iounmap(priv->dbell_win); 1070 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE, 1071 priv->dbell_ring.virt, priv->dbell_ring.phys); 1072 printk(KERN_ERR 1073 "MPC85xx RIO: unable to request inbound doorbell irq"); 1074 goto out; 1075 } 1076 1077 /* Configure doorbells for snooping, 512 entries, and enable */ 1078 out_be32(&priv->msg_regs->dmr, 0x00108161); 1079 1080 out: 1081 return rc; 1082 } 1083 1084 static void port_error_handler(struct rio_mport *port, int offset) 1085 { 1086 /*XXX: Error recovery is not implemented, we just clear errors */ 1087 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 1088 1089 if (offset == 0) { 1090 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0); 1091 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), 0); 1092 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR); 1093 } else { 1094 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0); 1095 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), 0); 1096 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); 1097 } 1098 } 1099 1100 static void msg_unit_error_handler(struct rio_mport *port) 1101 { 1102 struct rio_priv *priv = port->priv; 1103 1104 /*XXX: Error recovery is not implemented, we just clear errors */ 1105 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 1106 1107 out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR); 1108 out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR); 1109 out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR); 1110 out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR); 1111 1112 out_be32(&priv->msg_regs->odsr, ODSR_CLEAR); 1113 out_be32(&priv->msg_regs->dsr, IDSR_CLEAR); 1114 1115 out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR); 1116 } 1117 1118 /** 1119 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler 1120 * @irq: Linux interrupt number 1121 * @dev_instance: Pointer to interrupt-specific data 1122 * 1123 * Handles port write interrupts. Parses a list of registered 1124 * port write event handlers and executes a matching event handler. 1125 */ 1126 static irqreturn_t 1127 fsl_rio_port_write_handler(int irq, void *dev_instance) 1128 { 1129 u32 ipwmr, ipwsr; 1130 struct rio_mport *port = (struct rio_mport *)dev_instance; 1131 struct rio_priv *priv = port->priv; 1132 u32 epwisr, tmp; 1133 1134 epwisr = in_be32(priv->regs_win + RIO_EPWISR); 1135 if (!(epwisr & RIO_EPWISR_PW)) 1136 goto pw_done; 1137 1138 ipwmr = in_be32(&priv->msg_regs->pwmr); 1139 ipwsr = in_be32(&priv->msg_regs->pwsr); 1140 1141 #ifdef DEBUG_PW 1142 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); 1143 if (ipwsr & RIO_IPWSR_QF) 1144 pr_debug(" QF"); 1145 if (ipwsr & RIO_IPWSR_TE) 1146 pr_debug(" TE"); 1147 if (ipwsr & RIO_IPWSR_QFI) 1148 pr_debug(" QFI"); 1149 if (ipwsr & RIO_IPWSR_PWD) 1150 pr_debug(" PWD"); 1151 if (ipwsr & RIO_IPWSR_PWB) 1152 pr_debug(" PWB"); 1153 pr_debug(" )\n"); 1154 #endif 1155 /* Schedule deferred processing if PW was received */ 1156 if (ipwsr & RIO_IPWSR_QFI) { 1157 /* Save PW message (if there is room in FIFO), 1158 * otherwise discard it. 1159 */ 1160 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) { 1161 priv->port_write_msg.msg_count++; 1162 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt, 1163 RIO_PW_MSG_SIZE); 1164 } else { 1165 priv->port_write_msg.discard_count++; 1166 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", 1167 priv->port_write_msg.discard_count); 1168 } 1169 /* Clear interrupt and issue Clear Queue command. This allows 1170 * another port-write to be received. 1171 */ 1172 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI); 1173 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ); 1174 1175 schedule_work(&priv->pw_work); 1176 } 1177 1178 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { 1179 priv->port_write_msg.err_count++; 1180 pr_debug("RIO: Port-Write Transaction Err (%d)\n", 1181 priv->port_write_msg.err_count); 1182 /* Clear Transaction Error: port-write controller should be 1183 * disabled when clearing this error 1184 */ 1185 out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); 1186 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE); 1187 out_be32(&priv->msg_regs->pwmr, ipwmr); 1188 } 1189 1190 if (ipwsr & RIO_IPWSR_PWD) { 1191 priv->port_write_msg.discard_count++; 1192 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", 1193 priv->port_write_msg.discard_count); 1194 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD); 1195 } 1196 1197 pw_done: 1198 if (epwisr & RIO_EPWISR_PINT1) { 1199 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 1200 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 1201 port_error_handler(port, 0); 1202 } 1203 1204 if (epwisr & RIO_EPWISR_PINT2) { 1205 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 1206 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 1207 port_error_handler(port, 1); 1208 } 1209 1210 if (epwisr & RIO_EPWISR_MU) { 1211 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 1212 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 1213 msg_unit_error_handler(port); 1214 } 1215 1216 return IRQ_HANDLED; 1217 } 1218 1219 static void fsl_pw_dpc(struct work_struct *work) 1220 { 1221 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work); 1222 unsigned long flags; 1223 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; 1224 1225 /* 1226 * Process port-write messages 1227 */ 1228 spin_lock_irqsave(&priv->pw_fifo_lock, flags); 1229 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer, 1230 RIO_PW_MSG_SIZE)) { 1231 /* Process one message */ 1232 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 1233 #ifdef DEBUG_PW 1234 { 1235 u32 i; 1236 pr_debug("%s : Port-Write Message:", __func__); 1237 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { 1238 if ((i%4) == 0) 1239 pr_debug("\n0x%02x: 0x%08x", i*4, 1240 msg_buffer[i]); 1241 else 1242 pr_debug(" 0x%08x", msg_buffer[i]); 1243 } 1244 pr_debug("\n"); 1245 } 1246 #endif 1247 /* Pass the port-write message to RIO core for processing */ 1248 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); 1249 spin_lock_irqsave(&priv->pw_fifo_lock, flags); 1250 } 1251 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 1252 } 1253 1254 /** 1255 * fsl_rio_pw_enable - enable/disable port-write interface init 1256 * @mport: Master port implementing the port write unit 1257 * @enable: 1=enable; 0=disable port-write message handling 1258 */ 1259 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable) 1260 { 1261 struct rio_priv *priv = mport->priv; 1262 u32 rval; 1263 1264 rval = in_be32(&priv->msg_regs->pwmr); 1265 1266 if (enable) 1267 rval |= RIO_IPWMR_PWE; 1268 else 1269 rval &= ~RIO_IPWMR_PWE; 1270 1271 out_be32(&priv->msg_regs->pwmr, rval); 1272 1273 return 0; 1274 } 1275 1276 /** 1277 * fsl_rio_port_write_init - MPC85xx port write interface init 1278 * @mport: Master port implementing the port write unit 1279 * 1280 * Initializes port write unit hardware and DMA buffer 1281 * ring. Called from fsl_rio_setup(). Returns %0 on success 1282 * or %-ENOMEM on failure. 1283 */ 1284 static int fsl_rio_port_write_init(struct rio_mport *mport) 1285 { 1286 struct rio_priv *priv = mport->priv; 1287 int rc = 0; 1288 1289 /* Following configurations require a disabled port write controller */ 1290 out_be32(&priv->msg_regs->pwmr, 1291 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE); 1292 1293 /* Initialize port write */ 1294 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev, 1295 RIO_PW_MSG_SIZE, 1296 &priv->port_write_msg.phys, GFP_KERNEL); 1297 if (!priv->port_write_msg.virt) { 1298 pr_err("RIO: unable allocate port write queue\n"); 1299 return -ENOMEM; 1300 } 1301 1302 priv->port_write_msg.err_count = 0; 1303 priv->port_write_msg.discard_count = 0; 1304 1305 /* Point dequeue/enqueue pointers at first entry */ 1306 out_be32(&priv->msg_regs->epwqbar, 0); 1307 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys); 1308 1309 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", 1310 in_be32(&priv->msg_regs->epwqbar), 1311 in_be32(&priv->msg_regs->pwqbar)); 1312 1313 /* Clear interrupt status IPWSR */ 1314 out_be32(&priv->msg_regs->pwsr, 1315 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); 1316 1317 /* Configure port write contoller for snooping enable all reporting, 1318 clear queue full */ 1319 out_be32(&priv->msg_regs->pwmr, 1320 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); 1321 1322 1323 /* Hook up port-write handler */ 1324 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 1325 IRQF_SHARED, "port-write", (void *)mport); 1326 if (rc < 0) { 1327 pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); 1328 goto err_out; 1329 } 1330 /* Enable Error Interrupt */ 1331 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL); 1332 1333 INIT_WORK(&priv->pw_work, fsl_pw_dpc); 1334 spin_lock_init(&priv->pw_fifo_lock); 1335 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { 1336 pr_err("FIFO allocation failed\n"); 1337 rc = -ENOMEM; 1338 goto err_out_irq; 1339 } 1340 1341 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", 1342 in_be32(&priv->msg_regs->pwmr), 1343 in_be32(&priv->msg_regs->pwsr)); 1344 1345 return rc; 1346 1347 err_out_irq: 1348 free_irq(IRQ_RIO_PW(mport), (void *)mport); 1349 err_out: 1350 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE, 1351 priv->port_write_msg.virt, 1352 priv->port_write_msg.phys); 1353 return rc; 1354 } 1355 1356 static inline void fsl_rio_info(struct device *dev, u32 ccsr) 1357 { 1358 const char *str; 1359 if (ccsr & 1) { 1360 /* Serial phy */ 1361 switch (ccsr >> 30) { 1362 case 0: 1363 str = "1"; 1364 break; 1365 case 1: 1366 str = "4"; 1367 break; 1368 default: 1369 str = "Unknown"; 1370 break; 1371 } 1372 dev_info(dev, "Hardware port width: %s\n", str); 1373 1374 switch ((ccsr >> 27) & 7) { 1375 case 0: 1376 str = "Single-lane 0"; 1377 break; 1378 case 1: 1379 str = "Single-lane 2"; 1380 break; 1381 case 2: 1382 str = "Four-lane"; 1383 break; 1384 default: 1385 str = "Unknown"; 1386 break; 1387 } 1388 dev_info(dev, "Training connection status: %s\n", str); 1389 } else { 1390 /* Parallel phy */ 1391 if (!(ccsr & 0x80000000)) 1392 dev_info(dev, "Output port operating in 8-bit mode\n"); 1393 if (!(ccsr & 0x08000000)) 1394 dev_info(dev, "Input port operating in 8-bit mode\n"); 1395 } 1396 } 1397 1398 /** 1399 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface 1400 * @dev: platform_device pointer 1401 * 1402 * Initializes MPC85xx RapidIO hardware interface, configures 1403 * master port with system-specific info, and registers the 1404 * master port with the RapidIO subsystem. 1405 */ 1406 int fsl_rio_setup(struct platform_device *dev) 1407 { 1408 struct rio_ops *ops; 1409 struct rio_mport *port; 1410 struct rio_priv *priv; 1411 int rc = 0; 1412 const u32 *dt_range, *cell; 1413 struct resource regs; 1414 int rlen; 1415 u32 ccsr; 1416 u64 law_start, law_size; 1417 int paw, aw, sw; 1418 1419 if (!dev->dev.of_node) { 1420 dev_err(&dev->dev, "Device OF-Node is NULL"); 1421 return -EFAULT; 1422 } 1423 1424 rc = of_address_to_resource(dev->dev.of_node, 0, ®s); 1425 if (rc) { 1426 dev_err(&dev->dev, "Can't get %s property 'reg'\n", 1427 dev->dev.of_node->full_name); 1428 return -EFAULT; 1429 } 1430 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); 1431 dev_info(&dev->dev, "Regs: %pR\n", ®s); 1432 1433 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); 1434 if (!dt_range) { 1435 dev_err(&dev->dev, "Can't get %s property 'ranges'\n", 1436 dev->dev.of_node->full_name); 1437 return -EFAULT; 1438 } 1439 1440 /* Get node address wide */ 1441 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL); 1442 if (cell) 1443 aw = *cell; 1444 else 1445 aw = of_n_addr_cells(dev->dev.of_node); 1446 /* Get node size wide */ 1447 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL); 1448 if (cell) 1449 sw = *cell; 1450 else 1451 sw = of_n_size_cells(dev->dev.of_node); 1452 /* Get parent address wide wide */ 1453 paw = of_n_addr_cells(dev->dev.of_node); 1454 1455 law_start = of_read_number(dt_range + aw, paw); 1456 law_size = of_read_number(dt_range + aw + paw, sw); 1457 1458 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n", 1459 law_start, law_size); 1460 1461 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); 1462 if (!ops) { 1463 rc = -ENOMEM; 1464 goto err_ops; 1465 } 1466 ops->lcread = fsl_local_config_read; 1467 ops->lcwrite = fsl_local_config_write; 1468 ops->cread = fsl_rio_config_read; 1469 ops->cwrite = fsl_rio_config_write; 1470 ops->dsend = fsl_rio_doorbell_send; 1471 ops->pwenable = fsl_rio_pw_enable; 1472 ops->open_outb_mbox = fsl_open_outb_mbox; 1473 ops->open_inb_mbox = fsl_open_inb_mbox; 1474 ops->close_outb_mbox = fsl_close_outb_mbox; 1475 ops->close_inb_mbox = fsl_close_inb_mbox; 1476 ops->add_outb_message = fsl_add_outb_message; 1477 ops->add_inb_buffer = fsl_add_inb_buffer; 1478 ops->get_inb_message = fsl_get_inb_message; 1479 1480 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 1481 if (!port) { 1482 rc = -ENOMEM; 1483 goto err_port; 1484 } 1485 port->index = 0; 1486 1487 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); 1488 if (!priv) { 1489 printk(KERN_ERR "Can't alloc memory for 'priv'\n"); 1490 rc = -ENOMEM; 1491 goto err_priv; 1492 } 1493 1494 INIT_LIST_HEAD(&port->dbells); 1495 port->iores.start = law_start; 1496 port->iores.end = law_start + law_size - 1; 1497 port->iores.flags = IORESOURCE_MEM; 1498 port->iores.name = "rio_io_win"; 1499 1500 if (request_resource(&iomem_resource, &port->iores) < 0) { 1501 dev_err(&dev->dev, "RIO: Error requesting master port region" 1502 " 0x%016llx-0x%016llx\n", 1503 (u64)port->iores.start, (u64)port->iores.end); 1504 rc = -ENOMEM; 1505 goto err_res; 1506 } 1507 1508 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 1509 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 1510 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); 1511 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); 1512 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n", 1513 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq); 1514 1515 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 1516 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 1517 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 1518 strcpy(port->name, "RIO0 mport"); 1519 1520 priv->dev = &dev->dev; 1521 1522 port->ops = ops; 1523 port->priv = priv; 1524 port->phys_efptr = 0x100; 1525 1526 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); 1527 rio_regs_win = priv->regs_win; 1528 1529 /* Probe the master port phy type */ 1530 ccsr = in_be32(priv->regs_win + RIO_CCSR); 1531 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; 1532 dev_info(&dev->dev, "RapidIO PHY type: %s\n", 1533 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" : 1534 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" : 1535 "unknown")); 1536 /* Checking the port training status */ 1537 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 1538 dev_err(&dev->dev, "Port is not ready. " 1539 "Try to restart connection...\n"); 1540 switch (port->phy_type) { 1541 case RIO_PHY_SERIAL: 1542 /* Disable ports */ 1543 out_be32(priv->regs_win + RIO_CCSR, 0); 1544 /* Set 1x lane */ 1545 setbits32(priv->regs_win + RIO_CCSR, 0x02000000); 1546 /* Enable ports */ 1547 setbits32(priv->regs_win + RIO_CCSR, 0x00600000); 1548 break; 1549 case RIO_PHY_PARALLEL: 1550 /* Disable ports */ 1551 out_be32(priv->regs_win + RIO_CCSR, 0x22000000); 1552 /* Enable ports */ 1553 out_be32(priv->regs_win + RIO_CCSR, 0x44000000); 1554 break; 1555 } 1556 msleep(100); 1557 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 1558 dev_err(&dev->dev, "Port restart failed.\n"); 1559 rc = -ENOLINK; 1560 goto err; 1561 } 1562 dev_info(&dev->dev, "Port restart success!\n"); 1563 } 1564 fsl_rio_info(&dev->dev, ccsr); 1565 1566 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 1567 & RIO_PEF_CTLS) >> 4; 1568 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 1569 port->sys_size ? 65536 : 256); 1570 1571 if (rio_register_mport(port)) 1572 goto err; 1573 1574 if (port->host_deviceid >= 0) 1575 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | 1576 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED); 1577 else 1578 out_be32(priv->regs_win + RIO_GCCSR, 0x00000000); 1579 1580 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 1581 + RIO_ATMU_REGS_OFFSET); 1582 priv->maint_atmu_regs = priv->atmu_regs + 1; 1583 priv->dbell_atmu_regs = priv->atmu_regs + 2; 1584 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + 1585 ((port->phy_type == RIO_PHY_SERIAL) ? 1586 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); 1587 1588 /* Set to receive any dist ID for serial RapidIO controller. */ 1589 if (port->phy_type == RIO_PHY_SERIAL) 1590 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); 1591 1592 /* Configure maintenance transaction window */ 1593 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12); 1594 out_be32(&priv->maint_atmu_regs->rowar, 1595 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); 1596 1597 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); 1598 1599 /* Configure outbound doorbell window */ 1600 out_be32(&priv->dbell_atmu_regs->rowbar, 1601 (law_start + RIO_MAINT_WIN_SIZE) >> 12); 1602 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ 1603 fsl_rio_doorbell_init(port); 1604 fsl_rio_port_write_init(port); 1605 1606 return 0; 1607 err: 1608 iounmap(priv->regs_win); 1609 err_res: 1610 kfree(priv); 1611 err_priv: 1612 kfree(port); 1613 err_port: 1614 kfree(ops); 1615 err_ops: 1616 return rc; 1617 } 1618 1619 /* The probe function for RapidIO peer-to-peer network. 1620 */ 1621 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev) 1622 { 1623 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", 1624 dev->dev.of_node->full_name); 1625 1626 return fsl_rio_setup(dev); 1627 }; 1628 1629 static const struct of_device_id fsl_of_rio_rpn_ids[] = { 1630 { 1631 .compatible = "fsl,rapidio-delta", 1632 }, 1633 {}, 1634 }; 1635 1636 static struct platform_driver fsl_of_rio_rpn_driver = { 1637 .driver = { 1638 .name = "fsl-of-rio", 1639 .owner = THIS_MODULE, 1640 .of_match_table = fsl_of_rio_rpn_ids, 1641 }, 1642 .probe = fsl_of_rio_rpn_probe, 1643 }; 1644 1645 static __init int fsl_of_rio_rpn_init(void) 1646 { 1647 return platform_driver_register(&fsl_of_rio_rpn_driver); 1648 } 1649 1650 subsys_initcall(fsl_of_rio_rpn_init); 1651