1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC83xx/85xx/86xx PCI/PCIE support routing. 4 * 5 * Copyright 2007-2012 Freescale Semiconductor, Inc. 6 * Copyright 2008-2009 MontaVista Software, Inc. 7 * 8 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 9 * Recode: ZHANG WEI <wei.zhang@freescale.com> 10 * Rewrite the routing for Frescale PCI and PCI Express 11 * Roy Zang <tie-fei.zang@freescale.com> 12 * MPC83xx PCI-Express support: 13 * Tony Li <tony.li@freescale.com> 14 * Anton Vorontsov <avorontsov@ru.mvista.com> 15 */ 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/fsl/edac.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/memblock.h> 24 #include <linux/log2.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/platform_device.h> 28 #include <linux/slab.h> 29 #include <linux/suspend.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/uaccess.h> 32 33 #include <asm/io.h> 34 #include <asm/pci-bridge.h> 35 #include <asm/ppc-pci.h> 36 #include <asm/machdep.h> 37 #include <asm/mpc85xx.h> 38 #include <asm/disassemble.h> 39 #include <asm/ppc-opcode.h> 40 #include <asm/swiotlb.h> 41 #include <sysdev/fsl_soc.h> 42 #include <sysdev/fsl_pci.h> 43 44 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 45 46 static void quirk_fsl_pcie_early(struct pci_dev *dev) 47 { 48 u8 hdr_type; 49 50 /* if we aren't a PCIe don't bother */ 51 if (!pci_is_pcie(dev)) 52 return; 53 54 /* if we aren't in host mode don't bother */ 55 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 56 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 57 return; 58 59 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 60 fsl_pcie_bus_fixup = 1; 61 return; 62 } 63 64 static int fsl_indirect_read_config(struct pci_bus *, unsigned int, 65 int, int, u32 *); 66 67 static int fsl_pcie_check_link(struct pci_controller *hose) 68 { 69 u32 val = 0; 70 71 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { 72 if (hose->ops->read == fsl_indirect_read_config) 73 __indirect_read_config(hose, hose->first_busno, 0, 74 PCIE_LTSSM, 4, &val); 75 else 76 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 77 if (val < PCIE_LTSSM_L0) 78 return 1; 79 } else { 80 struct ccsr_pci __iomem *pci = hose->private_data; 81 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ 82 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) 83 >> PEX_CSR0_LTSSM_SHIFT; 84 if (val != PEX_CSR0_LTSSM_L0) 85 return 1; 86 } 87 88 return 0; 89 } 90 91 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, 92 int offset, int len, u32 *val) 93 { 94 struct pci_controller *hose = pci_bus_to_host(bus); 95 96 if (fsl_pcie_check_link(hose)) 97 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 98 else 99 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; 100 101 return indirect_read_config(bus, devfn, offset, len, val); 102 } 103 104 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 105 106 static struct pci_ops fsl_indirect_pcie_ops = 107 { 108 .read = fsl_indirect_read_config, 109 .write = indirect_write_config, 110 }; 111 112 static u64 pci64_dma_offset; 113 114 #ifdef CONFIG_SWIOTLB 115 static void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev) 116 { 117 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 118 119 pdev->dev.bus_dma_limit = 120 hose->dma_window_base_cur + hose->dma_window_size - 1; 121 } 122 123 static void setup_swiotlb_ops(struct pci_controller *hose) 124 { 125 if (ppc_swiotlb_enable) 126 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; 127 } 128 #else 129 static inline void setup_swiotlb_ops(struct pci_controller *hose) {} 130 #endif 131 132 static void fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) 133 { 134 /* 135 * Fix up PCI devices that are able to DMA to the large inbound 136 * mapping that allows addressing any RAM address from across PCI. 137 */ 138 if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) { 139 dev->bus_dma_limit = 0; 140 dev->archdata.dma_offset = pci64_dma_offset; 141 } 142 } 143 144 static int setup_one_atmu(struct ccsr_pci __iomem *pci, 145 unsigned int index, const struct resource *res, 146 resource_size_t offset) 147 { 148 resource_size_t pci_addr = res->start - offset; 149 resource_size_t phys_addr = res->start; 150 resource_size_t size = resource_size(res); 151 u32 flags = 0x80044000; /* enable & mem R/W */ 152 unsigned int i; 153 154 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 155 (u64)res->start, (u64)size); 156 157 if (res->flags & IORESOURCE_PREFETCH) 158 flags |= 0x10000000; /* enable relaxed ordering */ 159 160 for (i = 0; size > 0; i++) { 161 unsigned int bits = min_t(u32, ilog2(size), 162 __ffs(pci_addr | phys_addr)); 163 164 if (index + i >= 5) 165 return -1; 166 167 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 168 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 169 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 170 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 171 172 pci_addr += (resource_size_t)1U << bits; 173 phys_addr += (resource_size_t)1U << bits; 174 size -= (resource_size_t)1U << bits; 175 } 176 177 return i; 178 } 179 180 static bool is_kdump(void) 181 { 182 struct device_node *node; 183 184 node = of_find_node_by_type(NULL, "memory"); 185 if (!node) { 186 WARN_ON_ONCE(1); 187 return false; 188 } 189 190 return of_property_read_bool(node, "linux,usable-memory"); 191 } 192 193 /* atmu setup for fsl pci/pcie controller */ 194 static void setup_pci_atmu(struct pci_controller *hose) 195 { 196 struct ccsr_pci __iomem *pci = hose->private_data; 197 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 198 u64 mem, sz, paddr_hi = 0; 199 u64 offset = 0, paddr_lo = ULLONG_MAX; 200 u32 pcicsrbar = 0, pcicsrbar_sz; 201 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 202 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 203 const u64 *reg; 204 int len; 205 bool setup_inbound; 206 207 /* 208 * If this is kdump, we don't want to trigger a bunch of PCI 209 * errors by closing the window on in-flight DMA. 210 * 211 * We still run most of the function's logic so that things like 212 * hose->dma_window_size still get set. 213 */ 214 setup_inbound = !is_kdump(); 215 216 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) { 217 /* 218 * BSC9132 Rev1.0 has an issue where all the PEX inbound 219 * windows have implemented the default target value as 0xf 220 * for CCSR space.In all Freescale legacy devices the target 221 * of 0xf is reserved for local memory space. 9132 Rev1.0 222 * now has local memory space mapped to target 0x0 instead of 223 * 0xf. Hence adding a workaround to remove the target 0xf 224 * defined for memory space from Inbound window attributes. 225 */ 226 piwar &= ~PIWAR_TGI_LOCAL; 227 } 228 229 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 230 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 231 win_idx = 2; 232 start_idx = 0; 233 end_idx = 3; 234 } 235 } 236 237 /* Disable all windows (except powar0 since it's ignored) */ 238 for(i = 1; i < 5; i++) 239 out_be32(&pci->pow[i].powar, 0); 240 241 if (setup_inbound) { 242 for (i = start_idx; i < end_idx; i++) 243 out_be32(&pci->piw[i].piwar, 0); 244 } 245 246 /* Setup outbound MEM window */ 247 for(i = 0, j = 1; i < 3; i++) { 248 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 249 continue; 250 251 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 252 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 253 254 /* We assume all memory resources have the same offset */ 255 offset = hose->mem_offset[i]; 256 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); 257 258 if (n < 0 || j >= 5) { 259 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 260 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 261 } else 262 j += n; 263 } 264 265 /* Setup outbound IO window */ 266 if (hose->io_resource.flags & IORESOURCE_IO) { 267 if (j >= 5) { 268 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 269 } else { 270 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 271 "phy base 0x%016llx.\n", 272 (u64)hose->io_resource.start, 273 (u64)resource_size(&hose->io_resource), 274 (u64)hose->io_base_phys); 275 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 276 out_be32(&pci->pow[j].potear, 0); 277 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 278 /* Enable, IO R/W */ 279 out_be32(&pci->pow[j].powar, 0x80088000 280 | (ilog2(hose->io_resource.end 281 - hose->io_resource.start + 1) - 1)); 282 } 283 } 284 285 /* convert to pci address space */ 286 paddr_hi -= offset; 287 paddr_lo -= offset; 288 289 if (paddr_hi == paddr_lo) { 290 pr_err("%pOF: No outbound window space\n", hose->dn); 291 return; 292 } 293 294 if (paddr_lo == 0) { 295 pr_err("%pOF: No space for inbound window\n", hose->dn); 296 return; 297 } 298 299 /* setup PCSRBAR/PEXCSRBAR */ 300 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 301 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 302 pcicsrbar_sz = ~pcicsrbar_sz + 1; 303 304 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 305 (paddr_lo > 0x100000000ull)) 306 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 307 else 308 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 309 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 310 311 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 312 313 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar); 314 315 /* Setup inbound mem window */ 316 mem = memblock_end_of_DRAM(); 317 pr_info("%s: end of DRAM %llx\n", __func__, mem); 318 319 /* 320 * The msi-address-64 property, if it exists, indicates the physical 321 * address of the MSIIR register. Normally, this register is located 322 * inside CCSR, so the ATMU that covers all of CCSR is used. But if 323 * this property exists, then we normally need to create a new ATMU 324 * for it. For now, however, we cheat. The only entity that creates 325 * this property is the Freescale hypervisor, and the address is 326 * specified in the partition configuration. Typically, the address 327 * is located in the page immediately after the end of DDR. If so, we 328 * can avoid allocating a new ATMU by extending the DDR ATMU by one 329 * page. 330 */ 331 reg = of_get_property(hose->dn, "msi-address-64", &len); 332 if (reg && (len == sizeof(u64))) { 333 u64 address = be64_to_cpup(reg); 334 335 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { 336 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn); 337 mem += PAGE_SIZE; 338 } else { 339 /* TODO: Create a new ATMU for MSIIR */ 340 pr_warn("%pOF: msi-address-64 address of %llx is " 341 "unsupported\n", hose->dn, address); 342 } 343 } 344 345 sz = min(mem, paddr_lo); 346 mem_log = ilog2(sz); 347 348 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 349 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 350 /* Size window to exact size if power-of-two or one size up */ 351 if ((1ull << mem_log) != mem) { 352 mem_log++; 353 if ((1ull << mem_log) > mem) 354 pr_info("%pOF: Setting PCI inbound window " 355 "greater than memory size\n", hose->dn); 356 } 357 358 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 359 360 if (setup_inbound) { 361 /* Setup inbound memory window */ 362 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 363 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 364 out_be32(&pci->piw[win_idx].piwar, piwar); 365 } 366 367 win_idx--; 368 hose->dma_window_base_cur = 0x00000000; 369 hose->dma_window_size = (resource_size_t)sz; 370 371 /* 372 * if we have >4G of memory setup second PCI inbound window to 373 * let devices that are 64-bit address capable to work w/o 374 * SWIOTLB and access the full range of memory 375 */ 376 if (sz != mem) { 377 mem_log = ilog2(mem); 378 379 /* Size window up if we dont fit in exact power-of-2 */ 380 if ((1ull << mem_log) != mem) 381 mem_log++; 382 383 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); 384 pci64_dma_offset = 1ULL << mem_log; 385 386 if (setup_inbound) { 387 /* Setup inbound memory window */ 388 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 389 out_be32(&pci->piw[win_idx].piwbear, 390 pci64_dma_offset >> 44); 391 out_be32(&pci->piw[win_idx].piwbar, 392 pci64_dma_offset >> 12); 393 out_be32(&pci->piw[win_idx].piwar, piwar); 394 } 395 396 /* 397 * install our own dma_set_mask handler to fixup dma_ops 398 * and dma_offset 399 */ 400 ppc_md.dma_set_mask = fsl_pci_dma_set_mask; 401 402 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn); 403 } 404 } else { 405 u64 paddr = 0; 406 407 if (setup_inbound) { 408 /* Setup inbound memory window */ 409 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 410 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 411 out_be32(&pci->piw[win_idx].piwar, 412 (piwar | (mem_log - 1))); 413 } 414 415 win_idx--; 416 paddr += 1ull << mem_log; 417 sz -= 1ull << mem_log; 418 419 if (sz) { 420 mem_log = ilog2(sz); 421 piwar |= (mem_log - 1); 422 423 if (setup_inbound) { 424 out_be32(&pci->piw[win_idx].pitar, 425 paddr >> 12); 426 out_be32(&pci->piw[win_idx].piwbar, 427 paddr >> 12); 428 out_be32(&pci->piw[win_idx].piwar, piwar); 429 } 430 431 win_idx--; 432 paddr += 1ull << mem_log; 433 } 434 435 hose->dma_window_base_cur = 0x00000000; 436 hose->dma_window_size = (resource_size_t)paddr; 437 } 438 439 if (hose->dma_window_size < mem) { 440 #ifdef CONFIG_SWIOTLB 441 ppc_swiotlb_enable = 1; 442 #else 443 pr_err("%pOF: ERROR: Memory size exceeds PCI ATMU ability to " 444 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 445 hose->dn); 446 #endif 447 /* adjusting outbound windows could reclaim space in mem map */ 448 if (paddr_hi < 0xffffffffull) 449 pr_warn("%pOF: WARNING: Outbound window cfg leaves " 450 "gaps in memory map. Adjusting the memory map " 451 "could reduce unnecessary bounce buffering.\n", 452 hose->dn); 453 454 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn, 455 (u64)hose->dma_window_size); 456 } 457 } 458 459 static void setup_pci_cmd(struct pci_controller *hose) 460 { 461 u16 cmd; 462 int cap_x; 463 464 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 465 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 466 | PCI_COMMAND_IO; 467 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 468 469 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 470 if (cap_x) { 471 int pci_x_cmd = cap_x + PCI_X_CMD; 472 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 473 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 474 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 475 } else { 476 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 477 } 478 } 479 480 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 481 { 482 struct pci_controller *hose = pci_bus_to_host(bus); 483 int i, is_pcie = 0, no_link; 484 485 /* The root complex bridge comes up with bogus resources, 486 * we copy the PHB ones in. 487 * 488 * With the current generic PCI code, the PHB bus no longer 489 * has bus->resource[0..4] set, so things are a bit more 490 * tricky. 491 */ 492 493 if (fsl_pcie_bus_fixup) 494 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 495 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); 496 497 if (bus->parent == hose->bus && (is_pcie || no_link)) { 498 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { 499 struct resource *res = bus->resource[i]; 500 struct resource *par; 501 502 if (!res) 503 continue; 504 if (i == 0) 505 par = &hose->io_resource; 506 else if (i < 4) 507 par = &hose->mem_resources[i-1]; 508 else par = NULL; 509 510 res->start = par ? par->start : 0; 511 res->end = par ? par->end : 0; 512 res->flags = par ? par->flags : 0; 513 } 514 } 515 } 516 517 int fsl_add_bridge(struct platform_device *pdev, int is_primary) 518 { 519 int len; 520 struct pci_controller *hose; 521 struct resource rsrc; 522 const int *bus_range; 523 u8 hdr_type, progif; 524 struct device_node *dev; 525 struct ccsr_pci __iomem *pci; 526 u16 temp; 527 u32 svr = mfspr(SPRN_SVR); 528 529 dev = pdev->dev.of_node; 530 531 if (!of_device_is_available(dev)) { 532 pr_warn("%pOF: disabled\n", dev); 533 return -ENODEV; 534 } 535 536 pr_debug("Adding PCI host bridge %pOF\n", dev); 537 538 /* Fetch host bridge registers address */ 539 if (of_address_to_resource(dev, 0, &rsrc)) { 540 printk(KERN_WARNING "Can't get pci register base!"); 541 return -ENOMEM; 542 } 543 544 /* Get bus range if any */ 545 bus_range = of_get_property(dev, "bus-range", &len); 546 if (bus_range == NULL || len < 2 * sizeof(int)) 547 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" 548 " bus 0\n", dev); 549 550 pci_add_flags(PCI_REASSIGN_ALL_BUS); 551 hose = pcibios_alloc_controller(dev); 552 if (!hose) 553 return -ENOMEM; 554 555 /* set platform device as the parent */ 556 hose->parent = &pdev->dev; 557 hose->first_busno = bus_range ? bus_range[0] : 0x0; 558 hose->last_busno = bus_range ? bus_range[1] : 0xff; 559 560 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 561 (u64)rsrc.start, (u64)resource_size(&rsrc)); 562 563 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); 564 if (!hose->private_data) 565 goto no_bridge; 566 567 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 568 PPC_INDIRECT_TYPE_BIG_ENDIAN); 569 570 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) 571 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 572 573 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 574 /* use fsl_indirect_read_config for PCIe */ 575 hose->ops = &fsl_indirect_pcie_ops; 576 /* For PCIE read HEADER_TYPE to identify controller mode */ 577 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); 578 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 579 goto no_bridge; 580 581 } else { 582 /* For PCI read PROG to identify controller mode */ 583 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 584 if ((progif & 1) && 585 !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) 586 goto no_bridge; 587 } 588 589 setup_pci_cmd(hose); 590 591 /* check PCI express link status */ 592 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 593 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 594 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 595 if (fsl_pcie_check_link(hose)) 596 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 597 } else { 598 /* 599 * Set PBFR(PCI Bus Function Register)[10] = 1 to 600 * disable the combining of crossing cacheline 601 * boundary requests into one burst transaction. 602 * PCI-X operation is not affected. 603 * Fix erratum PCI 5 on MPC8548 604 */ 605 #define PCI_BUS_FUNCTION 0x44 606 #define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */ 607 if (((SVR_SOC_VER(svr) == SVR_8543) || 608 (SVR_SOC_VER(svr) == SVR_8545) || 609 (SVR_SOC_VER(svr) == SVR_8547) || 610 (SVR_SOC_VER(svr) == SVR_8548)) && 611 !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) { 612 early_read_config_word(hose, 0, 0, 613 PCI_BUS_FUNCTION, &temp); 614 temp |= PCI_BUS_FUNCTION_MDS; 615 early_write_config_word(hose, 0, 0, 616 PCI_BUS_FUNCTION, temp); 617 } 618 } 619 620 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 621 "Firmware bus number: %d->%d\n", 622 (unsigned long long)rsrc.start, hose->first_busno, 623 hose->last_busno); 624 625 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 626 hose, hose->cfg_addr, hose->cfg_data); 627 628 /* Interpret the "ranges" property */ 629 /* This also maps the I/O region and sets isa_io/mem_base */ 630 pci_process_bridge_OF_ranges(hose, dev, is_primary); 631 632 /* Setup PEX window registers */ 633 setup_pci_atmu(hose); 634 635 /* Set up controller operations */ 636 setup_swiotlb_ops(hose); 637 638 return 0; 639 640 no_bridge: 641 iounmap(hose->private_data); 642 /* unmap cfg_data & cfg_addr separately if not on same page */ 643 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 644 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 645 iounmap(hose->cfg_data); 646 iounmap(hose->cfg_addr); 647 pcibios_free_controller(hose); 648 return -ENODEV; 649 } 650 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 651 652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 653 quirk_fsl_pcie_early); 654 655 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 656 struct mpc83xx_pcie_priv { 657 void __iomem *cfg_type0; 658 void __iomem *cfg_type1; 659 u32 dev_base; 660 }; 661 662 struct pex_inbound_window { 663 u32 ar; 664 u32 tar; 665 u32 barl; 666 u32 barh; 667 }; 668 669 /* 670 * With the convention of u-boot, the PCIE outbound window 0 serves 671 * as configuration transactions outbound. 672 */ 673 #define PEX_OUTWIN0_BAR 0xCA4 674 #define PEX_OUTWIN0_TAL 0xCA8 675 #define PEX_OUTWIN0_TAH 0xCAC 676 #define PEX_RC_INWIN_BASE 0xE60 677 #define PEX_RCIWARn_EN 0x1 678 679 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 680 { 681 struct pci_controller *hose = pci_bus_to_host(bus); 682 683 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 684 return PCIBIOS_DEVICE_NOT_FOUND; 685 /* 686 * Workaround for the HW bug: for Type 0 configure transactions the 687 * PCI-E controller does not check the device number bits and just 688 * assumes that the device number bits are 0. 689 */ 690 if (bus->number == hose->first_busno || 691 bus->primary == hose->first_busno) { 692 if (devfn & 0xf8) 693 return PCIBIOS_DEVICE_NOT_FOUND; 694 } 695 696 if (ppc_md.pci_exclude_device) { 697 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 698 return PCIBIOS_DEVICE_NOT_FOUND; 699 } 700 701 return PCIBIOS_SUCCESSFUL; 702 } 703 704 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 705 unsigned int devfn, int offset) 706 { 707 struct pci_controller *hose = pci_bus_to_host(bus); 708 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 709 u32 dev_base = bus->number << 24 | devfn << 16; 710 int ret; 711 712 ret = mpc83xx_pcie_exclude_device(bus, devfn); 713 if (ret) 714 return NULL; 715 716 offset &= 0xfff; 717 718 /* Type 0 */ 719 if (bus->number == hose->first_busno) 720 return pcie->cfg_type0 + offset; 721 722 if (pcie->dev_base == dev_base) 723 goto mapped; 724 725 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 726 727 pcie->dev_base = dev_base; 728 mapped: 729 return pcie->cfg_type1 + offset; 730 } 731 732 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 733 int offset, int len, u32 val) 734 { 735 struct pci_controller *hose = pci_bus_to_host(bus); 736 737 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 738 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 739 val &= 0xffffff00; 740 741 return pci_generic_config_write(bus, devfn, offset, len, val); 742 } 743 744 static struct pci_ops mpc83xx_pcie_ops = { 745 .map_bus = mpc83xx_pcie_remap_cfg, 746 .read = pci_generic_config_read, 747 .write = mpc83xx_pcie_write_config, 748 }; 749 750 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 751 struct resource *reg) 752 { 753 struct mpc83xx_pcie_priv *pcie; 754 u32 cfg_bar; 755 int ret = -ENOMEM; 756 757 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 758 if (!pcie) 759 return ret; 760 761 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 762 if (!pcie->cfg_type0) 763 goto err0; 764 765 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 766 if (!cfg_bar) { 767 /* PCI-E isn't configured. */ 768 ret = -ENODEV; 769 goto err1; 770 } 771 772 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 773 if (!pcie->cfg_type1) 774 goto err1; 775 776 WARN_ON(hose->dn->data); 777 hose->dn->data = pcie; 778 hose->ops = &mpc83xx_pcie_ops; 779 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 780 781 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 782 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 783 784 if (fsl_pcie_check_link(hose)) 785 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 786 787 return 0; 788 err1: 789 iounmap(pcie->cfg_type0); 790 err0: 791 kfree(pcie); 792 return ret; 793 794 } 795 796 int __init mpc83xx_add_bridge(struct device_node *dev) 797 { 798 int ret; 799 int len; 800 struct pci_controller *hose; 801 struct resource rsrc_reg; 802 struct resource rsrc_cfg; 803 const int *bus_range; 804 int primary; 805 806 is_mpc83xx_pci = 1; 807 808 if (!of_device_is_available(dev)) { 809 pr_warn("%pOF: disabled by the firmware.\n", 810 dev); 811 return -ENODEV; 812 } 813 pr_debug("Adding PCI host bridge %pOF\n", dev); 814 815 /* Fetch host bridge registers address */ 816 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 817 printk(KERN_WARNING "Can't get pci register base!\n"); 818 return -ENOMEM; 819 } 820 821 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 822 823 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 824 printk(KERN_WARNING 825 "No pci config register base in dev tree, " 826 "using default\n"); 827 /* 828 * MPC83xx supports up to two host controllers 829 * one at 0x8500 has config space registers at 0x8300 830 * one at 0x8600 has config space registers at 0x8380 831 */ 832 if ((rsrc_reg.start & 0xfffff) == 0x8500) 833 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 834 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 835 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 836 } 837 /* 838 * Controller at offset 0x8500 is primary 839 */ 840 if ((rsrc_reg.start & 0xfffff) == 0x8500) 841 primary = 1; 842 else 843 primary = 0; 844 845 /* Get bus range if any */ 846 bus_range = of_get_property(dev, "bus-range", &len); 847 if (bus_range == NULL || len < 2 * sizeof(int)) { 848 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" 849 " bus 0\n", dev); 850 } 851 852 pci_add_flags(PCI_REASSIGN_ALL_BUS); 853 hose = pcibios_alloc_controller(dev); 854 if (!hose) 855 return -ENOMEM; 856 857 hose->first_busno = bus_range ? bus_range[0] : 0; 858 hose->last_busno = bus_range ? bus_range[1] : 0xff; 859 860 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 861 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 862 if (ret) 863 goto err0; 864 } else { 865 setup_indirect_pci(hose, rsrc_cfg.start, 866 rsrc_cfg.start + 4, 0); 867 } 868 869 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 870 "Firmware bus number: %d->%d\n", 871 (unsigned long long)rsrc_reg.start, hose->first_busno, 872 hose->last_busno); 873 874 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 875 hose, hose->cfg_addr, hose->cfg_data); 876 877 /* Interpret the "ranges" property */ 878 /* This also maps the I/O region and sets isa_io/mem_base */ 879 pci_process_bridge_OF_ranges(hose, dev, primary); 880 881 return 0; 882 err0: 883 pcibios_free_controller(hose); 884 return ret; 885 } 886 #endif /* CONFIG_PPC_83xx */ 887 888 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 889 { 890 #ifdef CONFIG_PPC_83xx 891 if (is_mpc83xx_pci) { 892 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 893 struct pex_inbound_window *in; 894 int i; 895 896 /* Walk the Root Complex Inbound windows to match IMMR base */ 897 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 898 for (i = 0; i < 4; i++) { 899 /* not enabled, skip */ 900 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN)) 901 continue; 902 903 if (get_immrbase() == in_le32(&in[i].tar)) 904 return (u64)in_le32(&in[i].barh) << 32 | 905 in_le32(&in[i].barl); 906 } 907 908 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 909 } 910 #endif 911 912 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 913 if (!is_mpc83xx_pci) { 914 u32 base; 915 916 pci_bus_read_config_dword(hose->bus, 917 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 918 919 /* 920 * For PEXCSRBAR, bit 3-0 indicate prefetchable and 921 * address type. So when getting base address, these 922 * bits should be masked 923 */ 924 base &= PCI_BASE_ADDRESS_MEM_MASK; 925 926 return base; 927 } 928 #endif 929 930 return 0; 931 } 932 933 #ifdef CONFIG_E500 934 static int mcheck_handle_load(struct pt_regs *regs, u32 inst) 935 { 936 unsigned int rd, ra, rb, d; 937 938 rd = get_rt(inst); 939 ra = get_ra(inst); 940 rb = get_rb(inst); 941 d = get_d(inst); 942 943 switch (get_op(inst)) { 944 case 31: 945 switch (get_xop(inst)) { 946 case OP_31_XOP_LWZX: 947 case OP_31_XOP_LWBRX: 948 regs->gpr[rd] = 0xffffffff; 949 break; 950 951 case OP_31_XOP_LWZUX: 952 regs->gpr[rd] = 0xffffffff; 953 regs->gpr[ra] += regs->gpr[rb]; 954 break; 955 956 case OP_31_XOP_LBZX: 957 regs->gpr[rd] = 0xff; 958 break; 959 960 case OP_31_XOP_LBZUX: 961 regs->gpr[rd] = 0xff; 962 regs->gpr[ra] += regs->gpr[rb]; 963 break; 964 965 case OP_31_XOP_LHZX: 966 case OP_31_XOP_LHBRX: 967 regs->gpr[rd] = 0xffff; 968 break; 969 970 case OP_31_XOP_LHZUX: 971 regs->gpr[rd] = 0xffff; 972 regs->gpr[ra] += regs->gpr[rb]; 973 break; 974 975 case OP_31_XOP_LHAX: 976 regs->gpr[rd] = ~0UL; 977 break; 978 979 case OP_31_XOP_LHAUX: 980 regs->gpr[rd] = ~0UL; 981 regs->gpr[ra] += regs->gpr[rb]; 982 break; 983 984 default: 985 return 0; 986 } 987 break; 988 989 case OP_LWZ: 990 regs->gpr[rd] = 0xffffffff; 991 break; 992 993 case OP_LWZU: 994 regs->gpr[rd] = 0xffffffff; 995 regs->gpr[ra] += (s16)d; 996 break; 997 998 case OP_LBZ: 999 regs->gpr[rd] = 0xff; 1000 break; 1001 1002 case OP_LBZU: 1003 regs->gpr[rd] = 0xff; 1004 regs->gpr[ra] += (s16)d; 1005 break; 1006 1007 case OP_LHZ: 1008 regs->gpr[rd] = 0xffff; 1009 break; 1010 1011 case OP_LHZU: 1012 regs->gpr[rd] = 0xffff; 1013 regs->gpr[ra] += (s16)d; 1014 break; 1015 1016 case OP_LHA: 1017 regs->gpr[rd] = ~0UL; 1018 break; 1019 1020 case OP_LHAU: 1021 regs->gpr[rd] = ~0UL; 1022 regs->gpr[ra] += (s16)d; 1023 break; 1024 1025 default: 1026 return 0; 1027 } 1028 1029 return 1; 1030 } 1031 1032 static int is_in_pci_mem_space(phys_addr_t addr) 1033 { 1034 struct pci_controller *hose; 1035 struct resource *res; 1036 int i; 1037 1038 list_for_each_entry(hose, &hose_list, list_node) { 1039 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) 1040 continue; 1041 1042 for (i = 0; i < 3; i++) { 1043 res = &hose->mem_resources[i]; 1044 if ((res->flags & IORESOURCE_MEM) && 1045 addr >= res->start && addr <= res->end) 1046 return 1; 1047 } 1048 } 1049 return 0; 1050 } 1051 1052 int fsl_pci_mcheck_exception(struct pt_regs *regs) 1053 { 1054 u32 inst; 1055 int ret; 1056 phys_addr_t addr = 0; 1057 1058 /* Let KVM/QEMU deal with the exception */ 1059 if (regs->msr & MSR_GS) 1060 return 0; 1061 1062 #ifdef CONFIG_PHYS_64BIT 1063 addr = mfspr(SPRN_MCARU); 1064 addr <<= 32; 1065 #endif 1066 addr += mfspr(SPRN_MCAR); 1067 1068 if (is_in_pci_mem_space(addr)) { 1069 if (user_mode(regs)) 1070 ret = copy_from_user_nofault(&inst, 1071 (void __user *)regs->nip, sizeof(inst)); 1072 else 1073 ret = get_kernel_nofault(inst, (void *)regs->nip); 1074 1075 if (!ret && mcheck_handle_load(regs, inst)) { 1076 regs_add_return_ip(regs, 4); 1077 return 1; 1078 } 1079 } 1080 1081 return 0; 1082 } 1083 #endif 1084 1085 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 1086 static const struct of_device_id pci_ids[] = { 1087 { .compatible = "fsl,mpc8540-pci", }, 1088 { .compatible = "fsl,mpc8548-pcie", }, 1089 { .compatible = "fsl,mpc8610-pci", }, 1090 { .compatible = "fsl,mpc8641-pcie", }, 1091 { .compatible = "fsl,qoriq-pcie", }, 1092 { .compatible = "fsl,qoriq-pcie-v2.1", }, 1093 { .compatible = "fsl,qoriq-pcie-v2.2", }, 1094 { .compatible = "fsl,qoriq-pcie-v2.3", }, 1095 { .compatible = "fsl,qoriq-pcie-v2.4", }, 1096 { .compatible = "fsl,qoriq-pcie-v3.0", }, 1097 1098 /* 1099 * The following entries are for compatibility with older device 1100 * trees. 1101 */ 1102 { .compatible = "fsl,p1022-pcie", }, 1103 { .compatible = "fsl,p4080-pcie", }, 1104 1105 {}, 1106 }; 1107 1108 struct device_node *fsl_pci_primary; 1109 1110 void __init fsl_pci_assign_primary(void) 1111 { 1112 struct device_node *np; 1113 1114 /* Callers can specify the primary bus using other means. */ 1115 if (fsl_pci_primary) 1116 return; 1117 1118 /* If a PCI host bridge contains an ISA node, it's primary. */ 1119 np = of_find_node_by_type(NULL, "isa"); 1120 while ((fsl_pci_primary = of_get_parent(np))) { 1121 of_node_put(np); 1122 np = fsl_pci_primary; 1123 1124 if (of_match_node(pci_ids, np) && of_device_is_available(np)) 1125 return; 1126 } 1127 1128 /* 1129 * If there's no PCI host bridge with ISA, arbitrarily 1130 * designate one as primary. This can go away once 1131 * various bugs with primary-less systems are fixed. 1132 */ 1133 for_each_matching_node(np, pci_ids) { 1134 if (of_device_is_available(np)) { 1135 fsl_pci_primary = np; 1136 of_node_put(np); 1137 return; 1138 } 1139 } 1140 } 1141 1142 #ifdef CONFIG_PM_SLEEP 1143 static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id) 1144 { 1145 struct pci_controller *hose = dev_id; 1146 struct ccsr_pci __iomem *pci = hose->private_data; 1147 u32 dr; 1148 1149 dr = in_be32(&pci->pex_pme_mes_dr); 1150 if (!dr) 1151 return IRQ_NONE; 1152 1153 out_be32(&pci->pex_pme_mes_dr, dr); 1154 1155 return IRQ_HANDLED; 1156 } 1157 1158 static int fsl_pci_pme_probe(struct pci_controller *hose) 1159 { 1160 struct ccsr_pci __iomem *pci; 1161 struct pci_dev *dev; 1162 int pme_irq; 1163 int res; 1164 u16 pms; 1165 1166 /* Get hose's pci_dev */ 1167 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); 1168 1169 /* PME Disable */ 1170 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1171 pms &= ~PCI_PM_CTRL_PME_ENABLE; 1172 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1173 1174 pme_irq = irq_of_parse_and_map(hose->dn, 0); 1175 if (!pme_irq) { 1176 dev_err(&dev->dev, "Failed to map PME interrupt.\n"); 1177 1178 return -ENXIO; 1179 } 1180 1181 res = devm_request_irq(hose->parent, pme_irq, 1182 fsl_pci_pme_handle, 1183 IRQF_SHARED, 1184 "[PCI] PME", hose); 1185 if (res < 0) { 1186 dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq); 1187 irq_dispose_mapping(pme_irq); 1188 1189 return -ENODEV; 1190 } 1191 1192 pci = hose->private_data; 1193 1194 /* Enable PTOD, ENL23D & EXL23D */ 1195 clrbits32(&pci->pex_pme_mes_disr, 1196 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1197 1198 out_be32(&pci->pex_pme_mes_ier, 0); 1199 setbits32(&pci->pex_pme_mes_ier, 1200 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1201 1202 /* PME Enable */ 1203 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1204 pms |= PCI_PM_CTRL_PME_ENABLE; 1205 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1206 1207 return 0; 1208 } 1209 1210 static void send_pme_turnoff_message(struct pci_controller *hose) 1211 { 1212 struct ccsr_pci __iomem *pci = hose->private_data; 1213 u32 dr; 1214 int i; 1215 1216 /* Send PME_Turn_Off Message Request */ 1217 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); 1218 1219 /* Wait trun off done */ 1220 for (i = 0; i < 150; i++) { 1221 dr = in_be32(&pci->pex_pme_mes_dr); 1222 if (dr) { 1223 out_be32(&pci->pex_pme_mes_dr, dr); 1224 break; 1225 } 1226 1227 udelay(1000); 1228 } 1229 } 1230 1231 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) 1232 { 1233 send_pme_turnoff_message(hose); 1234 } 1235 1236 static int fsl_pci_syscore_suspend(void) 1237 { 1238 struct pci_controller *hose, *tmp; 1239 1240 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1241 fsl_pci_syscore_do_suspend(hose); 1242 1243 return 0; 1244 } 1245 1246 static void fsl_pci_syscore_do_resume(struct pci_controller *hose) 1247 { 1248 struct ccsr_pci __iomem *pci = hose->private_data; 1249 u32 dr; 1250 int i; 1251 1252 /* Send Exit L2 State Message */ 1253 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); 1254 1255 /* Wait exit done */ 1256 for (i = 0; i < 150; i++) { 1257 dr = in_be32(&pci->pex_pme_mes_dr); 1258 if (dr) { 1259 out_be32(&pci->pex_pme_mes_dr, dr); 1260 break; 1261 } 1262 1263 udelay(1000); 1264 } 1265 1266 setup_pci_atmu(hose); 1267 } 1268 1269 static void fsl_pci_syscore_resume(void) 1270 { 1271 struct pci_controller *hose, *tmp; 1272 1273 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1274 fsl_pci_syscore_do_resume(hose); 1275 } 1276 1277 static struct syscore_ops pci_syscore_pm_ops = { 1278 .suspend = fsl_pci_syscore_suspend, 1279 .resume = fsl_pci_syscore_resume, 1280 }; 1281 #endif 1282 1283 void fsl_pcibios_fixup_phb(struct pci_controller *phb) 1284 { 1285 #ifdef CONFIG_PM_SLEEP 1286 fsl_pci_pme_probe(phb); 1287 #endif 1288 } 1289 1290 static int add_err_dev(struct platform_device *pdev) 1291 { 1292 struct platform_device *errdev; 1293 struct mpc85xx_edac_pci_plat_data pd = { 1294 .of_node = pdev->dev.of_node 1295 }; 1296 1297 errdev = platform_device_register_resndata(&pdev->dev, 1298 "mpc85xx-pci-edac", 1299 PLATFORM_DEVID_AUTO, 1300 pdev->resource, 1301 pdev->num_resources, 1302 &pd, sizeof(pd)); 1303 1304 return PTR_ERR_OR_ZERO(errdev); 1305 } 1306 1307 static int fsl_pci_probe(struct platform_device *pdev) 1308 { 1309 struct device_node *node; 1310 int ret; 1311 1312 node = pdev->dev.of_node; 1313 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 1314 if (ret) 1315 return ret; 1316 1317 ret = add_err_dev(pdev); 1318 if (ret) 1319 dev_err(&pdev->dev, "couldn't register error device: %d\n", 1320 ret); 1321 1322 return 0; 1323 } 1324 1325 static struct platform_driver fsl_pci_driver = { 1326 .driver = { 1327 .name = "fsl-pci", 1328 .of_match_table = pci_ids, 1329 }, 1330 .probe = fsl_pci_probe, 1331 }; 1332 1333 static int __init fsl_pci_init(void) 1334 { 1335 #ifdef CONFIG_PM_SLEEP 1336 register_syscore_ops(&pci_syscore_pm_ops); 1337 #endif 1338 return platform_driver_register(&fsl_pci_driver); 1339 } 1340 arch_initcall(fsl_pci_init); 1341 #endif 1342