1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC83xx/85xx/86xx PCI/PCIE support routing. 4 * 5 * Copyright 2007-2012 Freescale Semiconductor, Inc. 6 * Copyright 2008-2009 MontaVista Software, Inc. 7 * 8 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 9 * Recode: ZHANG WEI <wei.zhang@freescale.com> 10 * Rewrite the routing for Frescale PCI and PCI Express 11 * Roy Zang <tie-fei.zang@freescale.com> 12 * MPC83xx PCI-Express support: 13 * Tony Li <tony.li@freescale.com> 14 * Anton Vorontsov <avorontsov@ru.mvista.com> 15 */ 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/fsl/edac.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/memblock.h> 24 #include <linux/log2.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/platform_device.h> 28 #include <linux/slab.h> 29 #include <linux/suspend.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/uaccess.h> 32 33 #include <asm/io.h> 34 #include <asm/pci-bridge.h> 35 #include <asm/ppc-pci.h> 36 #include <asm/machdep.h> 37 #include <asm/mpc85xx.h> 38 #include <asm/disassemble.h> 39 #include <asm/ppc-opcode.h> 40 #include <asm/swiotlb.h> 41 #include <asm/setup.h> 42 #include <sysdev/fsl_soc.h> 43 #include <sysdev/fsl_pci.h> 44 45 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 46 47 static void quirk_fsl_pcie_early(struct pci_dev *dev) 48 { 49 u8 hdr_type; 50 51 /* if we aren't a PCIe don't bother */ 52 if (!pci_is_pcie(dev)) 53 return; 54 55 /* if we aren't in host mode don't bother */ 56 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 57 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 58 return; 59 60 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 61 fsl_pcie_bus_fixup = 1; 62 return; 63 } 64 65 static int fsl_indirect_read_config(struct pci_bus *, unsigned int, 66 int, int, u32 *); 67 68 static int fsl_pcie_check_link(struct pci_controller *hose) 69 { 70 u32 val = 0; 71 72 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { 73 if (hose->ops->read == fsl_indirect_read_config) 74 __indirect_read_config(hose, hose->first_busno, 0, 75 PCIE_LTSSM, 4, &val); 76 else 77 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 78 if (val < PCIE_LTSSM_L0) 79 return 1; 80 } else { 81 struct ccsr_pci __iomem *pci = hose->private_data; 82 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ 83 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) 84 >> PEX_CSR0_LTSSM_SHIFT; 85 if (val != PEX_CSR0_LTSSM_L0) 86 return 1; 87 } 88 89 return 0; 90 } 91 92 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, 93 int offset, int len, u32 *val) 94 { 95 struct pci_controller *hose = pci_bus_to_host(bus); 96 97 if (fsl_pcie_check_link(hose)) 98 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 99 else 100 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; 101 102 return indirect_read_config(bus, devfn, offset, len, val); 103 } 104 105 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 106 107 static struct pci_ops fsl_indirect_pcie_ops = 108 { 109 .read = fsl_indirect_read_config, 110 .write = indirect_write_config, 111 }; 112 113 static u64 pci64_dma_offset; 114 115 #ifdef CONFIG_SWIOTLB 116 static void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev) 117 { 118 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 119 120 pdev->dev.bus_dma_limit = 121 hose->dma_window_base_cur + hose->dma_window_size - 1; 122 } 123 124 static void setup_swiotlb_ops(struct pci_controller *hose) 125 { 126 if (ppc_swiotlb_enable) 127 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; 128 } 129 #else 130 static inline void setup_swiotlb_ops(struct pci_controller *hose) {} 131 #endif 132 133 static void fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) 134 { 135 /* 136 * Fix up PCI devices that are able to DMA to the large inbound 137 * mapping that allows addressing any RAM address from across PCI. 138 */ 139 if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) { 140 dev->bus_dma_limit = 0; 141 dev->archdata.dma_offset = pci64_dma_offset; 142 } 143 } 144 145 static int setup_one_atmu(struct ccsr_pci __iomem *pci, 146 unsigned int index, const struct resource *res, 147 resource_size_t offset) 148 { 149 resource_size_t pci_addr = res->start - offset; 150 resource_size_t phys_addr = res->start; 151 resource_size_t size = resource_size(res); 152 u32 flags = 0x80044000; /* enable & mem R/W */ 153 unsigned int i; 154 155 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 156 (u64)res->start, (u64)size); 157 158 if (res->flags & IORESOURCE_PREFETCH) 159 flags |= 0x10000000; /* enable relaxed ordering */ 160 161 for (i = 0; size > 0; i++) { 162 unsigned int bits = min_t(u32, ilog2(size), 163 __ffs(pci_addr | phys_addr)); 164 165 if (index + i >= 5) 166 return -1; 167 168 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 169 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 170 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 171 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 172 173 pci_addr += (resource_size_t)1U << bits; 174 phys_addr += (resource_size_t)1U << bits; 175 size -= (resource_size_t)1U << bits; 176 } 177 178 return i; 179 } 180 181 static bool is_kdump(void) 182 { 183 struct device_node *node; 184 185 node = of_find_node_by_type(NULL, "memory"); 186 if (!node) { 187 WARN_ON_ONCE(1); 188 return false; 189 } 190 191 return of_property_read_bool(node, "linux,usable-memory"); 192 } 193 194 /* atmu setup for fsl pci/pcie controller */ 195 static void setup_pci_atmu(struct pci_controller *hose) 196 { 197 struct ccsr_pci __iomem *pci = hose->private_data; 198 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 199 u64 mem, sz, paddr_hi = 0; 200 u64 offset = 0, paddr_lo = ULLONG_MAX; 201 u32 pcicsrbar = 0, pcicsrbar_sz; 202 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 203 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 204 const u64 *reg; 205 int len; 206 bool setup_inbound; 207 208 /* 209 * If this is kdump, we don't want to trigger a bunch of PCI 210 * errors by closing the window on in-flight DMA. 211 * 212 * We still run most of the function's logic so that things like 213 * hose->dma_window_size still get set. 214 */ 215 setup_inbound = !is_kdump(); 216 217 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) { 218 /* 219 * BSC9132 Rev1.0 has an issue where all the PEX inbound 220 * windows have implemented the default target value as 0xf 221 * for CCSR space.In all Freescale legacy devices the target 222 * of 0xf is reserved for local memory space. 9132 Rev1.0 223 * now has local memory space mapped to target 0x0 instead of 224 * 0xf. Hence adding a workaround to remove the target 0xf 225 * defined for memory space from Inbound window attributes. 226 */ 227 piwar &= ~PIWAR_TGI_LOCAL; 228 } 229 230 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 231 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 232 win_idx = 2; 233 start_idx = 0; 234 end_idx = 3; 235 } 236 } 237 238 /* Disable all windows (except powar0 since it's ignored) */ 239 for(i = 1; i < 5; i++) 240 out_be32(&pci->pow[i].powar, 0); 241 242 if (setup_inbound) { 243 for (i = start_idx; i < end_idx; i++) 244 out_be32(&pci->piw[i].piwar, 0); 245 } 246 247 /* Setup outbound MEM window */ 248 for(i = 0, j = 1; i < 3; i++) { 249 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 250 continue; 251 252 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 253 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 254 255 /* We assume all memory resources have the same offset */ 256 offset = hose->mem_offset[i]; 257 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); 258 259 if (n < 0 || j >= 5) { 260 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 261 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 262 } else 263 j += n; 264 } 265 266 /* Setup outbound IO window */ 267 if (hose->io_resource.flags & IORESOURCE_IO) { 268 if (j >= 5) { 269 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 270 } else { 271 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 272 "phy base 0x%016llx.\n", 273 (u64)hose->io_resource.start, 274 (u64)resource_size(&hose->io_resource), 275 (u64)hose->io_base_phys); 276 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 277 out_be32(&pci->pow[j].potear, 0); 278 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 279 /* Enable, IO R/W */ 280 out_be32(&pci->pow[j].powar, 0x80088000 281 | (ilog2(hose->io_resource.end 282 - hose->io_resource.start + 1) - 1)); 283 } 284 } 285 286 /* convert to pci address space */ 287 paddr_hi -= offset; 288 paddr_lo -= offset; 289 290 if (paddr_hi == paddr_lo) { 291 pr_err("%pOF: No outbound window space\n", hose->dn); 292 return; 293 } 294 295 if (paddr_lo == 0) { 296 pr_err("%pOF: No space for inbound window\n", hose->dn); 297 return; 298 } 299 300 /* setup PCSRBAR/PEXCSRBAR */ 301 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 302 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 303 pcicsrbar_sz = ~pcicsrbar_sz + 1; 304 305 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 306 (paddr_lo > 0x100000000ull)) 307 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 308 else 309 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 310 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 311 312 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 313 314 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar); 315 316 /* Setup inbound mem window */ 317 mem = memblock_end_of_DRAM(); 318 pr_info("%s: end of DRAM %llx\n", __func__, mem); 319 320 /* 321 * The msi-address-64 property, if it exists, indicates the physical 322 * address of the MSIIR register. Normally, this register is located 323 * inside CCSR, so the ATMU that covers all of CCSR is used. But if 324 * this property exists, then we normally need to create a new ATMU 325 * for it. For now, however, we cheat. The only entity that creates 326 * this property is the Freescale hypervisor, and the address is 327 * specified in the partition configuration. Typically, the address 328 * is located in the page immediately after the end of DDR. If so, we 329 * can avoid allocating a new ATMU by extending the DDR ATMU by one 330 * page. 331 */ 332 reg = of_get_property(hose->dn, "msi-address-64", &len); 333 if (reg && (len == sizeof(u64))) { 334 u64 address = be64_to_cpup(reg); 335 336 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { 337 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn); 338 mem += PAGE_SIZE; 339 } else { 340 /* TODO: Create a new ATMU for MSIIR */ 341 pr_warn("%pOF: msi-address-64 address of %llx is " 342 "unsupported\n", hose->dn, address); 343 } 344 } 345 346 sz = min(mem, paddr_lo); 347 mem_log = ilog2(sz); 348 349 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 350 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 351 /* Size window to exact size if power-of-two or one size up */ 352 if ((1ull << mem_log) != mem) { 353 mem_log++; 354 if ((1ull << mem_log) > mem) 355 pr_info("%pOF: Setting PCI inbound window " 356 "greater than memory size\n", hose->dn); 357 } 358 359 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 360 361 if (setup_inbound) { 362 /* Setup inbound memory window */ 363 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 364 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 365 out_be32(&pci->piw[win_idx].piwar, piwar); 366 } 367 368 win_idx--; 369 hose->dma_window_base_cur = 0x00000000; 370 hose->dma_window_size = (resource_size_t)sz; 371 372 /* 373 * if we have >4G of memory setup second PCI inbound window to 374 * let devices that are 64-bit address capable to work w/o 375 * SWIOTLB and access the full range of memory 376 */ 377 if (sz != mem) { 378 mem_log = ilog2(mem); 379 380 /* Size window up if we dont fit in exact power-of-2 */ 381 if ((1ull << mem_log) != mem) 382 mem_log++; 383 384 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); 385 pci64_dma_offset = 1ULL << mem_log; 386 387 if (setup_inbound) { 388 /* Setup inbound memory window */ 389 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 390 out_be32(&pci->piw[win_idx].piwbear, 391 pci64_dma_offset >> 44); 392 out_be32(&pci->piw[win_idx].piwbar, 393 pci64_dma_offset >> 12); 394 out_be32(&pci->piw[win_idx].piwar, piwar); 395 } 396 397 /* 398 * install our own dma_set_mask handler to fixup dma_ops 399 * and dma_offset 400 */ 401 ppc_md.dma_set_mask = fsl_pci_dma_set_mask; 402 403 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn); 404 } 405 } else { 406 u64 paddr = 0; 407 408 if (setup_inbound) { 409 /* Setup inbound memory window */ 410 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 411 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 412 out_be32(&pci->piw[win_idx].piwar, 413 (piwar | (mem_log - 1))); 414 } 415 416 win_idx--; 417 paddr += 1ull << mem_log; 418 sz -= 1ull << mem_log; 419 420 if (sz) { 421 mem_log = ilog2(sz); 422 piwar |= (mem_log - 1); 423 424 if (setup_inbound) { 425 out_be32(&pci->piw[win_idx].pitar, 426 paddr >> 12); 427 out_be32(&pci->piw[win_idx].piwbar, 428 paddr >> 12); 429 out_be32(&pci->piw[win_idx].piwar, piwar); 430 } 431 432 win_idx--; 433 paddr += 1ull << mem_log; 434 } 435 436 hose->dma_window_base_cur = 0x00000000; 437 hose->dma_window_size = (resource_size_t)paddr; 438 } 439 440 if (hose->dma_window_size < mem) { 441 #ifdef CONFIG_SWIOTLB 442 ppc_swiotlb_enable = 1; 443 #else 444 pr_err("%pOF: ERROR: Memory size exceeds PCI ATMU ability to " 445 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 446 hose->dn); 447 #endif 448 /* adjusting outbound windows could reclaim space in mem map */ 449 if (paddr_hi < 0xffffffffull) 450 pr_warn("%pOF: WARNING: Outbound window cfg leaves " 451 "gaps in memory map. Adjusting the memory map " 452 "could reduce unnecessary bounce buffering.\n", 453 hose->dn); 454 455 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn, 456 (u64)hose->dma_window_size); 457 } 458 } 459 460 static void setup_pci_cmd(struct pci_controller *hose) 461 { 462 u16 cmd; 463 int cap_x; 464 465 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 466 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 467 | PCI_COMMAND_IO; 468 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 469 470 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 471 if (cap_x) { 472 int pci_x_cmd = cap_x + PCI_X_CMD; 473 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 474 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 475 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 476 } else { 477 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 478 } 479 } 480 481 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 482 { 483 struct pci_controller *hose = pci_bus_to_host(bus); 484 int i, is_pcie = 0, no_link; 485 486 /* The root complex bridge comes up with bogus resources, 487 * we copy the PHB ones in. 488 * 489 * With the current generic PCI code, the PHB bus no longer 490 * has bus->resource[0..4] set, so things are a bit more 491 * tricky. 492 */ 493 494 if (fsl_pcie_bus_fixup) 495 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 496 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); 497 498 if (bus->parent == hose->bus && (is_pcie || no_link)) { 499 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { 500 struct resource *res = bus->resource[i]; 501 struct resource *par; 502 503 if (!res) 504 continue; 505 if (i == 0) 506 par = &hose->io_resource; 507 else if (i < 4) 508 par = &hose->mem_resources[i-1]; 509 else par = NULL; 510 511 res->start = par ? par->start : 0; 512 res->end = par ? par->end : 0; 513 res->flags = par ? par->flags : 0; 514 } 515 } 516 } 517 518 int fsl_add_bridge(struct platform_device *pdev, int is_primary) 519 { 520 int len; 521 struct pci_controller *hose; 522 struct resource rsrc; 523 const int *bus_range; 524 u8 hdr_type, progif; 525 struct device_node *dev; 526 struct ccsr_pci __iomem *pci; 527 u16 temp; 528 u32 svr = mfspr(SPRN_SVR); 529 530 dev = pdev->dev.of_node; 531 532 if (!of_device_is_available(dev)) { 533 pr_warn("%pOF: disabled\n", dev); 534 return -ENODEV; 535 } 536 537 pr_debug("Adding PCI host bridge %pOF\n", dev); 538 539 /* Fetch host bridge registers address */ 540 if (of_address_to_resource(dev, 0, &rsrc)) { 541 printk(KERN_WARNING "Can't get pci register base!"); 542 return -ENOMEM; 543 } 544 545 /* Get bus range if any */ 546 bus_range = of_get_property(dev, "bus-range", &len); 547 if (bus_range == NULL || len < 2 * sizeof(int)) 548 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" 549 " bus 0\n", dev); 550 551 pci_add_flags(PCI_REASSIGN_ALL_BUS); 552 hose = pcibios_alloc_controller(dev); 553 if (!hose) 554 return -ENOMEM; 555 556 /* set platform device as the parent */ 557 hose->parent = &pdev->dev; 558 hose->first_busno = bus_range ? bus_range[0] : 0x0; 559 hose->last_busno = bus_range ? bus_range[1] : 0xff; 560 561 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 562 (u64)rsrc.start, (u64)resource_size(&rsrc)); 563 564 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); 565 if (!hose->private_data) 566 goto no_bridge; 567 568 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 569 PPC_INDIRECT_TYPE_BIG_ENDIAN); 570 571 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) 572 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 573 574 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 575 /* use fsl_indirect_read_config for PCIe */ 576 hose->ops = &fsl_indirect_pcie_ops; 577 /* For PCIE read HEADER_TYPE to identify controller mode */ 578 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); 579 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 580 goto no_bridge; 581 582 } else { 583 /* For PCI read PROG to identify controller mode */ 584 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 585 if ((progif & 1) && 586 !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) 587 goto no_bridge; 588 } 589 590 setup_pci_cmd(hose); 591 592 /* check PCI express link status */ 593 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 594 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 595 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 596 if (fsl_pcie_check_link(hose)) 597 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 598 } else { 599 /* 600 * Set PBFR(PCI Bus Function Register)[10] = 1 to 601 * disable the combining of crossing cacheline 602 * boundary requests into one burst transaction. 603 * PCI-X operation is not affected. 604 * Fix erratum PCI 5 on MPC8548 605 */ 606 #define PCI_BUS_FUNCTION 0x44 607 #define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */ 608 if (((SVR_SOC_VER(svr) == SVR_8543) || 609 (SVR_SOC_VER(svr) == SVR_8545) || 610 (SVR_SOC_VER(svr) == SVR_8547) || 611 (SVR_SOC_VER(svr) == SVR_8548)) && 612 !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) { 613 early_read_config_word(hose, 0, 0, 614 PCI_BUS_FUNCTION, &temp); 615 temp |= PCI_BUS_FUNCTION_MDS; 616 early_write_config_word(hose, 0, 0, 617 PCI_BUS_FUNCTION, temp); 618 } 619 } 620 621 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 622 "Firmware bus number: %d->%d\n", 623 (unsigned long long)rsrc.start, hose->first_busno, 624 hose->last_busno); 625 626 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 627 hose, hose->cfg_addr, hose->cfg_data); 628 629 /* Interpret the "ranges" property */ 630 /* This also maps the I/O region and sets isa_io/mem_base */ 631 pci_process_bridge_OF_ranges(hose, dev, is_primary); 632 633 /* Setup PEX window registers */ 634 setup_pci_atmu(hose); 635 636 /* Set up controller operations */ 637 setup_swiotlb_ops(hose); 638 639 return 0; 640 641 no_bridge: 642 iounmap(hose->private_data); 643 /* unmap cfg_data & cfg_addr separately if not on same page */ 644 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 645 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 646 iounmap(hose->cfg_data); 647 iounmap(hose->cfg_addr); 648 pcibios_free_controller(hose); 649 return -ENODEV; 650 } 651 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 652 653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 654 quirk_fsl_pcie_early); 655 656 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 657 struct mpc83xx_pcie_priv { 658 void __iomem *cfg_type0; 659 void __iomem *cfg_type1; 660 u32 dev_base; 661 }; 662 663 struct pex_inbound_window { 664 u32 ar; 665 u32 tar; 666 u32 barl; 667 u32 barh; 668 }; 669 670 /* 671 * With the convention of u-boot, the PCIE outbound window 0 serves 672 * as configuration transactions outbound. 673 */ 674 #define PEX_OUTWIN0_BAR 0xCA4 675 #define PEX_OUTWIN0_TAL 0xCA8 676 #define PEX_OUTWIN0_TAH 0xCAC 677 #define PEX_RC_INWIN_BASE 0xE60 678 #define PEX_RCIWARn_EN 0x1 679 680 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 681 { 682 struct pci_controller *hose = pci_bus_to_host(bus); 683 684 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 685 return PCIBIOS_DEVICE_NOT_FOUND; 686 /* 687 * Workaround for the HW bug: for Type 0 configure transactions the 688 * PCI-E controller does not check the device number bits and just 689 * assumes that the device number bits are 0. 690 */ 691 if (bus->number == hose->first_busno || 692 bus->primary == hose->first_busno) { 693 if (devfn & 0xf8) 694 return PCIBIOS_DEVICE_NOT_FOUND; 695 } 696 697 if (ppc_md.pci_exclude_device) { 698 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 699 return PCIBIOS_DEVICE_NOT_FOUND; 700 } 701 702 return PCIBIOS_SUCCESSFUL; 703 } 704 705 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 706 unsigned int devfn, int offset) 707 { 708 struct pci_controller *hose = pci_bus_to_host(bus); 709 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 710 u32 dev_base = bus->number << 24 | devfn << 16; 711 int ret; 712 713 ret = mpc83xx_pcie_exclude_device(bus, devfn); 714 if (ret) 715 return NULL; 716 717 offset &= 0xfff; 718 719 /* Type 0 */ 720 if (bus->number == hose->first_busno) 721 return pcie->cfg_type0 + offset; 722 723 if (pcie->dev_base == dev_base) 724 goto mapped; 725 726 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 727 728 pcie->dev_base = dev_base; 729 mapped: 730 return pcie->cfg_type1 + offset; 731 } 732 733 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 734 int offset, int len, u32 val) 735 { 736 struct pci_controller *hose = pci_bus_to_host(bus); 737 738 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 739 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 740 val &= 0xffffff00; 741 742 return pci_generic_config_write(bus, devfn, offset, len, val); 743 } 744 745 static struct pci_ops mpc83xx_pcie_ops = { 746 .map_bus = mpc83xx_pcie_remap_cfg, 747 .read = pci_generic_config_read, 748 .write = mpc83xx_pcie_write_config, 749 }; 750 751 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 752 struct resource *reg) 753 { 754 struct mpc83xx_pcie_priv *pcie; 755 u32 cfg_bar; 756 int ret = -ENOMEM; 757 758 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 759 if (!pcie) 760 return ret; 761 762 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 763 if (!pcie->cfg_type0) 764 goto err0; 765 766 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 767 if (!cfg_bar) { 768 /* PCI-E isn't configured. */ 769 ret = -ENODEV; 770 goto err1; 771 } 772 773 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 774 if (!pcie->cfg_type1) 775 goto err1; 776 777 WARN_ON(hose->dn->data); 778 hose->dn->data = pcie; 779 hose->ops = &mpc83xx_pcie_ops; 780 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 781 782 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 783 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 784 785 if (fsl_pcie_check_link(hose)) 786 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 787 788 return 0; 789 err1: 790 iounmap(pcie->cfg_type0); 791 err0: 792 kfree(pcie); 793 return ret; 794 795 } 796 797 int __init mpc83xx_add_bridge(struct device_node *dev) 798 { 799 int ret; 800 int len; 801 struct pci_controller *hose; 802 struct resource rsrc_reg; 803 struct resource rsrc_cfg; 804 const int *bus_range; 805 int primary; 806 807 is_mpc83xx_pci = 1; 808 809 if (!of_device_is_available(dev)) { 810 pr_warn("%pOF: disabled by the firmware.\n", 811 dev); 812 return -ENODEV; 813 } 814 pr_debug("Adding PCI host bridge %pOF\n", dev); 815 816 /* Fetch host bridge registers address */ 817 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 818 printk(KERN_WARNING "Can't get pci register base!\n"); 819 return -ENOMEM; 820 } 821 822 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 823 824 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 825 printk(KERN_WARNING 826 "No pci config register base in dev tree, " 827 "using default\n"); 828 /* 829 * MPC83xx supports up to two host controllers 830 * one at 0x8500 has config space registers at 0x8300 831 * one at 0x8600 has config space registers at 0x8380 832 */ 833 if ((rsrc_reg.start & 0xfffff) == 0x8500) 834 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 835 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 836 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 837 } 838 /* 839 * Controller at offset 0x8500 is primary 840 */ 841 if ((rsrc_reg.start & 0xfffff) == 0x8500) 842 primary = 1; 843 else 844 primary = 0; 845 846 /* Get bus range if any */ 847 bus_range = of_get_property(dev, "bus-range", &len); 848 if (bus_range == NULL || len < 2 * sizeof(int)) { 849 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" 850 " bus 0\n", dev); 851 } 852 853 pci_add_flags(PCI_REASSIGN_ALL_BUS); 854 hose = pcibios_alloc_controller(dev); 855 if (!hose) 856 return -ENOMEM; 857 858 hose->first_busno = bus_range ? bus_range[0] : 0; 859 hose->last_busno = bus_range ? bus_range[1] : 0xff; 860 861 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 862 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 863 if (ret) 864 goto err0; 865 } else { 866 setup_indirect_pci(hose, rsrc_cfg.start, 867 rsrc_cfg.start + 4, 0); 868 } 869 870 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 871 "Firmware bus number: %d->%d\n", 872 (unsigned long long)rsrc_reg.start, hose->first_busno, 873 hose->last_busno); 874 875 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 876 hose, hose->cfg_addr, hose->cfg_data); 877 878 /* Interpret the "ranges" property */ 879 /* This also maps the I/O region and sets isa_io/mem_base */ 880 pci_process_bridge_OF_ranges(hose, dev, primary); 881 882 return 0; 883 err0: 884 pcibios_free_controller(hose); 885 return ret; 886 } 887 #endif /* CONFIG_PPC_83xx */ 888 889 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 890 { 891 #ifdef CONFIG_PPC_83xx 892 if (is_mpc83xx_pci) { 893 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 894 struct pex_inbound_window *in; 895 int i; 896 897 /* Walk the Root Complex Inbound windows to match IMMR base */ 898 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 899 for (i = 0; i < 4; i++) { 900 /* not enabled, skip */ 901 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN)) 902 continue; 903 904 if (get_immrbase() == in_le32(&in[i].tar)) 905 return (u64)in_le32(&in[i].barh) << 32 | 906 in_le32(&in[i].barl); 907 } 908 909 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 910 } 911 #endif 912 913 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 914 if (!is_mpc83xx_pci) { 915 u32 base; 916 917 pci_bus_read_config_dword(hose->bus, 918 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 919 920 /* 921 * For PEXCSRBAR, bit 3-0 indicate prefetchable and 922 * address type. So when getting base address, these 923 * bits should be masked 924 */ 925 base &= PCI_BASE_ADDRESS_MEM_MASK; 926 927 return base; 928 } 929 #endif 930 931 return 0; 932 } 933 934 #ifdef CONFIG_E500 935 static int mcheck_handle_load(struct pt_regs *regs, u32 inst) 936 { 937 unsigned int rd, ra, rb, d; 938 939 rd = get_rt(inst); 940 ra = get_ra(inst); 941 rb = get_rb(inst); 942 d = get_d(inst); 943 944 switch (get_op(inst)) { 945 case 31: 946 switch (get_xop(inst)) { 947 case OP_31_XOP_LWZX: 948 case OP_31_XOP_LWBRX: 949 regs->gpr[rd] = 0xffffffff; 950 break; 951 952 case OP_31_XOP_LWZUX: 953 regs->gpr[rd] = 0xffffffff; 954 regs->gpr[ra] += regs->gpr[rb]; 955 break; 956 957 case OP_31_XOP_LBZX: 958 regs->gpr[rd] = 0xff; 959 break; 960 961 case OP_31_XOP_LBZUX: 962 regs->gpr[rd] = 0xff; 963 regs->gpr[ra] += regs->gpr[rb]; 964 break; 965 966 case OP_31_XOP_LHZX: 967 case OP_31_XOP_LHBRX: 968 regs->gpr[rd] = 0xffff; 969 break; 970 971 case OP_31_XOP_LHZUX: 972 regs->gpr[rd] = 0xffff; 973 regs->gpr[ra] += regs->gpr[rb]; 974 break; 975 976 case OP_31_XOP_LHAX: 977 regs->gpr[rd] = ~0UL; 978 break; 979 980 case OP_31_XOP_LHAUX: 981 regs->gpr[rd] = ~0UL; 982 regs->gpr[ra] += regs->gpr[rb]; 983 break; 984 985 default: 986 return 0; 987 } 988 break; 989 990 case OP_LWZ: 991 regs->gpr[rd] = 0xffffffff; 992 break; 993 994 case OP_LWZU: 995 regs->gpr[rd] = 0xffffffff; 996 regs->gpr[ra] += (s16)d; 997 break; 998 999 case OP_LBZ: 1000 regs->gpr[rd] = 0xff; 1001 break; 1002 1003 case OP_LBZU: 1004 regs->gpr[rd] = 0xff; 1005 regs->gpr[ra] += (s16)d; 1006 break; 1007 1008 case OP_LHZ: 1009 regs->gpr[rd] = 0xffff; 1010 break; 1011 1012 case OP_LHZU: 1013 regs->gpr[rd] = 0xffff; 1014 regs->gpr[ra] += (s16)d; 1015 break; 1016 1017 case OP_LHA: 1018 regs->gpr[rd] = ~0UL; 1019 break; 1020 1021 case OP_LHAU: 1022 regs->gpr[rd] = ~0UL; 1023 regs->gpr[ra] += (s16)d; 1024 break; 1025 1026 default: 1027 return 0; 1028 } 1029 1030 return 1; 1031 } 1032 1033 static int is_in_pci_mem_space(phys_addr_t addr) 1034 { 1035 struct pci_controller *hose; 1036 struct resource *res; 1037 int i; 1038 1039 list_for_each_entry(hose, &hose_list, list_node) { 1040 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) 1041 continue; 1042 1043 for (i = 0; i < 3; i++) { 1044 res = &hose->mem_resources[i]; 1045 if ((res->flags & IORESOURCE_MEM) && 1046 addr >= res->start && addr <= res->end) 1047 return 1; 1048 } 1049 } 1050 return 0; 1051 } 1052 1053 int fsl_pci_mcheck_exception(struct pt_regs *regs) 1054 { 1055 u32 inst; 1056 int ret; 1057 phys_addr_t addr = 0; 1058 1059 /* Let KVM/QEMU deal with the exception */ 1060 if (regs->msr & MSR_GS) 1061 return 0; 1062 1063 #ifdef CONFIG_PHYS_64BIT 1064 addr = mfspr(SPRN_MCARU); 1065 addr <<= 32; 1066 #endif 1067 addr += mfspr(SPRN_MCAR); 1068 1069 if (is_in_pci_mem_space(addr)) { 1070 if (user_mode(regs)) 1071 ret = copy_from_user_nofault(&inst, 1072 (void __user *)regs->nip, sizeof(inst)); 1073 else 1074 ret = get_kernel_nofault(inst, (void *)regs->nip); 1075 1076 if (!ret && mcheck_handle_load(regs, inst)) { 1077 regs_add_return_ip(regs, 4); 1078 return 1; 1079 } 1080 } 1081 1082 return 0; 1083 } 1084 #endif 1085 1086 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 1087 static const struct of_device_id pci_ids[] = { 1088 { .compatible = "fsl,mpc8540-pci", }, 1089 { .compatible = "fsl,mpc8548-pcie", }, 1090 { .compatible = "fsl,mpc8610-pci", }, 1091 { .compatible = "fsl,mpc8641-pcie", }, 1092 { .compatible = "fsl,qoriq-pcie", }, 1093 { .compatible = "fsl,qoriq-pcie-v2.1", }, 1094 { .compatible = "fsl,qoriq-pcie-v2.2", }, 1095 { .compatible = "fsl,qoriq-pcie-v2.3", }, 1096 { .compatible = "fsl,qoriq-pcie-v2.4", }, 1097 { .compatible = "fsl,qoriq-pcie-v3.0", }, 1098 1099 /* 1100 * The following entries are for compatibility with older device 1101 * trees. 1102 */ 1103 { .compatible = "fsl,p1022-pcie", }, 1104 { .compatible = "fsl,p4080-pcie", }, 1105 1106 {}, 1107 }; 1108 1109 struct device_node *fsl_pci_primary; 1110 1111 void __init fsl_pci_assign_primary(void) 1112 { 1113 struct device_node *np; 1114 1115 /* Callers can specify the primary bus using other means. */ 1116 if (fsl_pci_primary) 1117 return; 1118 1119 /* If a PCI host bridge contains an ISA node, it's primary. */ 1120 np = of_find_node_by_type(NULL, "isa"); 1121 while ((fsl_pci_primary = of_get_parent(np))) { 1122 of_node_put(np); 1123 np = fsl_pci_primary; 1124 1125 if (of_match_node(pci_ids, np) && of_device_is_available(np)) 1126 return; 1127 } 1128 1129 /* 1130 * If there's no PCI host bridge with ISA, arbitrarily 1131 * designate one as primary. This can go away once 1132 * various bugs with primary-less systems are fixed. 1133 */ 1134 for_each_matching_node(np, pci_ids) { 1135 if (of_device_is_available(np)) { 1136 fsl_pci_primary = np; 1137 of_node_put(np); 1138 return; 1139 } 1140 } 1141 } 1142 1143 #ifdef CONFIG_PM_SLEEP 1144 static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id) 1145 { 1146 struct pci_controller *hose = dev_id; 1147 struct ccsr_pci __iomem *pci = hose->private_data; 1148 u32 dr; 1149 1150 dr = in_be32(&pci->pex_pme_mes_dr); 1151 if (!dr) 1152 return IRQ_NONE; 1153 1154 out_be32(&pci->pex_pme_mes_dr, dr); 1155 1156 return IRQ_HANDLED; 1157 } 1158 1159 static int fsl_pci_pme_probe(struct pci_controller *hose) 1160 { 1161 struct ccsr_pci __iomem *pci; 1162 struct pci_dev *dev; 1163 int pme_irq; 1164 int res; 1165 u16 pms; 1166 1167 /* Get hose's pci_dev */ 1168 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); 1169 1170 /* PME Disable */ 1171 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1172 pms &= ~PCI_PM_CTRL_PME_ENABLE; 1173 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1174 1175 pme_irq = irq_of_parse_and_map(hose->dn, 0); 1176 if (!pme_irq) { 1177 dev_err(&dev->dev, "Failed to map PME interrupt.\n"); 1178 1179 return -ENXIO; 1180 } 1181 1182 res = devm_request_irq(hose->parent, pme_irq, 1183 fsl_pci_pme_handle, 1184 IRQF_SHARED, 1185 "[PCI] PME", hose); 1186 if (res < 0) { 1187 dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq); 1188 irq_dispose_mapping(pme_irq); 1189 1190 return -ENODEV; 1191 } 1192 1193 pci = hose->private_data; 1194 1195 /* Enable PTOD, ENL23D & EXL23D */ 1196 clrbits32(&pci->pex_pme_mes_disr, 1197 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1198 1199 out_be32(&pci->pex_pme_mes_ier, 0); 1200 setbits32(&pci->pex_pme_mes_ier, 1201 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1202 1203 /* PME Enable */ 1204 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1205 pms |= PCI_PM_CTRL_PME_ENABLE; 1206 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1207 1208 return 0; 1209 } 1210 1211 static void send_pme_turnoff_message(struct pci_controller *hose) 1212 { 1213 struct ccsr_pci __iomem *pci = hose->private_data; 1214 u32 dr; 1215 int i; 1216 1217 /* Send PME_Turn_Off Message Request */ 1218 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); 1219 1220 /* Wait trun off done */ 1221 for (i = 0; i < 150; i++) { 1222 dr = in_be32(&pci->pex_pme_mes_dr); 1223 if (dr) { 1224 out_be32(&pci->pex_pme_mes_dr, dr); 1225 break; 1226 } 1227 1228 udelay(1000); 1229 } 1230 } 1231 1232 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) 1233 { 1234 send_pme_turnoff_message(hose); 1235 } 1236 1237 static int fsl_pci_syscore_suspend(void) 1238 { 1239 struct pci_controller *hose, *tmp; 1240 1241 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1242 fsl_pci_syscore_do_suspend(hose); 1243 1244 return 0; 1245 } 1246 1247 static void fsl_pci_syscore_do_resume(struct pci_controller *hose) 1248 { 1249 struct ccsr_pci __iomem *pci = hose->private_data; 1250 u32 dr; 1251 int i; 1252 1253 /* Send Exit L2 State Message */ 1254 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); 1255 1256 /* Wait exit done */ 1257 for (i = 0; i < 150; i++) { 1258 dr = in_be32(&pci->pex_pme_mes_dr); 1259 if (dr) { 1260 out_be32(&pci->pex_pme_mes_dr, dr); 1261 break; 1262 } 1263 1264 udelay(1000); 1265 } 1266 1267 setup_pci_atmu(hose); 1268 } 1269 1270 static void fsl_pci_syscore_resume(void) 1271 { 1272 struct pci_controller *hose, *tmp; 1273 1274 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1275 fsl_pci_syscore_do_resume(hose); 1276 } 1277 1278 static struct syscore_ops pci_syscore_pm_ops = { 1279 .suspend = fsl_pci_syscore_suspend, 1280 .resume = fsl_pci_syscore_resume, 1281 }; 1282 #endif 1283 1284 void fsl_pcibios_fixup_phb(struct pci_controller *phb) 1285 { 1286 #ifdef CONFIG_PM_SLEEP 1287 fsl_pci_pme_probe(phb); 1288 #endif 1289 } 1290 1291 static int add_err_dev(struct platform_device *pdev) 1292 { 1293 struct platform_device *errdev; 1294 struct mpc85xx_edac_pci_plat_data pd = { 1295 .of_node = pdev->dev.of_node 1296 }; 1297 1298 errdev = platform_device_register_resndata(&pdev->dev, 1299 "mpc85xx-pci-edac", 1300 PLATFORM_DEVID_AUTO, 1301 pdev->resource, 1302 pdev->num_resources, 1303 &pd, sizeof(pd)); 1304 1305 return PTR_ERR_OR_ZERO(errdev); 1306 } 1307 1308 static int fsl_pci_probe(struct platform_device *pdev) 1309 { 1310 struct device_node *node; 1311 int ret; 1312 1313 node = pdev->dev.of_node; 1314 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 1315 if (ret) 1316 return ret; 1317 1318 ret = add_err_dev(pdev); 1319 if (ret) 1320 dev_err(&pdev->dev, "couldn't register error device: %d\n", 1321 ret); 1322 1323 return 0; 1324 } 1325 1326 static struct platform_driver fsl_pci_driver = { 1327 .driver = { 1328 .name = "fsl-pci", 1329 .of_match_table = pci_ids, 1330 }, 1331 .probe = fsl_pci_probe, 1332 }; 1333 1334 static int __init fsl_pci_init(void) 1335 { 1336 #ifdef CONFIG_PM_SLEEP 1337 register_syscore_ops(&pci_syscore_pm_ops); 1338 #endif 1339 return platform_driver_register(&fsl_pci_driver); 1340 } 1341 arch_initcall(fsl_pci_init); 1342 #endif 1343