1 /* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2012 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/bootmem.h> 26 #include <linux/memblock.h> 27 #include <linux/log2.h> 28 #include <linux/slab.h> 29 30 #include <asm/io.h> 31 #include <asm/prom.h> 32 #include <asm/pci-bridge.h> 33 #include <asm/machdep.h> 34 #include <sysdev/fsl_soc.h> 35 #include <sysdev/fsl_pci.h> 36 37 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 38 39 static void quirk_fsl_pcie_header(struct pci_dev *dev) 40 { 41 u8 hdr_type; 42 43 /* if we aren't a PCIe don't bother */ 44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 45 return; 46 47 /* if we aren't in host mode don't bother */ 48 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 49 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 50 return; 51 52 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 53 fsl_pcie_bus_fixup = 1; 54 return; 55 } 56 57 static int __init fsl_pcie_check_link(struct pci_controller *hose) 58 { 59 u32 val; 60 61 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 62 if (val < PCIE_LTSSM_L0) 63 return 1; 64 return 0; 65 } 66 67 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 68 69 #define MAX_PHYS_ADDR_BITS 40 70 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; 71 72 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) 73 { 74 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 75 return -EIO; 76 77 /* 78 * Fixup PCI devices that are able to DMA to above the physical 79 * address width of the SoC such that we can address any internal 80 * SoC address from across PCI if needed 81 */ 82 if ((dev->bus == &pci_bus_type) && 83 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) { 84 set_dma_ops(dev, &dma_direct_ops); 85 set_dma_offset(dev, pci64_dma_offset); 86 } 87 88 *dev->dma_mask = dma_mask; 89 return 0; 90 } 91 92 static int setup_one_atmu(struct ccsr_pci __iomem *pci, 93 unsigned int index, const struct resource *res, 94 resource_size_t offset) 95 { 96 resource_size_t pci_addr = res->start - offset; 97 resource_size_t phys_addr = res->start; 98 resource_size_t size = resource_size(res); 99 u32 flags = 0x80044000; /* enable & mem R/W */ 100 unsigned int i; 101 102 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 103 (u64)res->start, (u64)size); 104 105 if (res->flags & IORESOURCE_PREFETCH) 106 flags |= 0x10000000; /* enable relaxed ordering */ 107 108 for (i = 0; size > 0; i++) { 109 unsigned int bits = min(__ilog2(size), 110 __ffs(pci_addr | phys_addr)); 111 112 if (index + i >= 5) 113 return -1; 114 115 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 116 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 117 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 118 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 119 120 pci_addr += (resource_size_t)1U << bits; 121 phys_addr += (resource_size_t)1U << bits; 122 size -= (resource_size_t)1U << bits; 123 } 124 125 return i; 126 } 127 128 /* atmu setup for fsl pci/pcie controller */ 129 static void setup_pci_atmu(struct pci_controller *hose, 130 struct resource *rsrc) 131 { 132 struct ccsr_pci __iomem *pci; 133 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 134 u64 mem, sz, paddr_hi = 0; 135 u64 paddr_lo = ULLONG_MAX; 136 u32 pcicsrbar = 0, pcicsrbar_sz; 137 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 138 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 139 const char *name = hose->dn->full_name; 140 const u64 *reg; 141 int len; 142 143 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 144 (u64)rsrc->start, (u64)resource_size(rsrc)); 145 146 pci = ioremap(rsrc->start, resource_size(rsrc)); 147 if (!pci) { 148 dev_err(hose->parent, "Unable to map ATMU registers\n"); 149 return; 150 } 151 152 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 153 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 154 win_idx = 2; 155 start_idx = 0; 156 end_idx = 3; 157 } 158 } 159 160 /* Disable all windows (except powar0 since it's ignored) */ 161 for(i = 1; i < 5; i++) 162 out_be32(&pci->pow[i].powar, 0); 163 for (i = start_idx; i < end_idx; i++) 164 out_be32(&pci->piw[i].piwar, 0); 165 166 /* Setup outbound MEM window */ 167 for(i = 0, j = 1; i < 3; i++) { 168 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 169 continue; 170 171 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 172 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 173 174 n = setup_one_atmu(pci, j, &hose->mem_resources[i], 175 hose->pci_mem_offset); 176 177 if (n < 0 || j >= 5) { 178 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 179 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 180 } else 181 j += n; 182 } 183 184 /* Setup outbound IO window */ 185 if (hose->io_resource.flags & IORESOURCE_IO) { 186 if (j >= 5) { 187 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 188 } else { 189 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 190 "phy base 0x%016llx.\n", 191 (u64)hose->io_resource.start, 192 (u64)resource_size(&hose->io_resource), 193 (u64)hose->io_base_phys); 194 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 195 out_be32(&pci->pow[j].potear, 0); 196 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 197 /* Enable, IO R/W */ 198 out_be32(&pci->pow[j].powar, 0x80088000 199 | (__ilog2(hose->io_resource.end 200 - hose->io_resource.start + 1) - 1)); 201 } 202 } 203 204 /* convert to pci address space */ 205 paddr_hi -= hose->pci_mem_offset; 206 paddr_lo -= hose->pci_mem_offset; 207 208 if (paddr_hi == paddr_lo) { 209 pr_err("%s: No outbound window space\n", name); 210 goto out; 211 } 212 213 if (paddr_lo == 0) { 214 pr_err("%s: No space for inbound window\n", name); 215 goto out; 216 } 217 218 /* setup PCSRBAR/PEXCSRBAR */ 219 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 220 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 221 pcicsrbar_sz = ~pcicsrbar_sz + 1; 222 223 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 224 (paddr_lo > 0x100000000ull)) 225 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 226 else 227 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 228 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 229 230 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 231 232 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); 233 234 /* Setup inbound mem window */ 235 mem = memblock_end_of_DRAM(); 236 237 /* 238 * The msi-address-64 property, if it exists, indicates the physical 239 * address of the MSIIR register. Normally, this register is located 240 * inside CCSR, so the ATMU that covers all of CCSR is used. But if 241 * this property exists, then we normally need to create a new ATMU 242 * for it. For now, however, we cheat. The only entity that creates 243 * this property is the Freescale hypervisor, and the address is 244 * specified in the partition configuration. Typically, the address 245 * is located in the page immediately after the end of DDR. If so, we 246 * can avoid allocating a new ATMU by extending the DDR ATMU by one 247 * page. 248 */ 249 reg = of_get_property(hose->dn, "msi-address-64", &len); 250 if (reg && (len == sizeof(u64))) { 251 u64 address = be64_to_cpup(reg); 252 253 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { 254 pr_info("%s: extending DDR ATMU to cover MSIIR", name); 255 mem += PAGE_SIZE; 256 } else { 257 /* TODO: Create a new ATMU for MSIIR */ 258 pr_warn("%s: msi-address-64 address of %llx is " 259 "unsupported\n", name, address); 260 } 261 } 262 263 sz = min(mem, paddr_lo); 264 mem_log = __ilog2_u64(sz); 265 266 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 267 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 268 /* Size window to exact size if power-of-two or one size up */ 269 if ((1ull << mem_log) != mem) { 270 if ((1ull << mem_log) > mem) 271 pr_info("%s: Setting PCI inbound window " 272 "greater than memory size\n", name); 273 mem_log++; 274 } 275 276 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 277 278 /* Setup inbound memory window */ 279 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 280 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 281 out_be32(&pci->piw[win_idx].piwar, piwar); 282 win_idx--; 283 284 hose->dma_window_base_cur = 0x00000000; 285 hose->dma_window_size = (resource_size_t)sz; 286 287 /* 288 * if we have >4G of memory setup second PCI inbound window to 289 * let devices that are 64-bit address capable to work w/o 290 * SWIOTLB and access the full range of memory 291 */ 292 if (sz != mem) { 293 mem_log = __ilog2_u64(mem); 294 295 /* Size window up if we dont fit in exact power-of-2 */ 296 if ((1ull << mem_log) != mem) 297 mem_log++; 298 299 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); 300 301 /* Setup inbound memory window */ 302 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 303 out_be32(&pci->piw[win_idx].piwbear, 304 pci64_dma_offset >> 44); 305 out_be32(&pci->piw[win_idx].piwbar, 306 pci64_dma_offset >> 12); 307 out_be32(&pci->piw[win_idx].piwar, piwar); 308 309 /* 310 * install our own dma_set_mask handler to fixup dma_ops 311 * and dma_offset 312 */ 313 ppc_md.dma_set_mask = fsl_pci_dma_set_mask; 314 315 pr_info("%s: Setup 64-bit PCI DMA window\n", name); 316 } 317 } else { 318 u64 paddr = 0; 319 320 /* Setup inbound memory window */ 321 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 322 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 323 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); 324 win_idx--; 325 326 paddr += 1ull << mem_log; 327 sz -= 1ull << mem_log; 328 329 if (sz) { 330 mem_log = __ilog2_u64(sz); 331 piwar |= (mem_log - 1); 332 333 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 334 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 335 out_be32(&pci->piw[win_idx].piwar, piwar); 336 win_idx--; 337 338 paddr += 1ull << mem_log; 339 } 340 341 hose->dma_window_base_cur = 0x00000000; 342 hose->dma_window_size = (resource_size_t)paddr; 343 } 344 345 if (hose->dma_window_size < mem) { 346 #ifndef CONFIG_SWIOTLB 347 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 348 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 349 name); 350 #endif 351 /* adjusting outbound windows could reclaim space in mem map */ 352 if (paddr_hi < 0xffffffffull) 353 pr_warning("%s: WARNING: Outbound window cfg leaves " 354 "gaps in memory map. Adjusting the memory map " 355 "could reduce unnecessary bounce buffering.\n", 356 name); 357 358 pr_info("%s: DMA window size is 0x%llx\n", name, 359 (u64)hose->dma_window_size); 360 } 361 362 out: 363 iounmap(pci); 364 } 365 366 static void __init setup_pci_cmd(struct pci_controller *hose) 367 { 368 u16 cmd; 369 int cap_x; 370 371 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 372 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 373 | PCI_COMMAND_IO; 374 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 375 376 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 377 if (cap_x) { 378 int pci_x_cmd = cap_x + PCI_X_CMD; 379 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 380 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 381 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 382 } else { 383 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 384 } 385 } 386 387 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 388 { 389 struct pci_controller *hose = pci_bus_to_host(bus); 390 int i, is_pcie = 0, no_link; 391 392 /* The root complex bridge comes up with bogus resources, 393 * we copy the PHB ones in. 394 * 395 * With the current generic PCI code, the PHB bus no longer 396 * has bus->resource[0..4] set, so things are a bit more 397 * tricky. 398 */ 399 400 if (fsl_pcie_bus_fixup) 401 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 402 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); 403 404 if (bus->parent == hose->bus && (is_pcie || no_link)) { 405 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { 406 struct resource *res = bus->resource[i]; 407 struct resource *par; 408 409 if (!res) 410 continue; 411 if (i == 0) 412 par = &hose->io_resource; 413 else if (i < 4) 414 par = &hose->mem_resources[i-1]; 415 else par = NULL; 416 417 res->start = par ? par->start : 0; 418 res->end = par ? par->end : 0; 419 res->flags = par ? par->flags : 0; 420 } 421 } 422 } 423 424 int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) 425 { 426 int len; 427 struct pci_controller *hose; 428 struct resource rsrc; 429 const int *bus_range; 430 u8 hdr_type, progif; 431 struct device_node *dev; 432 433 dev = pdev->dev.of_node; 434 435 if (!of_device_is_available(dev)) { 436 pr_warning("%s: disabled\n", dev->full_name); 437 return -ENODEV; 438 } 439 440 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 441 442 /* Fetch host bridge registers address */ 443 if (of_address_to_resource(dev, 0, &rsrc)) { 444 printk(KERN_WARNING "Can't get pci register base!"); 445 return -ENOMEM; 446 } 447 448 /* Get bus range if any */ 449 bus_range = of_get_property(dev, "bus-range", &len); 450 if (bus_range == NULL || len < 2 * sizeof(int)) 451 printk(KERN_WARNING "Can't get bus-range for %s, assume" 452 " bus 0\n", dev->full_name); 453 454 pci_add_flags(PCI_REASSIGN_ALL_BUS); 455 hose = pcibios_alloc_controller(dev); 456 if (!hose) 457 return -ENOMEM; 458 459 /* set platform device as the parent */ 460 hose->parent = &pdev->dev; 461 hose->first_busno = bus_range ? bus_range[0] : 0x0; 462 hose->last_busno = bus_range ? bus_range[1] : 0xff; 463 464 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 465 PPC_INDIRECT_TYPE_BIG_ENDIAN); 466 467 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 468 /* For PCIE read HEADER_TYPE to identify controler mode */ 469 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); 470 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 471 goto no_bridge; 472 473 } else { 474 /* For PCI read PROG to identify controller mode */ 475 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 476 if ((progif & 1) == 1) 477 goto no_bridge; 478 } 479 480 setup_pci_cmd(hose); 481 482 /* check PCI express link status */ 483 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 484 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 485 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 486 if (fsl_pcie_check_link(hose)) 487 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 488 } 489 490 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 491 "Firmware bus number: %d->%d\n", 492 (unsigned long long)rsrc.start, hose->first_busno, 493 hose->last_busno); 494 495 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 496 hose, hose->cfg_addr, hose->cfg_data); 497 498 /* Interpret the "ranges" property */ 499 /* This also maps the I/O region and sets isa_io/mem_base */ 500 pci_process_bridge_OF_ranges(hose, dev, is_primary); 501 502 /* Setup PEX window registers */ 503 setup_pci_atmu(hose, &rsrc); 504 505 return 0; 506 507 no_bridge: 508 /* unmap cfg_data & cfg_addr separately if not on same page */ 509 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 510 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 511 iounmap(hose->cfg_data); 512 iounmap(hose->cfg_addr); 513 pcibios_free_controller(hose); 514 return -ENODEV; 515 } 516 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 517 518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header); 519 520 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 521 struct mpc83xx_pcie_priv { 522 void __iomem *cfg_type0; 523 void __iomem *cfg_type1; 524 u32 dev_base; 525 }; 526 527 struct pex_inbound_window { 528 u32 ar; 529 u32 tar; 530 u32 barl; 531 u32 barh; 532 }; 533 534 /* 535 * With the convention of u-boot, the PCIE outbound window 0 serves 536 * as configuration transactions outbound. 537 */ 538 #define PEX_OUTWIN0_BAR 0xCA4 539 #define PEX_OUTWIN0_TAL 0xCA8 540 #define PEX_OUTWIN0_TAH 0xCAC 541 #define PEX_RC_INWIN_BASE 0xE60 542 #define PEX_RCIWARn_EN 0x1 543 544 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 545 { 546 struct pci_controller *hose = pci_bus_to_host(bus); 547 548 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 549 return PCIBIOS_DEVICE_NOT_FOUND; 550 /* 551 * Workaround for the HW bug: for Type 0 configure transactions the 552 * PCI-E controller does not check the device number bits and just 553 * assumes that the device number bits are 0. 554 */ 555 if (bus->number == hose->first_busno || 556 bus->primary == hose->first_busno) { 557 if (devfn & 0xf8) 558 return PCIBIOS_DEVICE_NOT_FOUND; 559 } 560 561 if (ppc_md.pci_exclude_device) { 562 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 563 return PCIBIOS_DEVICE_NOT_FOUND; 564 } 565 566 return PCIBIOS_SUCCESSFUL; 567 } 568 569 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 570 unsigned int devfn, int offset) 571 { 572 struct pci_controller *hose = pci_bus_to_host(bus); 573 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 574 u32 dev_base = bus->number << 24 | devfn << 16; 575 int ret; 576 577 ret = mpc83xx_pcie_exclude_device(bus, devfn); 578 if (ret) 579 return NULL; 580 581 offset &= 0xfff; 582 583 /* Type 0 */ 584 if (bus->number == hose->first_busno) 585 return pcie->cfg_type0 + offset; 586 587 if (pcie->dev_base == dev_base) 588 goto mapped; 589 590 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 591 592 pcie->dev_base = dev_base; 593 mapped: 594 return pcie->cfg_type1 + offset; 595 } 596 597 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 598 int offset, int len, u32 *val) 599 { 600 void __iomem *cfg_addr; 601 602 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 603 if (!cfg_addr) 604 return PCIBIOS_DEVICE_NOT_FOUND; 605 606 switch (len) { 607 case 1: 608 *val = in_8(cfg_addr); 609 break; 610 case 2: 611 *val = in_le16(cfg_addr); 612 break; 613 default: 614 *val = in_le32(cfg_addr); 615 break; 616 } 617 618 return PCIBIOS_SUCCESSFUL; 619 } 620 621 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 622 int offset, int len, u32 val) 623 { 624 struct pci_controller *hose = pci_bus_to_host(bus); 625 void __iomem *cfg_addr; 626 627 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 628 if (!cfg_addr) 629 return PCIBIOS_DEVICE_NOT_FOUND; 630 631 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 632 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 633 val &= 0xffffff00; 634 635 switch (len) { 636 case 1: 637 out_8(cfg_addr, val); 638 break; 639 case 2: 640 out_le16(cfg_addr, val); 641 break; 642 default: 643 out_le32(cfg_addr, val); 644 break; 645 } 646 647 return PCIBIOS_SUCCESSFUL; 648 } 649 650 static struct pci_ops mpc83xx_pcie_ops = { 651 .read = mpc83xx_pcie_read_config, 652 .write = mpc83xx_pcie_write_config, 653 }; 654 655 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 656 struct resource *reg) 657 { 658 struct mpc83xx_pcie_priv *pcie; 659 u32 cfg_bar; 660 int ret = -ENOMEM; 661 662 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 663 if (!pcie) 664 return ret; 665 666 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 667 if (!pcie->cfg_type0) 668 goto err0; 669 670 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 671 if (!cfg_bar) { 672 /* PCI-E isn't configured. */ 673 ret = -ENODEV; 674 goto err1; 675 } 676 677 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 678 if (!pcie->cfg_type1) 679 goto err1; 680 681 WARN_ON(hose->dn->data); 682 hose->dn->data = pcie; 683 hose->ops = &mpc83xx_pcie_ops; 684 685 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 686 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 687 688 if (fsl_pcie_check_link(hose)) 689 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 690 691 return 0; 692 err1: 693 iounmap(pcie->cfg_type0); 694 err0: 695 kfree(pcie); 696 return ret; 697 698 } 699 700 int __init mpc83xx_add_bridge(struct device_node *dev) 701 { 702 int ret; 703 int len; 704 struct pci_controller *hose; 705 struct resource rsrc_reg; 706 struct resource rsrc_cfg; 707 const int *bus_range; 708 int primary; 709 710 is_mpc83xx_pci = 1; 711 712 if (!of_device_is_available(dev)) { 713 pr_warning("%s: disabled by the firmware.\n", 714 dev->full_name); 715 return -ENODEV; 716 } 717 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 718 719 /* Fetch host bridge registers address */ 720 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 721 printk(KERN_WARNING "Can't get pci register base!\n"); 722 return -ENOMEM; 723 } 724 725 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 726 727 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 728 printk(KERN_WARNING 729 "No pci config register base in dev tree, " 730 "using default\n"); 731 /* 732 * MPC83xx supports up to two host controllers 733 * one at 0x8500 has config space registers at 0x8300 734 * one at 0x8600 has config space registers at 0x8380 735 */ 736 if ((rsrc_reg.start & 0xfffff) == 0x8500) 737 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 738 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 739 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 740 } 741 /* 742 * Controller at offset 0x8500 is primary 743 */ 744 if ((rsrc_reg.start & 0xfffff) == 0x8500) 745 primary = 1; 746 else 747 primary = 0; 748 749 /* Get bus range if any */ 750 bus_range = of_get_property(dev, "bus-range", &len); 751 if (bus_range == NULL || len < 2 * sizeof(int)) { 752 printk(KERN_WARNING "Can't get bus-range for %s, assume" 753 " bus 0\n", dev->full_name); 754 } 755 756 pci_add_flags(PCI_REASSIGN_ALL_BUS); 757 hose = pcibios_alloc_controller(dev); 758 if (!hose) 759 return -ENOMEM; 760 761 hose->first_busno = bus_range ? bus_range[0] : 0; 762 hose->last_busno = bus_range ? bus_range[1] : 0xff; 763 764 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 765 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 766 if (ret) 767 goto err0; 768 } else { 769 setup_indirect_pci(hose, rsrc_cfg.start, 770 rsrc_cfg.start + 4, 0); 771 } 772 773 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 774 "Firmware bus number: %d->%d\n", 775 (unsigned long long)rsrc_reg.start, hose->first_busno, 776 hose->last_busno); 777 778 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 779 hose, hose->cfg_addr, hose->cfg_data); 780 781 /* Interpret the "ranges" property */ 782 /* This also maps the I/O region and sets isa_io/mem_base */ 783 pci_process_bridge_OF_ranges(hose, dev, primary); 784 785 return 0; 786 err0: 787 pcibios_free_controller(hose); 788 return ret; 789 } 790 #endif /* CONFIG_PPC_83xx */ 791 792 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 793 { 794 #ifdef CONFIG_PPC_83xx 795 if (is_mpc83xx_pci) { 796 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 797 struct pex_inbound_window *in; 798 int i; 799 800 /* Walk the Root Complex Inbound windows to match IMMR base */ 801 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 802 for (i = 0; i < 4; i++) { 803 /* not enabled, skip */ 804 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN) 805 continue; 806 807 if (get_immrbase() == in_le32(&in[i].tar)) 808 return (u64)in_le32(&in[i].barh) << 32 | 809 in_le32(&in[i].barl); 810 } 811 812 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 813 } 814 #endif 815 816 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 817 if (!is_mpc83xx_pci) { 818 u32 base; 819 820 pci_bus_read_config_dword(hose->bus, 821 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 822 return base; 823 } 824 #endif 825 826 return 0; 827 } 828 829 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 830 static const struct of_device_id pci_ids[] = { 831 { .compatible = "fsl,mpc8540-pci", }, 832 { .compatible = "fsl,mpc8548-pcie", }, 833 { .compatible = "fsl,mpc8610-pci", }, 834 { .compatible = "fsl,mpc8641-pcie", }, 835 { .compatible = "fsl,qoriq-pcie-v2.1", }, 836 { .compatible = "fsl,qoriq-pcie-v2.2", }, 837 { .compatible = "fsl,qoriq-pcie-v2.3", }, 838 { .compatible = "fsl,qoriq-pcie-v2.4", }, 839 840 /* 841 * The following entries are for compatibility with older device 842 * trees. 843 */ 844 { .compatible = "fsl,p1022-pcie", }, 845 { .compatible = "fsl,p4080-pcie", }, 846 847 {}, 848 }; 849 850 struct device_node *fsl_pci_primary; 851 852 void fsl_pci_assign_primary(void) 853 { 854 struct device_node *np; 855 856 /* Callers can specify the primary bus using other means. */ 857 if (fsl_pci_primary) 858 return; 859 860 /* If a PCI host bridge contains an ISA node, it's primary. */ 861 np = of_find_node_by_type(NULL, "isa"); 862 while ((fsl_pci_primary = of_get_parent(np))) { 863 of_node_put(np); 864 np = fsl_pci_primary; 865 866 if (of_match_node(pci_ids, np) && of_device_is_available(np)) 867 return; 868 } 869 870 /* 871 * If there's no PCI host bridge with ISA, arbitrarily 872 * designate one as primary. This can go away once 873 * various bugs with primary-less systems are fixed. 874 */ 875 for_each_matching_node(np, pci_ids) { 876 if (of_device_is_available(np)) { 877 fsl_pci_primary = np; 878 of_node_put(np); 879 return; 880 } 881 } 882 } 883 884 static int fsl_pci_probe(struct platform_device *pdev) 885 { 886 int ret; 887 struct device_node *node; 888 #ifdef CONFIG_SWIOTLB 889 struct pci_controller *hose; 890 #endif 891 892 node = pdev->dev.of_node; 893 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 894 895 #ifdef CONFIG_SWIOTLB 896 if (ret == 0) { 897 hose = pci_find_hose_for_OF_device(pdev->dev.of_node); 898 899 /* 900 * if we couldn't map all of DRAM via the dma windows 901 * we need SWIOTLB to handle buffers located outside of 902 * dma capable memory region 903 */ 904 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur + 905 hose->dma_window_size) 906 ppc_swiotlb_enable = 1; 907 } 908 #endif 909 910 mpc85xx_pci_err_probe(pdev); 911 912 return 0; 913 } 914 915 #ifdef CONFIG_PM 916 static int fsl_pci_resume(struct device *dev) 917 { 918 struct pci_controller *hose; 919 struct resource pci_rsrc; 920 921 hose = pci_find_hose_for_OF_device(dev->of_node); 922 if (!hose) 923 return -ENODEV; 924 925 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) { 926 dev_err(dev, "Get pci register base failed."); 927 return -ENODEV; 928 } 929 930 setup_pci_atmu(hose, &pci_rsrc); 931 932 return 0; 933 } 934 935 static const struct dev_pm_ops pci_pm_ops = { 936 .resume = fsl_pci_resume, 937 }; 938 939 #define PCI_PM_OPS (&pci_pm_ops) 940 941 #else 942 943 #define PCI_PM_OPS NULL 944 945 #endif 946 947 static struct platform_driver fsl_pci_driver = { 948 .driver = { 949 .name = "fsl-pci", 950 .pm = PCI_PM_OPS, 951 .of_match_table = pci_ids, 952 }, 953 .probe = fsl_pci_probe, 954 }; 955 956 static int __init fsl_pci_init(void) 957 { 958 return platform_driver_register(&fsl_pci_driver); 959 } 960 arch_initcall(fsl_pci_init); 961 #endif 962