1 /* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2011 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/bootmem.h> 26 #include <linux/memblock.h> 27 #include <linux/log2.h> 28 #include <linux/slab.h> 29 30 #include <asm/io.h> 31 #include <asm/prom.h> 32 #include <asm/pci-bridge.h> 33 #include <asm/machdep.h> 34 #include <sysdev/fsl_soc.h> 35 #include <sysdev/fsl_pci.h> 36 37 static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 38 39 static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 40 { 41 /* if we aren't a PCIe don't bother */ 42 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 43 return; 44 45 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 46 fsl_pcie_bus_fixup = 1; 47 return; 48 } 49 50 static int __init fsl_pcie_check_link(struct pci_controller *hose) 51 { 52 u32 val; 53 54 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 55 if (val < PCIE_LTSSM_L0) 56 return 1; 57 return 0; 58 } 59 60 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 61 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, 62 unsigned int index, const struct resource *res, 63 resource_size_t offset) 64 { 65 resource_size_t pci_addr = res->start - offset; 66 resource_size_t phys_addr = res->start; 67 resource_size_t size = res->end - res->start + 1; 68 u32 flags = 0x80044000; /* enable & mem R/W */ 69 unsigned int i; 70 71 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 72 (u64)res->start, (u64)size); 73 74 if (res->flags & IORESOURCE_PREFETCH) 75 flags |= 0x10000000; /* enable relaxed ordering */ 76 77 for (i = 0; size > 0; i++) { 78 unsigned int bits = min(__ilog2(size), 79 __ffs(pci_addr | phys_addr)); 80 81 if (index + i >= 5) 82 return -1; 83 84 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 85 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 86 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 87 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 88 89 pci_addr += (resource_size_t)1U << bits; 90 phys_addr += (resource_size_t)1U << bits; 91 size -= (resource_size_t)1U << bits; 92 } 93 94 return i; 95 } 96 97 /* atmu setup for fsl pci/pcie controller */ 98 static void __init setup_pci_atmu(struct pci_controller *hose, 99 struct resource *rsrc) 100 { 101 struct ccsr_pci __iomem *pci; 102 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 103 u64 mem, sz, paddr_hi = 0; 104 u64 paddr_lo = ULLONG_MAX; 105 u32 pcicsrbar = 0, pcicsrbar_sz; 106 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 107 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 108 char *name = hose->dn->full_name; 109 110 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 111 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); 112 113 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) { 114 win_idx = 2; 115 start_idx = 0; 116 end_idx = 3; 117 } 118 119 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 120 if (!pci) { 121 dev_err(hose->parent, "Unable to map ATMU registers\n"); 122 return; 123 } 124 125 /* Disable all windows (except powar0 since it's ignored) */ 126 for(i = 1; i < 5; i++) 127 out_be32(&pci->pow[i].powar, 0); 128 for (i = start_idx; i < end_idx; i++) 129 out_be32(&pci->piw[i].piwar, 0); 130 131 /* Setup outbound MEM window */ 132 for(i = 0, j = 1; i < 3; i++) { 133 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 134 continue; 135 136 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 137 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 138 139 n = setup_one_atmu(pci, j, &hose->mem_resources[i], 140 hose->pci_mem_offset); 141 142 if (n < 0 || j >= 5) { 143 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 144 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 145 } else 146 j += n; 147 } 148 149 /* Setup outbound IO window */ 150 if (hose->io_resource.flags & IORESOURCE_IO) { 151 if (j >= 5) { 152 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 153 } else { 154 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 155 "phy base 0x%016llx.\n", 156 (u64)hose->io_resource.start, 157 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1, 158 (u64)hose->io_base_phys); 159 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 160 out_be32(&pci->pow[j].potear, 0); 161 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 162 /* Enable, IO R/W */ 163 out_be32(&pci->pow[j].powar, 0x80088000 164 | (__ilog2(hose->io_resource.end 165 - hose->io_resource.start + 1) - 1)); 166 } 167 } 168 169 /* convert to pci address space */ 170 paddr_hi -= hose->pci_mem_offset; 171 paddr_lo -= hose->pci_mem_offset; 172 173 if (paddr_hi == paddr_lo) { 174 pr_err("%s: No outbound window space\n", name); 175 return ; 176 } 177 178 if (paddr_lo == 0) { 179 pr_err("%s: No space for inbound window\n", name); 180 return ; 181 } 182 183 /* setup PCSRBAR/PEXCSRBAR */ 184 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 185 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 186 pcicsrbar_sz = ~pcicsrbar_sz + 1; 187 188 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 189 (paddr_lo > 0x100000000ull)) 190 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 191 else 192 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 193 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 194 195 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 196 197 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); 198 199 /* Setup inbound mem window */ 200 mem = memblock_end_of_DRAM(); 201 sz = min(mem, paddr_lo); 202 mem_log = __ilog2_u64(sz); 203 204 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 205 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 206 /* Size window to exact size if power-of-two or one size up */ 207 if ((1ull << mem_log) != mem) { 208 if ((1ull << mem_log) > mem) 209 pr_info("%s: Setting PCI inbound window " 210 "greater than memory size\n", name); 211 mem_log++; 212 } 213 214 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 215 216 /* Setup inbound memory window */ 217 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 218 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 219 out_be32(&pci->piw[win_idx].piwar, piwar); 220 win_idx--; 221 222 hose->dma_window_base_cur = 0x00000000; 223 hose->dma_window_size = (resource_size_t)sz; 224 } else { 225 u64 paddr = 0; 226 227 /* Setup inbound memory window */ 228 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 229 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 230 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); 231 win_idx--; 232 233 paddr += 1ull << mem_log; 234 sz -= 1ull << mem_log; 235 236 if (sz) { 237 mem_log = __ilog2_u64(sz); 238 piwar |= (mem_log - 1); 239 240 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 241 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 242 out_be32(&pci->piw[win_idx].piwar, piwar); 243 win_idx--; 244 245 paddr += 1ull << mem_log; 246 } 247 248 hose->dma_window_base_cur = 0x00000000; 249 hose->dma_window_size = (resource_size_t)paddr; 250 } 251 252 if (hose->dma_window_size < mem) { 253 #ifndef CONFIG_SWIOTLB 254 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 255 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 256 name); 257 #endif 258 /* adjusting outbound windows could reclaim space in mem map */ 259 if (paddr_hi < 0xffffffffull) 260 pr_warning("%s: WARNING: Outbound window cfg leaves " 261 "gaps in memory map. Adjusting the memory map " 262 "could reduce unnecessary bounce buffering.\n", 263 name); 264 265 pr_info("%s: DMA window size is 0x%llx\n", name, 266 (u64)hose->dma_window_size); 267 } 268 269 iounmap(pci); 270 } 271 272 static void __init setup_pci_cmd(struct pci_controller *hose) 273 { 274 u16 cmd; 275 int cap_x; 276 277 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 278 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 279 | PCI_COMMAND_IO; 280 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 281 282 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 283 if (cap_x) { 284 int pci_x_cmd = cap_x + PCI_X_CMD; 285 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 286 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 287 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 288 } else { 289 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 290 } 291 } 292 293 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 294 { 295 struct pci_controller *hose = pci_bus_to_host(bus); 296 int i; 297 298 if ((bus->parent == hose->bus) && 299 ((fsl_pcie_bus_fixup && 300 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) || 301 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK))) 302 { 303 for (i = 0; i < 4; ++i) { 304 struct resource *res = bus->resource[i]; 305 struct resource *par = bus->parent->resource[i]; 306 if (res) { 307 res->start = 0; 308 res->end = 0; 309 res->flags = 0; 310 } 311 if (res && par) { 312 res->start = par->start; 313 res->end = par->end; 314 res->flags = par->flags; 315 } 316 } 317 } 318 } 319 320 int __init fsl_add_bridge(struct device_node *dev, int is_primary) 321 { 322 int len; 323 struct pci_controller *hose; 324 struct resource rsrc; 325 const int *bus_range; 326 327 if (!of_device_is_available(dev)) { 328 pr_warning("%s: disabled\n", dev->full_name); 329 return -ENODEV; 330 } 331 332 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 333 334 /* Fetch host bridge registers address */ 335 if (of_address_to_resource(dev, 0, &rsrc)) { 336 printk(KERN_WARNING "Can't get pci register base!"); 337 return -ENOMEM; 338 } 339 340 /* Get bus range if any */ 341 bus_range = of_get_property(dev, "bus-range", &len); 342 if (bus_range == NULL || len < 2 * sizeof(int)) 343 printk(KERN_WARNING "Can't get bus-range for %s, assume" 344 " bus 0\n", dev->full_name); 345 346 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 347 hose = pcibios_alloc_controller(dev); 348 if (!hose) 349 return -ENOMEM; 350 351 hose->first_busno = bus_range ? bus_range[0] : 0x0; 352 hose->last_busno = bus_range ? bus_range[1] : 0xff; 353 354 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 355 PPC_INDIRECT_TYPE_BIG_ENDIAN); 356 setup_pci_cmd(hose); 357 358 /* check PCI express link status */ 359 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 360 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 361 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 362 if (fsl_pcie_check_link(hose)) 363 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 364 } 365 366 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 367 "Firmware bus number: %d->%d\n", 368 (unsigned long long)rsrc.start, hose->first_busno, 369 hose->last_busno); 370 371 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 372 hose, hose->cfg_addr, hose->cfg_data); 373 374 /* Interpret the "ranges" property */ 375 /* This also maps the I/O region and sets isa_io/mem_base */ 376 pci_process_bridge_OF_ranges(hose, dev, is_primary); 377 378 /* Setup PEX window registers */ 379 setup_pci_atmu(hose, &rsrc); 380 381 return 0; 382 } 383 384 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header); 385 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header); 386 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header); 387 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header); 388 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); 389 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); 390 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); 391 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header); 392 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header); 393 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); 394 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); 395 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); 396 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header); 397 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header); 398 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header); 399 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header); 400 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header); 401 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header); 402 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header); 403 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header); 404 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); 405 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); 406 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); 407 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); 408 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header); 409 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header); 410 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header); 411 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header); 412 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header); 413 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header); 414 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header); 415 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header); 416 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header); 417 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header); 418 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header); 419 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header); 420 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); 421 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); 422 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header); 423 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header); 424 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header); 425 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header); 426 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header); 427 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header); 428 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header); 429 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header); 430 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header); 431 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header); 432 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header); 433 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header); 434 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 435 436 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 437 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header); 438 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header); 439 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header); 440 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header); 441 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header); 442 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header); 443 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header); 444 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header); 445 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header); 446 447 struct mpc83xx_pcie_priv { 448 void __iomem *cfg_type0; 449 void __iomem *cfg_type1; 450 u32 dev_base; 451 }; 452 453 struct pex_inbound_window { 454 u32 ar; 455 u32 tar; 456 u32 barl; 457 u32 barh; 458 }; 459 460 /* 461 * With the convention of u-boot, the PCIE outbound window 0 serves 462 * as configuration transactions outbound. 463 */ 464 #define PEX_OUTWIN0_BAR 0xCA4 465 #define PEX_OUTWIN0_TAL 0xCA8 466 #define PEX_OUTWIN0_TAH 0xCAC 467 #define PEX_RC_INWIN_BASE 0xE60 468 #define PEX_RCIWARn_EN 0x1 469 470 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 471 { 472 struct pci_controller *hose = pci_bus_to_host(bus); 473 474 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 475 return PCIBIOS_DEVICE_NOT_FOUND; 476 /* 477 * Workaround for the HW bug: for Type 0 configure transactions the 478 * PCI-E controller does not check the device number bits and just 479 * assumes that the device number bits are 0. 480 */ 481 if (bus->number == hose->first_busno || 482 bus->primary == hose->first_busno) { 483 if (devfn & 0xf8) 484 return PCIBIOS_DEVICE_NOT_FOUND; 485 } 486 487 if (ppc_md.pci_exclude_device) { 488 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 489 return PCIBIOS_DEVICE_NOT_FOUND; 490 } 491 492 return PCIBIOS_SUCCESSFUL; 493 } 494 495 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 496 unsigned int devfn, int offset) 497 { 498 struct pci_controller *hose = pci_bus_to_host(bus); 499 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 500 u32 dev_base = bus->number << 24 | devfn << 16; 501 int ret; 502 503 ret = mpc83xx_pcie_exclude_device(bus, devfn); 504 if (ret) 505 return NULL; 506 507 offset &= 0xfff; 508 509 /* Type 0 */ 510 if (bus->number == hose->first_busno) 511 return pcie->cfg_type0 + offset; 512 513 if (pcie->dev_base == dev_base) 514 goto mapped; 515 516 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 517 518 pcie->dev_base = dev_base; 519 mapped: 520 return pcie->cfg_type1 + offset; 521 } 522 523 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 524 int offset, int len, u32 *val) 525 { 526 void __iomem *cfg_addr; 527 528 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 529 if (!cfg_addr) 530 return PCIBIOS_DEVICE_NOT_FOUND; 531 532 switch (len) { 533 case 1: 534 *val = in_8(cfg_addr); 535 break; 536 case 2: 537 *val = in_le16(cfg_addr); 538 break; 539 default: 540 *val = in_le32(cfg_addr); 541 break; 542 } 543 544 return PCIBIOS_SUCCESSFUL; 545 } 546 547 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 548 int offset, int len, u32 val) 549 { 550 struct pci_controller *hose = pci_bus_to_host(bus); 551 void __iomem *cfg_addr; 552 553 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); 554 if (!cfg_addr) 555 return PCIBIOS_DEVICE_NOT_FOUND; 556 557 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 558 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 559 val &= 0xffffff00; 560 561 switch (len) { 562 case 1: 563 out_8(cfg_addr, val); 564 break; 565 case 2: 566 out_le16(cfg_addr, val); 567 break; 568 default: 569 out_le32(cfg_addr, val); 570 break; 571 } 572 573 return PCIBIOS_SUCCESSFUL; 574 } 575 576 static struct pci_ops mpc83xx_pcie_ops = { 577 .read = mpc83xx_pcie_read_config, 578 .write = mpc83xx_pcie_write_config, 579 }; 580 581 static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 582 struct resource *reg) 583 { 584 struct mpc83xx_pcie_priv *pcie; 585 u32 cfg_bar; 586 int ret = -ENOMEM; 587 588 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 589 if (!pcie) 590 return ret; 591 592 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 593 if (!pcie->cfg_type0) 594 goto err0; 595 596 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 597 if (!cfg_bar) { 598 /* PCI-E isn't configured. */ 599 ret = -ENODEV; 600 goto err1; 601 } 602 603 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 604 if (!pcie->cfg_type1) 605 goto err1; 606 607 WARN_ON(hose->dn->data); 608 hose->dn->data = pcie; 609 hose->ops = &mpc83xx_pcie_ops; 610 611 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 612 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 613 614 if (fsl_pcie_check_link(hose)) 615 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 616 617 return 0; 618 err1: 619 iounmap(pcie->cfg_type0); 620 err0: 621 kfree(pcie); 622 return ret; 623 624 } 625 626 int __init mpc83xx_add_bridge(struct device_node *dev) 627 { 628 int ret; 629 int len; 630 struct pci_controller *hose; 631 struct resource rsrc_reg; 632 struct resource rsrc_cfg; 633 const int *bus_range; 634 int primary; 635 636 is_mpc83xx_pci = 1; 637 638 if (!of_device_is_available(dev)) { 639 pr_warning("%s: disabled by the firmware.\n", 640 dev->full_name); 641 return -ENODEV; 642 } 643 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 644 645 /* Fetch host bridge registers address */ 646 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 647 printk(KERN_WARNING "Can't get pci register base!\n"); 648 return -ENOMEM; 649 } 650 651 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 652 653 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 654 printk(KERN_WARNING 655 "No pci config register base in dev tree, " 656 "using default\n"); 657 /* 658 * MPC83xx supports up to two host controllers 659 * one at 0x8500 has config space registers at 0x8300 660 * one at 0x8600 has config space registers at 0x8380 661 */ 662 if ((rsrc_reg.start & 0xfffff) == 0x8500) 663 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 664 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 665 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 666 } 667 /* 668 * Controller at offset 0x8500 is primary 669 */ 670 if ((rsrc_reg.start & 0xfffff) == 0x8500) 671 primary = 1; 672 else 673 primary = 0; 674 675 /* Get bus range if any */ 676 bus_range = of_get_property(dev, "bus-range", &len); 677 if (bus_range == NULL || len < 2 * sizeof(int)) { 678 printk(KERN_WARNING "Can't get bus-range for %s, assume" 679 " bus 0\n", dev->full_name); 680 } 681 682 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 683 hose = pcibios_alloc_controller(dev); 684 if (!hose) 685 return -ENOMEM; 686 687 hose->first_busno = bus_range ? bus_range[0] : 0; 688 hose->last_busno = bus_range ? bus_range[1] : 0xff; 689 690 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 691 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 692 if (ret) 693 goto err0; 694 } else { 695 setup_indirect_pci(hose, rsrc_cfg.start, 696 rsrc_cfg.start + 4, 0); 697 } 698 699 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 700 "Firmware bus number: %d->%d\n", 701 (unsigned long long)rsrc_reg.start, hose->first_busno, 702 hose->last_busno); 703 704 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 705 hose, hose->cfg_addr, hose->cfg_data); 706 707 /* Interpret the "ranges" property */ 708 /* This also maps the I/O region and sets isa_io/mem_base */ 709 pci_process_bridge_OF_ranges(hose, dev, primary); 710 711 return 0; 712 err0: 713 pcibios_free_controller(hose); 714 return ret; 715 } 716 #endif /* CONFIG_PPC_83xx */ 717 718 u64 fsl_pci_immrbar_base(struct pci_controller *hose) 719 { 720 #ifdef CONFIG_PPC_83xx 721 if (is_mpc83xx_pci) { 722 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 723 struct pex_inbound_window *in; 724 int i; 725 726 /* Walk the Root Complex Inbound windows to match IMMR base */ 727 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 728 for (i = 0; i < 4; i++) { 729 /* not enabled, skip */ 730 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN) 731 continue; 732 733 if (get_immrbase() == in_le32(&in[i].tar)) 734 return (u64)in_le32(&in[i].barh) << 32 | 735 in_le32(&in[i].barl); 736 } 737 738 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 739 } 740 #endif 741 742 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 743 if (!is_mpc83xx_pci) { 744 u32 base; 745 746 pci_bus_read_config_dword(hose->bus, 747 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 748 return base; 749 } 750 #endif 751 752 return 0; 753 } 754