1 /* 2 * MPC85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007 Freescale Semiconductor, Inc 5 * 6 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 7 * Recode: ZHANG WEI <wei.zhang@freescale.com> 8 * Rewrite the routing for Frescale PCI and PCI Express 9 * Roy Zang <tie-fei.zang@freescale.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/init.h> 21 #include <linux/bootmem.h> 22 23 #include <asm/io.h> 24 #include <asm/prom.h> 25 #include <asm/pci-bridge.h> 26 #include <asm/machdep.h> 27 #include <sysdev/fsl_soc.h> 28 #include <sysdev/fsl_pci.h> 29 30 /* atmu setup for fsl pci/pcie controller */ 31 void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) 32 { 33 struct ccsr_pci __iomem *pci; 34 int i; 35 36 pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start, 37 rsrc->end - rsrc->start + 1); 38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 39 40 /* Disable all windows (except powar0 since its ignored) */ 41 for(i = 1; i < 5; i++) 42 out_be32(&pci->pow[i].powar, 0); 43 for(i = 0; i < 3; i++) 44 out_be32(&pci->piw[i].piwar, 0); 45 46 /* Setup outbound MEM window */ 47 for(i = 0; i < 3; i++) 48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){ 49 pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n", 50 hose->mem_resources[i].start, 51 hose->mem_resources[i].end 52 - hose->mem_resources[i].start + 1); 53 out_be32(&pci->pow[i+1].potar, 54 (hose->mem_resources[i].start >> 12) 55 & 0x000fffff); 56 out_be32(&pci->pow[i+1].potear, 0); 57 out_be32(&pci->pow[i+1].powbar, 58 (hose->mem_resources[i].start >> 12) 59 & 0x000fffff); 60 /* Enable, Mem R/W */ 61 out_be32(&pci->pow[i+1].powar, 0x80044000 62 | (__ilog2(hose->mem_resources[i].end 63 - hose->mem_resources[i].start + 1) - 1)); 64 } 65 66 /* Setup outbound IO window */ 67 if (hose->io_resource.flags & IORESOURCE_IO){ 68 pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", 69 hose->io_resource.start, 70 hose->io_resource.end - hose->io_resource.start + 1, 71 hose->io_base_phys); 72 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12) 73 & 0x000fffff); 74 out_be32(&pci->pow[i+1].potear, 0); 75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12) 76 & 0x000fffff); 77 /* Enable, IO R/W */ 78 out_be32(&pci->pow[i+1].powar, 0x80088000 79 | (__ilog2(hose->io_resource.end 80 - hose->io_resource.start + 1) - 1)); 81 } 82 83 /* Setup 2G inbound Memory Window @ 1 */ 84 out_be32(&pci->piw[2].pitar, 0x00000000); 85 out_be32(&pci->piw[2].piwbar,0x00000000); 86 out_be32(&pci->piw[2].piwar, PIWAR_2G); 87 } 88 89 void __init setup_pci_cmd(struct pci_controller *hose) 90 { 91 u16 cmd; 92 int cap_x; 93 94 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 95 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 96 | PCI_COMMAND_IO; 97 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 98 99 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 100 if (cap_x) { 101 int pci_x_cmd = cap_x + PCI_X_CMD; 102 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 103 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 104 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 105 } else { 106 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 107 } 108 } 109 110 static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev) 111 { 112 struct resource *res; 113 int i, res_idx = PCI_BRIDGE_RESOURCES; 114 struct pci_controller *hose; 115 116 /* if we aren't a PCIe don't bother */ 117 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 118 return ; 119 120 /* 121 * Make the bridge be transparent. 122 */ 123 dev->transparent = 1; 124 125 hose = pci_bus_to_host(dev->bus); 126 if (!hose) { 127 printk(KERN_ERR "Can't find hose for bus %d\n", 128 dev->bus->number); 129 return; 130 } 131 132 /* Clear out any of the virtual P2P bridge registers */ 133 pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); 134 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0); 135 pci_write_config_byte(dev, PCI_IO_BASE, 0x10); 136 pci_write_config_byte(dev, PCI_IO_LIMIT, 0); 137 pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10); 138 pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0); 139 pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0); 140 pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 141 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10); 142 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0); 143 144 if (hose->io_resource.flags) { 145 res = &dev->resource[res_idx++]; 146 res->start = hose->io_resource.start; 147 res->end = hose->io_resource.end; 148 res->flags = hose->io_resource.flags; 149 update_bridge_resource(dev, res); 150 } 151 152 for (i = 0; i < 3; i++) { 153 res = &dev->resource[res_idx + i]; 154 res->start = hose->mem_resources[i].start; 155 res->end = hose->mem_resources[i].end; 156 res->flags = hose->mem_resources[i].flags; 157 update_bridge_resource(dev, res); 158 } 159 } 160 161 int __init fsl_pcie_check_link(struct pci_controller *hose) 162 { 163 u32 val; 164 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 165 if (val < PCIE_LTSSM_L0) 166 return 1; 167 return 0; 168 } 169 170 void fsl_pcibios_fixup_bus(struct pci_bus *bus) 171 { 172 struct pci_controller *hose = (struct pci_controller *) bus->sysdata; 173 int i; 174 175 /* deal with bogus pci_bus when we don't have anything connected on PCIe */ 176 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { 177 if (bus->parent) { 178 for (i = 0; i < 4; ++i) 179 bus->resource[i] = bus->parent->resource[i]; 180 } 181 } 182 } 183 184 int __init fsl_add_bridge(struct device_node *dev, int is_primary) 185 { 186 int len; 187 struct pci_controller *hose; 188 struct resource rsrc; 189 const int *bus_range; 190 191 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 192 193 /* Fetch host bridge registers address */ 194 if (of_address_to_resource(dev, 0, &rsrc)) { 195 printk(KERN_WARNING "Can't get pci register base!"); 196 return -ENOMEM; 197 } 198 199 /* Get bus range if any */ 200 bus_range = of_get_property(dev, "bus-range", &len); 201 if (bus_range == NULL || len < 2 * sizeof(int)) 202 printk(KERN_WARNING "Can't get bus-range for %s, assume" 203 " bus 0\n", dev->full_name); 204 205 pci_assign_all_buses = 1; 206 hose = pcibios_alloc_controller(dev); 207 if (!hose) 208 return -ENOMEM; 209 210 hose->first_busno = bus_range ? bus_range[0] : 0x0; 211 hose->last_busno = bus_range ? bus_range[1] : 0xff; 212 213 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 214 PPC_INDIRECT_TYPE_BIG_ENDIAN); 215 setup_pci_cmd(hose); 216 217 /* check PCI express link status */ 218 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 219 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 220 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 221 if (fsl_pcie_check_link(hose)) 222 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 223 } 224 225 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx." 226 "Firmware bus number: %d->%d\n", 227 (unsigned long long)rsrc.start, hose->first_busno, 228 hose->last_busno); 229 230 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 231 hose, hose->cfg_addr, hose->cfg_data); 232 233 /* Interpret the "ranges" property */ 234 /* This also maps the I/O region and sets isa_io/mem_base */ 235 pci_process_bridge_OF_ranges(hose, dev, is_primary); 236 237 /* Setup PEX window registers */ 238 setup_pci_atmu(hose, &rsrc); 239 240 return 0; 241 } 242 243 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent); 244 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent); 245 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent); 246 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent); 247 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent); 248 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent); 249 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent); 250 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent); 251 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent); 252 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent); 253 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent); 254 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_transparent); 255 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_transparent); 256 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent); 257 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent); 258 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_transparent) 259 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_transparent); 260 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); 261 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); 262 DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_transparent); 263