1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved. 4 * 5 * Author: Tony Li <tony.li@freescale.com> 6 * Jason Jin <Jason.jin@freescale.com> 7 */ 8 #ifndef _POWERPC_SYSDEV_FSL_MSI_H 9 #define _POWERPC_SYSDEV_FSL_MSI_H 10 11 #include <linux/of.h> 12 #include <asm/msi_bitmap.h> 13 14 #define NR_MSI_REG_MSIIR 8 /* MSIIR can index 8 MSI registers */ 15 #define NR_MSI_REG_MSIIR1 16 /* MSIIR1 can index 16 MSI registers */ 16 #define NR_MSI_REG_MAX NR_MSI_REG_MSIIR1 17 #define IRQS_PER_MSI_REG 32 18 #define NR_MSI_IRQS_MAX (NR_MSI_REG_MAX * IRQS_PER_MSI_REG) 19 20 #define FSL_PIC_IP_MASK 0x0000000F 21 #define FSL_PIC_IP_MPIC 0x00000001 22 #define FSL_PIC_IP_IPIC 0x00000002 23 #define FSL_PIC_IP_VMPIC 0x00000003 24 25 #define MSI_HW_ERRATA_ENDIAN 0x00000010 26 27 struct fsl_msi_cascade_data; 28 29 struct fsl_msi { 30 struct irq_domain *irqhost; 31 32 unsigned long cascade_irq; 33 34 u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */ 35 u32 ibs_shift; /* Shift of interrupt bit select */ 36 u32 srs_shift; /* Shift of the shared interrupt register select */ 37 void __iomem *msi_regs; 38 u32 feature; 39 struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX]; 40 41 struct msi_bitmap bitmap; 42 43 struct list_head list; /* support multiple MSI banks */ 44 45 phandle phandle; 46 }; 47 48 #endif /* _POWERPC_SYSDEV_FSL_MSI_H */ 49 50