1 /* 2 * arch/powerpc/sysdev/dart_iommu.c 3 * 4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 5 * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, 6 * IBM Corporation 7 * 8 * Based on pSeries_iommu.c: 9 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 10 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 11 * 12 * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. 13 * 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/config.h> 31 #include <linux/init.h> 32 #include <linux/types.h> 33 #include <linux/slab.h> 34 #include <linux/mm.h> 35 #include <linux/spinlock.h> 36 #include <linux/string.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/vmalloc.h> 40 #include <asm/io.h> 41 #include <asm/prom.h> 42 #include <asm/iommu.h> 43 #include <asm/pci-bridge.h> 44 #include <asm/machdep.h> 45 #include <asm/abs_addr.h> 46 #include <asm/cacheflush.h> 47 #include <asm/lmb.h> 48 #include <asm/ppc-pci.h> 49 50 #include "dart.h" 51 52 extern int iommu_is_off; 53 extern int iommu_force_on; 54 55 /* Physical base address and size of the DART table */ 56 unsigned long dart_tablebase; /* exported to htab_initialize */ 57 static unsigned long dart_tablesize; 58 59 /* Virtual base address of the DART table */ 60 static u32 *dart_vbase; 61 62 /* Mapped base address for the dart */ 63 static unsigned int __iomem *dart; 64 65 /* Dummy val that entries are set to when unused */ 66 static unsigned int dart_emptyval; 67 68 static struct iommu_table iommu_table_dart; 69 static int iommu_table_dart_inited; 70 static int dart_dirty; 71 static int dart_is_u4; 72 73 #define DBG(...) 74 75 static inline void dart_tlb_invalidate_all(void) 76 { 77 unsigned long l = 0; 78 unsigned int reg, inv_bit; 79 unsigned long limit; 80 81 DBG("dart: flush\n"); 82 83 /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the 84 * control register and wait for it to clear. 85 * 86 * Gotcha: Sometimes, the DART won't detect that the bit gets 87 * set. If so, clear it and set it again. 88 */ 89 90 limit = 0; 91 92 inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; 93 retry: 94 l = 0; 95 reg = DART_IN(DART_CNTL); 96 reg |= inv_bit; 97 DART_OUT(DART_CNTL, reg); 98 99 while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) 100 l++; 101 if (l == (1L << limit)) { 102 if (limit < 4) { 103 limit++; 104 reg = DART_IN(DART_CNTL); 105 reg &= ~inv_bit; 106 DART_OUT(DART_CNTL, reg); 107 goto retry; 108 } else 109 panic("DART: TLB did not flush after waiting a long " 110 "time. Buggy U3 ?"); 111 } 112 } 113 114 static void dart_flush(struct iommu_table *tbl) 115 { 116 if (dart_dirty) 117 dart_tlb_invalidate_all(); 118 dart_dirty = 0; 119 } 120 121 static void dart_build(struct iommu_table *tbl, long index, 122 long npages, unsigned long uaddr, 123 enum dma_data_direction direction) 124 { 125 unsigned int *dp; 126 unsigned int rpn; 127 128 DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); 129 130 index <<= DART_PAGE_FACTOR; 131 npages <<= DART_PAGE_FACTOR; 132 133 dp = ((unsigned int*)tbl->it_base) + index; 134 135 /* On U3, all memory is contigous, so we can move this 136 * out of the loop. 137 */ 138 while (npages--) { 139 rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; 140 141 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); 142 143 uaddr += DART_PAGE_SIZE; 144 } 145 146 dart_dirty = 1; 147 } 148 149 150 static void dart_free(struct iommu_table *tbl, long index, long npages) 151 { 152 unsigned int *dp; 153 154 /* We don't worry about flushing the TLB cache. The only drawback of 155 * not doing it is that we won't catch buggy device drivers doing 156 * bad DMAs, but then no 32-bit architecture ever does either. 157 */ 158 159 DBG("dart: free at: %lx, %lx\n", index, npages); 160 161 index <<= DART_PAGE_FACTOR; 162 npages <<= DART_PAGE_FACTOR; 163 164 dp = ((unsigned int *)tbl->it_base) + index; 165 166 while (npages--) 167 *(dp++) = dart_emptyval; 168 } 169 170 171 static int dart_init(struct device_node *dart_node) 172 { 173 unsigned int i; 174 unsigned long tmp, base, size; 175 struct resource r; 176 177 if (dart_tablebase == 0 || dart_tablesize == 0) { 178 printk(KERN_INFO "DART: table not allocated, using " 179 "direct DMA\n"); 180 return -ENODEV; 181 } 182 183 if (of_address_to_resource(dart_node, 0, &r)) 184 panic("DART: can't get register base ! "); 185 186 /* Make sure nothing from the DART range remains in the CPU cache 187 * from a previous mapping that existed before the kernel took 188 * over 189 */ 190 flush_dcache_phys_range(dart_tablebase, 191 dart_tablebase + dart_tablesize); 192 193 /* Allocate a spare page to map all invalid DART pages. We need to do 194 * that to work around what looks like a problem with the HT bridge 195 * prefetching into invalid pages and corrupting data 196 */ 197 tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); 198 dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & 199 DARTMAP_RPNMASK); 200 201 /* Map in DART registers */ 202 dart = ioremap(r.start, r.end - r.start + 1); 203 if (dart == NULL) 204 panic("DART: Cannot map registers!"); 205 206 /* Map in DART table */ 207 dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); 208 209 /* Fill initial table */ 210 for (i = 0; i < dart_tablesize/4; i++) 211 dart_vbase[i] = dart_emptyval; 212 213 /* Initialize DART with table base and enable it. */ 214 base = dart_tablebase >> DART_PAGE_SHIFT; 215 size = dart_tablesize >> DART_PAGE_SHIFT; 216 if (dart_is_u4) { 217 size &= DART_SIZE_U4_SIZE_MASK; 218 DART_OUT(DART_BASE_U4, base); 219 DART_OUT(DART_SIZE_U4, size); 220 DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); 221 } else { 222 size &= DART_CNTL_U3_SIZE_MASK; 223 DART_OUT(DART_CNTL, 224 DART_CNTL_U3_ENABLE | 225 (base << DART_CNTL_U3_BASE_SHIFT) | 226 (size << DART_CNTL_U3_SIZE_SHIFT)); 227 } 228 229 /* Invalidate DART to get rid of possible stale TLBs */ 230 dart_tlb_invalidate_all(); 231 232 printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", 233 dart_is_u4 ? "U4" : "U3"); 234 235 return 0; 236 } 237 238 static void iommu_table_dart_setup(void) 239 { 240 iommu_table_dart.it_busno = 0; 241 iommu_table_dart.it_offset = 0; 242 /* it_size is in number of entries */ 243 iommu_table_dart.it_size = (dart_tablesize / sizeof(u32)) >> DART_PAGE_FACTOR; 244 245 /* Initialize the common IOMMU code */ 246 iommu_table_dart.it_base = (unsigned long)dart_vbase; 247 iommu_table_dart.it_index = 0; 248 iommu_table_dart.it_blocksize = 1; 249 iommu_init_table(&iommu_table_dart); 250 251 /* Reserve the last page of the DART to avoid possible prefetch 252 * past the DART mapped area 253 */ 254 set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); 255 } 256 257 static void iommu_dev_setup_dart(struct pci_dev *dev) 258 { 259 struct device_node *dn; 260 261 /* We only have one iommu table on the mac for now, which makes 262 * things simple. Setup all PCI devices to point to this table 263 * 264 * We must use pci_device_to_OF_node() to make sure that 265 * we get the real "final" pointer to the device in the 266 * pci_dev sysdata and not the temporary PHB one 267 */ 268 dn = pci_device_to_OF_node(dev); 269 270 if (dn) 271 PCI_DN(dn)->iommu_table = &iommu_table_dart; 272 } 273 274 static void iommu_bus_setup_dart(struct pci_bus *bus) 275 { 276 struct device_node *dn; 277 278 if (!iommu_table_dart_inited) { 279 iommu_table_dart_inited = 1; 280 iommu_table_dart_setup(); 281 } 282 283 dn = pci_bus_to_OF_node(bus); 284 285 if (dn) 286 PCI_DN(dn)->iommu_table = &iommu_table_dart; 287 } 288 289 static void iommu_dev_setup_null(struct pci_dev *dev) { } 290 static void iommu_bus_setup_null(struct pci_bus *bus) { } 291 292 void iommu_init_early_dart(void) 293 { 294 struct device_node *dn; 295 296 /* Find the DART in the device-tree */ 297 dn = of_find_compatible_node(NULL, "dart", "u3-dart"); 298 if (dn == NULL) { 299 dn = of_find_compatible_node(NULL, "dart", "u4-dart"); 300 if (dn == NULL) 301 goto bail; 302 dart_is_u4 = 1; 303 } 304 305 /* Setup low level TCE operations for the core IOMMU code */ 306 ppc_md.tce_build = dart_build; 307 ppc_md.tce_free = dart_free; 308 ppc_md.tce_flush = dart_flush; 309 310 /* Initialize the DART HW */ 311 if (dart_init(dn) == 0) { 312 ppc_md.iommu_dev_setup = iommu_dev_setup_dart; 313 ppc_md.iommu_bus_setup = iommu_bus_setup_dart; 314 315 /* Setup pci_dma ops */ 316 pci_iommu_init(); 317 318 return; 319 } 320 321 bail: 322 /* If init failed, use direct iommu and null setup functions */ 323 ppc_md.iommu_dev_setup = iommu_dev_setup_null; 324 ppc_md.iommu_bus_setup = iommu_bus_setup_null; 325 326 /* Setup pci_dma ops */ 327 pci_direct_iommu_init(); 328 } 329 330 331 void __init alloc_dart_table(void) 332 { 333 /* Only reserve DART space if machine has more than 1GB of RAM 334 * or if requested with iommu=on on cmdline. 335 * 336 * 1GB of RAM is picked as limit because some default devices 337 * (i.e. Airport Extreme) have 30 bit address range limits. 338 */ 339 340 if (iommu_is_off) 341 return; 342 343 if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull) 344 return; 345 346 /* 512 pages (2MB) is max DART tablesize. */ 347 dart_tablesize = 1UL << 21; 348 /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we 349 * will blow up an entire large page anyway in the kernel mapping 350 */ 351 dart_tablebase = (unsigned long) 352 abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); 353 354 printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase); 355 } 356