1 /* 2 * arch/powerpc/sysdev/dart_iommu.c 3 * 4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 5 * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, 6 * IBM Corporation 7 * 8 * Based on pSeries_iommu.c: 9 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 10 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 11 * 12 * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. 13 * 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/init.h> 31 #include <linux/types.h> 32 #include <linux/slab.h> 33 #include <linux/mm.h> 34 #include <linux/spinlock.h> 35 #include <linux/string.h> 36 #include <linux/pci.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/vmalloc.h> 39 #include <asm/io.h> 40 #include <asm/prom.h> 41 #include <asm/iommu.h> 42 #include <asm/pci-bridge.h> 43 #include <asm/machdep.h> 44 #include <asm/abs_addr.h> 45 #include <asm/cacheflush.h> 46 #include <asm/lmb.h> 47 #include <asm/ppc-pci.h> 48 49 #include "dart.h" 50 51 /* Physical base address and size of the DART table */ 52 unsigned long dart_tablebase; /* exported to htab_initialize */ 53 static unsigned long dart_tablesize; 54 55 /* Virtual base address of the DART table */ 56 static u32 *dart_vbase; 57 58 /* Mapped base address for the dart */ 59 static unsigned int __iomem *dart; 60 61 /* Dummy val that entries are set to when unused */ 62 static unsigned int dart_emptyval; 63 64 static struct iommu_table iommu_table_dart; 65 static int iommu_table_dart_inited; 66 static int dart_dirty; 67 static int dart_is_u4; 68 69 #define DBG(...) 70 71 static inline void dart_tlb_invalidate_all(void) 72 { 73 unsigned long l = 0; 74 unsigned int reg, inv_bit; 75 unsigned long limit; 76 77 DBG("dart: flush\n"); 78 79 /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the 80 * control register and wait for it to clear. 81 * 82 * Gotcha: Sometimes, the DART won't detect that the bit gets 83 * set. If so, clear it and set it again. 84 */ 85 86 limit = 0; 87 88 inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; 89 retry: 90 l = 0; 91 reg = DART_IN(DART_CNTL); 92 reg |= inv_bit; 93 DART_OUT(DART_CNTL, reg); 94 95 while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) 96 l++; 97 if (l == (1L << limit)) { 98 if (limit < 4) { 99 limit++; 100 reg = DART_IN(DART_CNTL); 101 reg &= ~inv_bit; 102 DART_OUT(DART_CNTL, reg); 103 goto retry; 104 } else 105 panic("DART: TLB did not flush after waiting a long " 106 "time. Buggy U3 ?"); 107 } 108 } 109 110 static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) 111 { 112 unsigned int reg; 113 unsigned int l, limit; 114 115 reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | 116 (bus_rpn & DART_CNTL_U4_IONE_MASK); 117 DART_OUT(DART_CNTL, reg); 118 119 limit = 0; 120 wait_more: 121 l = 0; 122 while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { 123 rmb(); 124 l++; 125 } 126 127 if (l == (1L << limit)) { 128 if (limit < 4) { 129 limit++; 130 goto wait_more; 131 } else 132 panic("DART: TLB did not flush after waiting a long " 133 "time. Buggy U4 ?"); 134 } 135 } 136 137 static void dart_flush(struct iommu_table *tbl) 138 { 139 mb(); 140 if (dart_dirty) { 141 dart_tlb_invalidate_all(); 142 dart_dirty = 0; 143 } 144 } 145 146 static void dart_build(struct iommu_table *tbl, long index, 147 long npages, unsigned long uaddr, 148 enum dma_data_direction direction) 149 { 150 unsigned int *dp; 151 unsigned int rpn; 152 long l; 153 154 DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); 155 156 dp = ((unsigned int*)tbl->it_base) + index; 157 158 /* On U3, all memory is contigous, so we can move this 159 * out of the loop. 160 */ 161 l = npages; 162 while (l--) { 163 rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; 164 165 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); 166 167 uaddr += DART_PAGE_SIZE; 168 } 169 170 /* make sure all updates have reached memory */ 171 mb(); 172 in_be32((unsigned __iomem *)dp); 173 mb(); 174 175 if (dart_is_u4) { 176 rpn = index; 177 while (npages--) 178 dart_tlb_invalidate_one(rpn++); 179 } else { 180 dart_dirty = 1; 181 } 182 } 183 184 185 static void dart_free(struct iommu_table *tbl, long index, long npages) 186 { 187 unsigned int *dp; 188 189 /* We don't worry about flushing the TLB cache. The only drawback of 190 * not doing it is that we won't catch buggy device drivers doing 191 * bad DMAs, but then no 32-bit architecture ever does either. 192 */ 193 194 DBG("dart: free at: %lx, %lx\n", index, npages); 195 196 dp = ((unsigned int *)tbl->it_base) + index; 197 198 while (npages--) 199 *(dp++) = dart_emptyval; 200 } 201 202 203 static int dart_init(struct device_node *dart_node) 204 { 205 unsigned int i; 206 unsigned long tmp, base, size; 207 struct resource r; 208 209 if (dart_tablebase == 0 || dart_tablesize == 0) { 210 printk(KERN_INFO "DART: table not allocated, using " 211 "direct DMA\n"); 212 return -ENODEV; 213 } 214 215 if (of_address_to_resource(dart_node, 0, &r)) 216 panic("DART: can't get register base ! "); 217 218 /* Make sure nothing from the DART range remains in the CPU cache 219 * from a previous mapping that existed before the kernel took 220 * over 221 */ 222 flush_dcache_phys_range(dart_tablebase, 223 dart_tablebase + dart_tablesize); 224 225 /* Allocate a spare page to map all invalid DART pages. We need to do 226 * that to work around what looks like a problem with the HT bridge 227 * prefetching into invalid pages and corrupting data 228 */ 229 tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); 230 dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & 231 DARTMAP_RPNMASK); 232 233 /* Map in DART registers */ 234 dart = ioremap(r.start, r.end - r.start + 1); 235 if (dart == NULL) 236 panic("DART: Cannot map registers!"); 237 238 /* Map in DART table */ 239 dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); 240 241 /* Fill initial table */ 242 for (i = 0; i < dart_tablesize/4; i++) 243 dart_vbase[i] = dart_emptyval; 244 245 /* Initialize DART with table base and enable it. */ 246 base = dart_tablebase >> DART_PAGE_SHIFT; 247 size = dart_tablesize >> DART_PAGE_SHIFT; 248 if (dart_is_u4) { 249 size &= DART_SIZE_U4_SIZE_MASK; 250 DART_OUT(DART_BASE_U4, base); 251 DART_OUT(DART_SIZE_U4, size); 252 DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); 253 } else { 254 size &= DART_CNTL_U3_SIZE_MASK; 255 DART_OUT(DART_CNTL, 256 DART_CNTL_U3_ENABLE | 257 (base << DART_CNTL_U3_BASE_SHIFT) | 258 (size << DART_CNTL_U3_SIZE_SHIFT)); 259 } 260 261 /* Invalidate DART to get rid of possible stale TLBs */ 262 dart_tlb_invalidate_all(); 263 264 printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", 265 dart_is_u4 ? "U4" : "U3"); 266 267 return 0; 268 } 269 270 static void iommu_table_dart_setup(void) 271 { 272 iommu_table_dart.it_busno = 0; 273 iommu_table_dart.it_offset = 0; 274 /* it_size is in number of entries */ 275 iommu_table_dart.it_size = dart_tablesize / sizeof(u32); 276 277 /* Initialize the common IOMMU code */ 278 iommu_table_dart.it_base = (unsigned long)dart_vbase; 279 iommu_table_dart.it_index = 0; 280 iommu_table_dart.it_blocksize = 1; 281 iommu_init_table(&iommu_table_dart, -1); 282 283 /* Reserve the last page of the DART to avoid possible prefetch 284 * past the DART mapped area 285 */ 286 set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); 287 } 288 289 static void pci_dma_dev_setup_dart(struct pci_dev *dev) 290 { 291 /* We only have one iommu table on the mac for now, which makes 292 * things simple. Setup all PCI devices to point to this table 293 */ 294 dev->dev.archdata.dma_data = &iommu_table_dart; 295 } 296 297 static void pci_dma_bus_setup_dart(struct pci_bus *bus) 298 { 299 struct device_node *dn; 300 301 if (!iommu_table_dart_inited) { 302 iommu_table_dart_inited = 1; 303 iommu_table_dart_setup(); 304 } 305 306 dn = pci_bus_to_OF_node(bus); 307 308 if (dn) 309 PCI_DN(dn)->iommu_table = &iommu_table_dart; 310 } 311 312 void iommu_init_early_dart(void) 313 { 314 struct device_node *dn; 315 316 /* Find the DART in the device-tree */ 317 dn = of_find_compatible_node(NULL, "dart", "u3-dart"); 318 if (dn == NULL) { 319 dn = of_find_compatible_node(NULL, "dart", "u4-dart"); 320 if (dn == NULL) 321 goto bail; 322 dart_is_u4 = 1; 323 } 324 325 /* Setup low level TCE operations for the core IOMMU code */ 326 ppc_md.tce_build = dart_build; 327 ppc_md.tce_free = dart_free; 328 ppc_md.tce_flush = dart_flush; 329 330 /* Initialize the DART HW */ 331 if (dart_init(dn) == 0) { 332 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart; 333 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart; 334 335 /* Setup pci_dma ops */ 336 pci_dma_ops = &dma_iommu_ops; 337 return; 338 } 339 340 bail: 341 /* If init failed, use direct iommu and null setup functions */ 342 ppc_md.pci_dma_dev_setup = NULL; 343 ppc_md.pci_dma_bus_setup = NULL; 344 345 /* Setup pci_dma ops */ 346 pci_dma_ops = &dma_direct_ops; 347 } 348 349 350 void __init alloc_dart_table(void) 351 { 352 /* Only reserve DART space if machine has more than 1GB of RAM 353 * or if requested with iommu=on on cmdline. 354 * 355 * 1GB of RAM is picked as limit because some default devices 356 * (i.e. Airport Extreme) have 30 bit address range limits. 357 */ 358 359 if (iommu_is_off) 360 return; 361 362 if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull) 363 return; 364 365 /* 512 pages (2MB) is max DART tablesize. */ 366 dart_tablesize = 1UL << 21; 367 /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we 368 * will blow up an entire large page anyway in the kernel mapping 369 */ 370 dart_tablebase = (unsigned long) 371 abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); 372 373 printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase); 374 } 375