1 /* 2 * arch/powerpc/sysdev/dart_iommu.c 3 * 4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 5 * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, 6 * IBM Corporation 7 * 8 * Based on pSeries_iommu.c: 9 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 10 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 11 * 12 * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. 13 * 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/config.h> 31 #include <linux/init.h> 32 #include <linux/types.h> 33 #include <linux/slab.h> 34 #include <linux/mm.h> 35 #include <linux/spinlock.h> 36 #include <linux/string.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/vmalloc.h> 40 #include <asm/io.h> 41 #include <asm/prom.h> 42 #include <asm/iommu.h> 43 #include <asm/pci-bridge.h> 44 #include <asm/machdep.h> 45 #include <asm/abs_addr.h> 46 #include <asm/cacheflush.h> 47 #include <asm/lmb.h> 48 #include <asm/ppc-pci.h> 49 50 #include "dart.h" 51 52 extern int iommu_is_off; 53 extern int iommu_force_on; 54 55 /* Physical base address and size of the DART table */ 56 unsigned long dart_tablebase; /* exported to htab_initialize */ 57 static unsigned long dart_tablesize; 58 59 /* Virtual base address of the DART table */ 60 static u32 *dart_vbase; 61 62 /* Mapped base address for the dart */ 63 static unsigned int __iomem *dart; 64 65 /* Dummy val that entries are set to when unused */ 66 static unsigned int dart_emptyval; 67 68 static struct iommu_table iommu_table_dart; 69 static int iommu_table_dart_inited; 70 static int dart_dirty; 71 static int dart_is_u4; 72 73 #define DBG(...) 74 75 static inline void dart_tlb_invalidate_all(void) 76 { 77 unsigned long l = 0; 78 unsigned int reg, inv_bit; 79 unsigned long limit; 80 81 DBG("dart: flush\n"); 82 83 /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the 84 * control register and wait for it to clear. 85 * 86 * Gotcha: Sometimes, the DART won't detect that the bit gets 87 * set. If so, clear it and set it again. 88 */ 89 90 limit = 0; 91 92 inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; 93 retry: 94 l = 0; 95 reg = DART_IN(DART_CNTL); 96 reg |= inv_bit; 97 DART_OUT(DART_CNTL, reg); 98 99 while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) 100 l++; 101 if (l == (1L << limit)) { 102 if (limit < 4) { 103 limit++; 104 reg = DART_IN(DART_CNTL); 105 reg &= ~inv_bit; 106 DART_OUT(DART_CNTL, reg); 107 goto retry; 108 } else 109 panic("DART: TLB did not flush after waiting a long " 110 "time. Buggy U3 ?"); 111 } 112 } 113 114 static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) 115 { 116 unsigned int reg; 117 unsigned int l, limit; 118 119 reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | 120 (bus_rpn & DART_CNTL_U4_IONE_MASK); 121 DART_OUT(DART_CNTL, reg); 122 123 limit = 0; 124 wait_more: 125 l = 0; 126 while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { 127 rmb(); 128 l++; 129 } 130 131 if (l == (1L << limit)) { 132 if (limit < 4) { 133 limit++; 134 goto wait_more; 135 } else 136 panic("DART: TLB did not flush after waiting a long " 137 "time. Buggy U4 ?"); 138 } 139 } 140 141 static void dart_flush(struct iommu_table *tbl) 142 { 143 if (dart_dirty) { 144 dart_tlb_invalidate_all(); 145 dart_dirty = 0; 146 } 147 } 148 149 static void dart_build(struct iommu_table *tbl, long index, 150 long npages, unsigned long uaddr, 151 enum dma_data_direction direction) 152 { 153 unsigned int *dp; 154 unsigned int rpn; 155 long l; 156 157 DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); 158 159 index <<= DART_PAGE_FACTOR; 160 npages <<= DART_PAGE_FACTOR; 161 162 dp = ((unsigned int*)tbl->it_base) + index; 163 164 /* On U3, all memory is contigous, so we can move this 165 * out of the loop. 166 */ 167 l = npages; 168 while (l--) { 169 rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; 170 171 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); 172 173 uaddr += DART_PAGE_SIZE; 174 } 175 176 if (dart_is_u4) { 177 rpn = index; 178 mb(); /* make sure all updates have reached memory */ 179 while (npages--) 180 dart_tlb_invalidate_one(rpn++); 181 } else { 182 dart_dirty = 1; 183 } 184 } 185 186 187 static void dart_free(struct iommu_table *tbl, long index, long npages) 188 { 189 unsigned int *dp; 190 191 /* We don't worry about flushing the TLB cache. The only drawback of 192 * not doing it is that we won't catch buggy device drivers doing 193 * bad DMAs, but then no 32-bit architecture ever does either. 194 */ 195 196 DBG("dart: free at: %lx, %lx\n", index, npages); 197 198 index <<= DART_PAGE_FACTOR; 199 npages <<= DART_PAGE_FACTOR; 200 201 dp = ((unsigned int *)tbl->it_base) + index; 202 203 while (npages--) 204 *(dp++) = dart_emptyval; 205 } 206 207 208 static int dart_init(struct device_node *dart_node) 209 { 210 unsigned int i; 211 unsigned long tmp, base, size; 212 struct resource r; 213 214 if (dart_tablebase == 0 || dart_tablesize == 0) { 215 printk(KERN_INFO "DART: table not allocated, using " 216 "direct DMA\n"); 217 return -ENODEV; 218 } 219 220 if (of_address_to_resource(dart_node, 0, &r)) 221 panic("DART: can't get register base ! "); 222 223 /* Make sure nothing from the DART range remains in the CPU cache 224 * from a previous mapping that existed before the kernel took 225 * over 226 */ 227 flush_dcache_phys_range(dart_tablebase, 228 dart_tablebase + dart_tablesize); 229 230 /* Allocate a spare page to map all invalid DART pages. We need to do 231 * that to work around what looks like a problem with the HT bridge 232 * prefetching into invalid pages and corrupting data 233 */ 234 tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); 235 dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & 236 DARTMAP_RPNMASK); 237 238 /* Map in DART registers */ 239 dart = ioremap(r.start, r.end - r.start + 1); 240 if (dart == NULL) 241 panic("DART: Cannot map registers!"); 242 243 /* Map in DART table */ 244 dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); 245 246 /* Fill initial table */ 247 for (i = 0; i < dart_tablesize/4; i++) 248 dart_vbase[i] = dart_emptyval; 249 250 /* Initialize DART with table base and enable it. */ 251 base = dart_tablebase >> DART_PAGE_SHIFT; 252 size = dart_tablesize >> DART_PAGE_SHIFT; 253 if (dart_is_u4) { 254 size &= DART_SIZE_U4_SIZE_MASK; 255 DART_OUT(DART_BASE_U4, base); 256 DART_OUT(DART_SIZE_U4, size); 257 DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); 258 } else { 259 size &= DART_CNTL_U3_SIZE_MASK; 260 DART_OUT(DART_CNTL, 261 DART_CNTL_U3_ENABLE | 262 (base << DART_CNTL_U3_BASE_SHIFT) | 263 (size << DART_CNTL_U3_SIZE_SHIFT)); 264 } 265 266 /* Invalidate DART to get rid of possible stale TLBs */ 267 dart_tlb_invalidate_all(); 268 269 printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", 270 dart_is_u4 ? "U4" : "U3"); 271 272 return 0; 273 } 274 275 static void iommu_table_dart_setup(void) 276 { 277 iommu_table_dart.it_busno = 0; 278 iommu_table_dart.it_offset = 0; 279 /* it_size is in number of entries */ 280 iommu_table_dart.it_size = (dart_tablesize / sizeof(u32)) >> DART_PAGE_FACTOR; 281 282 /* Initialize the common IOMMU code */ 283 iommu_table_dart.it_base = (unsigned long)dart_vbase; 284 iommu_table_dart.it_index = 0; 285 iommu_table_dart.it_blocksize = 1; 286 iommu_init_table(&iommu_table_dart, -1); 287 288 /* Reserve the last page of the DART to avoid possible prefetch 289 * past the DART mapped area 290 */ 291 set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); 292 } 293 294 static void iommu_dev_setup_dart(struct pci_dev *dev) 295 { 296 struct device_node *dn; 297 298 /* We only have one iommu table on the mac for now, which makes 299 * things simple. Setup all PCI devices to point to this table 300 * 301 * We must use pci_device_to_OF_node() to make sure that 302 * we get the real "final" pointer to the device in the 303 * pci_dev sysdata and not the temporary PHB one 304 */ 305 dn = pci_device_to_OF_node(dev); 306 307 if (dn) 308 PCI_DN(dn)->iommu_table = &iommu_table_dart; 309 } 310 311 static void iommu_bus_setup_dart(struct pci_bus *bus) 312 { 313 struct device_node *dn; 314 315 if (!iommu_table_dart_inited) { 316 iommu_table_dart_inited = 1; 317 iommu_table_dart_setup(); 318 } 319 320 dn = pci_bus_to_OF_node(bus); 321 322 if (dn) 323 PCI_DN(dn)->iommu_table = &iommu_table_dart; 324 } 325 326 static void iommu_dev_setup_null(struct pci_dev *dev) { } 327 static void iommu_bus_setup_null(struct pci_bus *bus) { } 328 329 void iommu_init_early_dart(void) 330 { 331 struct device_node *dn; 332 333 /* Find the DART in the device-tree */ 334 dn = of_find_compatible_node(NULL, "dart", "u3-dart"); 335 if (dn == NULL) { 336 dn = of_find_compatible_node(NULL, "dart", "u4-dart"); 337 if (dn == NULL) 338 goto bail; 339 dart_is_u4 = 1; 340 } 341 342 /* Setup low level TCE operations for the core IOMMU code */ 343 ppc_md.tce_build = dart_build; 344 ppc_md.tce_free = dart_free; 345 ppc_md.tce_flush = dart_flush; 346 347 /* Initialize the DART HW */ 348 if (dart_init(dn) == 0) { 349 ppc_md.iommu_dev_setup = iommu_dev_setup_dart; 350 ppc_md.iommu_bus_setup = iommu_bus_setup_dart; 351 352 /* Setup pci_dma ops */ 353 pci_iommu_init(); 354 355 return; 356 } 357 358 bail: 359 /* If init failed, use direct iommu and null setup functions */ 360 ppc_md.iommu_dev_setup = iommu_dev_setup_null; 361 ppc_md.iommu_bus_setup = iommu_bus_setup_null; 362 363 /* Setup pci_dma ops */ 364 pci_direct_iommu_init(); 365 } 366 367 368 void __init alloc_dart_table(void) 369 { 370 /* Only reserve DART space if machine has more than 1GB of RAM 371 * or if requested with iommu=on on cmdline. 372 * 373 * 1GB of RAM is picked as limit because some default devices 374 * (i.e. Airport Extreme) have 30 bit address range limits. 375 */ 376 377 if (iommu_is_off) 378 return; 379 380 if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull) 381 return; 382 383 /* 512 pages (2MB) is max DART tablesize. */ 384 dart_tablesize = 1UL << 21; 385 /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we 386 * will blow up an entire large page anyway in the kernel mapping 387 */ 388 dart_tablebase = (unsigned long) 389 abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); 390 391 printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase); 392 } 393