1 /* 2 * Common CPM code 3 * 4 * Author: Scott Wood <scottwood@freescale.com> 5 * 6 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. 7 * 8 * Some parts derived from commproc.c/cpm2_common.c, which is: 9 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) 10 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com> 11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) 12 * 2006 (c) MontaVista Software, Inc. 13 * Vitaly Bordug <vbordug@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of version 2 of the GNU General Public License as 17 * published by the Free Software Foundation. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/of_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/export.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/slab.h> 27 28 #include <asm/udbg.h> 29 #include <asm/io.h> 30 #include <asm/cpm.h> 31 #include <soc/fsl/qe/qe.h> 32 33 #include <mm/mmu_decl.h> 34 35 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 36 #include <linux/of_gpio.h> 37 #endif 38 39 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM 40 static u32 __iomem *cpm_udbg_txdesc = 41 (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR; 42 43 static void udbg_putc_cpm(char c) 44 { 45 u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]); 46 47 if (c == '\n') 48 udbg_putc_cpm('\r'); 49 50 while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000) 51 ; 52 53 out_8(txbuf, c); 54 out_be32(&cpm_udbg_txdesc[0], 0xa0000001); 55 } 56 57 void __init udbg_init_cpm(void) 58 { 59 if (cpm_udbg_txdesc) { 60 #ifdef CONFIG_CPM2 61 setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG); 62 #endif 63 udbg_putc = udbg_putc_cpm; 64 } 65 } 66 #endif 67 68 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) 69 70 struct cpm2_ioports { 71 u32 dir, par, sor, odr, dat; 72 u32 res[3]; 73 }; 74 75 struct cpm2_gpio32_chip { 76 struct of_mm_gpio_chip mm_gc; 77 spinlock_t lock; 78 79 /* shadowed data register to clear/set bits safely */ 80 u32 cpdata; 81 }; 82 83 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 84 { 85 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc); 86 struct cpm2_ioports __iomem *iop = mm_gc->regs; 87 88 cpm2_gc->cpdata = in_be32(&iop->dat); 89 } 90 91 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 92 { 93 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 94 struct cpm2_ioports __iomem *iop = mm_gc->regs; 95 u32 pin_mask; 96 97 pin_mask = 1 << (31 - gpio); 98 99 return !!(in_be32(&iop->dat) & pin_mask); 100 } 101 102 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, 103 int value) 104 { 105 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc); 106 struct cpm2_ioports __iomem *iop = mm_gc->regs; 107 108 if (value) 109 cpm2_gc->cpdata |= pin_mask; 110 else 111 cpm2_gc->cpdata &= ~pin_mask; 112 113 out_be32(&iop->dat, cpm2_gc->cpdata); 114 } 115 116 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 117 { 118 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 119 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); 120 unsigned long flags; 121 u32 pin_mask = 1 << (31 - gpio); 122 123 spin_lock_irqsave(&cpm2_gc->lock, flags); 124 125 __cpm2_gpio32_set(mm_gc, pin_mask, value); 126 127 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 128 } 129 130 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 131 { 132 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 133 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); 134 struct cpm2_ioports __iomem *iop = mm_gc->regs; 135 unsigned long flags; 136 u32 pin_mask = 1 << (31 - gpio); 137 138 spin_lock_irqsave(&cpm2_gc->lock, flags); 139 140 setbits32(&iop->dir, pin_mask); 141 __cpm2_gpio32_set(mm_gc, pin_mask, val); 142 143 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 144 145 return 0; 146 } 147 148 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 149 { 150 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 151 struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); 152 struct cpm2_ioports __iomem *iop = mm_gc->regs; 153 unsigned long flags; 154 u32 pin_mask = 1 << (31 - gpio); 155 156 spin_lock_irqsave(&cpm2_gc->lock, flags); 157 158 clrbits32(&iop->dir, pin_mask); 159 160 spin_unlock_irqrestore(&cpm2_gc->lock, flags); 161 162 return 0; 163 } 164 165 int cpm2_gpiochip_add32(struct device_node *np) 166 { 167 struct cpm2_gpio32_chip *cpm2_gc; 168 struct of_mm_gpio_chip *mm_gc; 169 struct gpio_chip *gc; 170 171 cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL); 172 if (!cpm2_gc) 173 return -ENOMEM; 174 175 spin_lock_init(&cpm2_gc->lock); 176 177 mm_gc = &cpm2_gc->mm_gc; 178 gc = &mm_gc->gc; 179 180 mm_gc->save_regs = cpm2_gpio32_save_regs; 181 gc->ngpio = 32; 182 gc->direction_input = cpm2_gpio32_dir_in; 183 gc->direction_output = cpm2_gpio32_dir_out; 184 gc->get = cpm2_gpio32_get; 185 gc->set = cpm2_gpio32_set; 186 187 return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc); 188 } 189 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */ 190