1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 64-bit pSeries and RS/6000 setup code. 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Adapted from 'alpha' version by Gary Thomas 7 * Modified by Cort Dougan (cort@cs.nmt.edu) 8 * Modified by PPC64 Team, IBM Corp 9 */ 10 11 /* 12 * bootup setup stuff.. 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/errno.h> 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/user.h> 23 #include <linux/tty.h> 24 #include <linux/major.h> 25 #include <linux/interrupt.h> 26 #include <linux/reboot.h> 27 #include <linux/init.h> 28 #include <linux/ioport.h> 29 #include <linux/console.h> 30 #include <linux/pci.h> 31 #include <linux/utsname.h> 32 #include <linux/adb.h> 33 #include <linux/export.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/seq_file.h> 37 #include <linux/root_dev.h> 38 #include <linux/of.h> 39 #include <linux/of_pci.h> 40 #include <linux/memblock.h> 41 42 #include <asm/mmu.h> 43 #include <asm/processor.h> 44 #include <asm/io.h> 45 #include <asm/pgtable.h> 46 #include <asm/prom.h> 47 #include <asm/rtas.h> 48 #include <asm/pci-bridge.h> 49 #include <asm/iommu.h> 50 #include <asm/dma.h> 51 #include <asm/machdep.h> 52 #include <asm/irq.h> 53 #include <asm/time.h> 54 #include <asm/nvram.h> 55 #include <asm/pmc.h> 56 #include <asm/xics.h> 57 #include <asm/xive.h> 58 #include <asm/ppc-pci.h> 59 #include <asm/i8259.h> 60 #include <asm/udbg.h> 61 #include <asm/smp.h> 62 #include <asm/firmware.h> 63 #include <asm/eeh.h> 64 #include <asm/reg.h> 65 #include <asm/plpar_wrappers.h> 66 #include <asm/kexec.h> 67 #include <asm/isa-bridge.h> 68 #include <asm/security_features.h> 69 #include <asm/asm-const.h> 70 71 #include "pseries.h" 72 #include "../../../../drivers/pci/pci.h" 73 74 int CMO_PrPSP = -1; 75 int CMO_SecPSP = -1; 76 unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K); 77 EXPORT_SYMBOL(CMO_PageSize); 78 79 int fwnmi_active; /* TRUE if an FWNMI handler is present */ 80 81 static void pSeries_show_cpuinfo(struct seq_file *m) 82 { 83 struct device_node *root; 84 const char *model = ""; 85 86 root = of_find_node_by_path("/"); 87 if (root) 88 model = of_get_property(root, "model", NULL); 89 seq_printf(m, "machine\t\t: CHRP %s\n", model); 90 of_node_put(root); 91 if (radix_enabled()) 92 seq_printf(m, "MMU\t\t: Radix\n"); 93 else 94 seq_printf(m, "MMU\t\t: Hash\n"); 95 } 96 97 /* Initialize firmware assisted non-maskable interrupts if 98 * the firmware supports this feature. 99 */ 100 static void __init fwnmi_init(void) 101 { 102 unsigned long system_reset_addr, machine_check_addr; 103 u8 *mce_data_buf; 104 unsigned int i; 105 int nr_cpus = num_possible_cpus(); 106 #ifdef CONFIG_PPC_BOOK3S_64 107 struct slb_entry *slb_ptr; 108 size_t size; 109 #endif 110 111 int ibm_nmi_register = rtas_token("ibm,nmi-register"); 112 if (ibm_nmi_register == RTAS_UNKNOWN_SERVICE) 113 return; 114 115 /* If the kernel's not linked at zero we point the firmware at low 116 * addresses anyway, and use a trampoline to get to the real code. */ 117 system_reset_addr = __pa(system_reset_fwnmi) - PHYSICAL_START; 118 machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START; 119 120 if (0 == rtas_call(ibm_nmi_register, 2, 1, NULL, system_reset_addr, 121 machine_check_addr)) 122 fwnmi_active = 1; 123 124 /* 125 * Allocate a chunk for per cpu buffer to hold rtas errorlog. 126 * It will be used in real mode mce handler, hence it needs to be 127 * below RMA. 128 */ 129 mce_data_buf = memblock_alloc_try_nid_raw(RTAS_ERROR_LOG_MAX * nr_cpus, 130 RTAS_ERROR_LOG_MAX, MEMBLOCK_LOW_LIMIT, 131 ppc64_rma_size, NUMA_NO_NODE); 132 if (!mce_data_buf) 133 panic("Failed to allocate %d bytes below %pa for MCE buffer\n", 134 RTAS_ERROR_LOG_MAX * nr_cpus, &ppc64_rma_size); 135 136 for_each_possible_cpu(i) { 137 paca_ptrs[i]->mce_data_buf = mce_data_buf + 138 (RTAS_ERROR_LOG_MAX * i); 139 } 140 141 #ifdef CONFIG_PPC_BOOK3S_64 142 /* Allocate per cpu slb area to save old slb contents during MCE */ 143 size = sizeof(struct slb_entry) * mmu_slb_size * nr_cpus; 144 slb_ptr = memblock_alloc_try_nid_raw(size, sizeof(struct slb_entry), 145 MEMBLOCK_LOW_LIMIT, ppc64_rma_size, 146 NUMA_NO_NODE); 147 if (!slb_ptr) 148 panic("Failed to allocate %zu bytes below %pa for slb area\n", 149 size, &ppc64_rma_size); 150 151 for_each_possible_cpu(i) 152 paca_ptrs[i]->mce_faulty_slbs = slb_ptr + (mmu_slb_size * i); 153 #endif 154 } 155 156 static void pseries_8259_cascade(struct irq_desc *desc) 157 { 158 struct irq_chip *chip = irq_desc_get_chip(desc); 159 unsigned int cascade_irq = i8259_irq(); 160 161 if (cascade_irq) 162 generic_handle_irq(cascade_irq); 163 164 chip->irq_eoi(&desc->irq_data); 165 } 166 167 static void __init pseries_setup_i8259_cascade(void) 168 { 169 struct device_node *np, *old, *found = NULL; 170 unsigned int cascade; 171 const u32 *addrp; 172 unsigned long intack = 0; 173 int naddr; 174 175 for_each_node_by_type(np, "interrupt-controller") { 176 if (of_device_is_compatible(np, "chrp,iic")) { 177 found = np; 178 break; 179 } 180 } 181 182 if (found == NULL) { 183 printk(KERN_DEBUG "pic: no ISA interrupt controller\n"); 184 return; 185 } 186 187 cascade = irq_of_parse_and_map(found, 0); 188 if (!cascade) { 189 printk(KERN_ERR "pic: failed to map cascade interrupt"); 190 return; 191 } 192 pr_debug("pic: cascade mapped to irq %d\n", cascade); 193 194 for (old = of_node_get(found); old != NULL ; old = np) { 195 np = of_get_parent(old); 196 of_node_put(old); 197 if (np == NULL) 198 break; 199 if (!of_node_name_eq(np, "pci")) 200 continue; 201 addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL); 202 if (addrp == NULL) 203 continue; 204 naddr = of_n_addr_cells(np); 205 intack = addrp[naddr-1]; 206 if (naddr > 1) 207 intack |= ((unsigned long)addrp[naddr-2]) << 32; 208 } 209 if (intack) 210 printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack); 211 i8259_init(found, intack); 212 of_node_put(found); 213 irq_set_chained_handler(cascade, pseries_8259_cascade); 214 } 215 216 static void __init pseries_init_irq(void) 217 { 218 /* Try using a XIVE if available, otherwise use a XICS */ 219 if (!xive_spapr_init()) { 220 xics_init(); 221 pseries_setup_i8259_cascade(); 222 } 223 } 224 225 static void pseries_lpar_enable_pmcs(void) 226 { 227 unsigned long set, reset; 228 229 set = 1UL << 63; 230 reset = 0; 231 plpar_hcall_norets(H_PERFMON, set, reset); 232 } 233 234 static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data) 235 { 236 struct of_reconfig_data *rd = data; 237 struct device_node *parent, *np = rd->dn; 238 struct pci_dn *pdn; 239 int err = NOTIFY_OK; 240 241 switch (action) { 242 case OF_RECONFIG_ATTACH_NODE: 243 parent = of_get_parent(np); 244 pdn = parent ? PCI_DN(parent) : NULL; 245 if (pdn) 246 pci_add_device_node_info(pdn->phb, np); 247 248 of_node_put(parent); 249 break; 250 case OF_RECONFIG_DETACH_NODE: 251 pdn = PCI_DN(np); 252 if (pdn) 253 list_del(&pdn->list); 254 break; 255 default: 256 err = NOTIFY_DONE; 257 break; 258 } 259 return err; 260 } 261 262 static struct notifier_block pci_dn_reconfig_nb = { 263 .notifier_call = pci_dn_reconfig_notifier, 264 }; 265 266 struct kmem_cache *dtl_cache; 267 268 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 269 /* 270 * Allocate space for the dispatch trace log for all possible cpus 271 * and register the buffers with the hypervisor. This is used for 272 * computing time stolen by the hypervisor. 273 */ 274 static int alloc_dispatch_logs(void) 275 { 276 int cpu, ret; 277 struct paca_struct *pp; 278 struct dtl_entry *dtl; 279 280 if (!firmware_has_feature(FW_FEATURE_SPLPAR)) 281 return 0; 282 283 if (!dtl_cache) 284 return 0; 285 286 for_each_possible_cpu(cpu) { 287 pp = paca_ptrs[cpu]; 288 dtl = kmem_cache_alloc(dtl_cache, GFP_KERNEL); 289 if (!dtl) { 290 pr_warn("Failed to allocate dispatch trace log for cpu %d\n", 291 cpu); 292 pr_warn("Stolen time statistics will be unreliable\n"); 293 break; 294 } 295 296 pp->dtl_ridx = 0; 297 pp->dispatch_log = dtl; 298 pp->dispatch_log_end = dtl + N_DISPATCH_LOG; 299 pp->dtl_curr = dtl; 300 } 301 302 /* Register the DTL for the current (boot) cpu */ 303 dtl = get_paca()->dispatch_log; 304 get_paca()->dtl_ridx = 0; 305 get_paca()->dtl_curr = dtl; 306 get_paca()->lppaca_ptr->dtl_idx = 0; 307 308 /* hypervisor reads buffer length from this field */ 309 dtl->enqueue_to_dispatch_time = cpu_to_be32(DISPATCH_LOG_BYTES); 310 ret = register_dtl(hard_smp_processor_id(), __pa(dtl)); 311 if (ret) 312 pr_err("WARNING: DTL registration of cpu %d (hw %d) failed " 313 "with %d\n", smp_processor_id(), 314 hard_smp_processor_id(), ret); 315 get_paca()->lppaca_ptr->dtl_enable_mask = 2; 316 317 return 0; 318 } 319 #else /* !CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 320 static inline int alloc_dispatch_logs(void) 321 { 322 return 0; 323 } 324 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 325 326 static int alloc_dispatch_log_kmem_cache(void) 327 { 328 dtl_cache = kmem_cache_create("dtl", DISPATCH_LOG_BYTES, 329 DISPATCH_LOG_BYTES, 0, NULL); 330 if (!dtl_cache) { 331 pr_warn("Failed to create dispatch trace log buffer cache\n"); 332 pr_warn("Stolen time statistics will be unreliable\n"); 333 return 0; 334 } 335 336 return alloc_dispatch_logs(); 337 } 338 machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache); 339 340 static void pseries_lpar_idle(void) 341 { 342 /* 343 * Default handler to go into low thread priority and possibly 344 * low power mode by ceding processor to hypervisor 345 */ 346 347 /* Indicate to hypervisor that we are idle. */ 348 get_lppaca()->idle = 1; 349 350 /* 351 * Yield the processor to the hypervisor. We return if 352 * an external interrupt occurs (which are driven prior 353 * to returning here) or if a prod occurs from another 354 * processor. When returning here, external interrupts 355 * are enabled. 356 */ 357 cede_processor(); 358 359 get_lppaca()->idle = 0; 360 } 361 362 /* 363 * Enable relocation on during exceptions. This has partition wide scope and 364 * may take a while to complete, if it takes longer than one second we will 365 * just give up rather than wasting any more time on this - if that turns out 366 * to ever be a problem in practice we can move this into a kernel thread to 367 * finish off the process later in boot. 368 */ 369 void pseries_enable_reloc_on_exc(void) 370 { 371 long rc; 372 unsigned int delay, total_delay = 0; 373 374 while (1) { 375 rc = enable_reloc_on_exceptions(); 376 if (!H_IS_LONG_BUSY(rc)) { 377 if (rc == H_P2) { 378 pr_info("Relocation on exceptions not" 379 " supported\n"); 380 } else if (rc != H_SUCCESS) { 381 pr_warn("Unable to enable relocation" 382 " on exceptions: %ld\n", rc); 383 } 384 break; 385 } 386 387 delay = get_longbusy_msecs(rc); 388 total_delay += delay; 389 if (total_delay > 1000) { 390 pr_warn("Warning: Giving up waiting to enable " 391 "relocation on exceptions (%u msec)!\n", 392 total_delay); 393 return; 394 } 395 396 mdelay(delay); 397 } 398 } 399 EXPORT_SYMBOL(pseries_enable_reloc_on_exc); 400 401 void pseries_disable_reloc_on_exc(void) 402 { 403 long rc; 404 405 while (1) { 406 rc = disable_reloc_on_exceptions(); 407 if (!H_IS_LONG_BUSY(rc)) 408 break; 409 mdelay(get_longbusy_msecs(rc)); 410 } 411 if (rc != H_SUCCESS) 412 pr_warn("Warning: Failed to disable relocation on exceptions: %ld\n", 413 rc); 414 } 415 EXPORT_SYMBOL(pseries_disable_reloc_on_exc); 416 417 #ifdef CONFIG_KEXEC_CORE 418 static void pSeries_machine_kexec(struct kimage *image) 419 { 420 if (firmware_has_feature(FW_FEATURE_SET_MODE)) 421 pseries_disable_reloc_on_exc(); 422 423 default_machine_kexec(image); 424 } 425 #endif 426 427 #ifdef __LITTLE_ENDIAN__ 428 void pseries_big_endian_exceptions(void) 429 { 430 long rc; 431 432 while (1) { 433 rc = enable_big_endian_exceptions(); 434 if (!H_IS_LONG_BUSY(rc)) 435 break; 436 mdelay(get_longbusy_msecs(rc)); 437 } 438 439 /* 440 * At this point it is unlikely panic() will get anything 441 * out to the user, since this is called very late in kexec 442 * but at least this will stop us from continuing on further 443 * and creating an even more difficult to debug situation. 444 * 445 * There is a known problem when kdump'ing, if cpus are offline 446 * the above call will fail. Rather than panicking again, keep 447 * going and hope the kdump kernel is also little endian, which 448 * it usually is. 449 */ 450 if (rc && !kdump_in_progress()) 451 panic("Could not enable big endian exceptions"); 452 } 453 454 void pseries_little_endian_exceptions(void) 455 { 456 long rc; 457 458 while (1) { 459 rc = enable_little_endian_exceptions(); 460 if (!H_IS_LONG_BUSY(rc)) 461 break; 462 mdelay(get_longbusy_msecs(rc)); 463 } 464 if (rc) { 465 ppc_md.progress("H_SET_MODE LE exception fail", 0); 466 panic("Could not enable little endian exceptions"); 467 } 468 } 469 #endif 470 471 static void __init find_and_init_phbs(void) 472 { 473 struct device_node *node; 474 struct pci_controller *phb; 475 struct device_node *root = of_find_node_by_path("/"); 476 477 for_each_child_of_node(root, node) { 478 if (!of_node_is_type(node, "pci") && 479 !of_node_is_type(node, "pciex")) 480 continue; 481 482 phb = pcibios_alloc_controller(node); 483 if (!phb) 484 continue; 485 rtas_setup_phb(phb); 486 pci_process_bridge_OF_ranges(phb, node, 0); 487 isa_bridge_find_early(phb); 488 phb->controller_ops = pseries_pci_controller_ops; 489 } 490 491 of_node_put(root); 492 493 /* 494 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties 495 * in chosen. 496 */ 497 of_pci_check_probe_only(); 498 } 499 500 static void init_cpu_char_feature_flags(struct h_cpu_char_result *result) 501 { 502 /* 503 * The features below are disabled by default, so we instead look to see 504 * if firmware has *enabled* them, and set them if so. 505 */ 506 if (result->character & H_CPU_CHAR_SPEC_BAR_ORI31) 507 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31); 508 509 if (result->character & H_CPU_CHAR_BCCTRL_SERIALISED) 510 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED); 511 512 if (result->character & H_CPU_CHAR_L1D_FLUSH_ORI30) 513 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30); 514 515 if (result->character & H_CPU_CHAR_L1D_FLUSH_TRIG2) 516 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2); 517 518 if (result->character & H_CPU_CHAR_L1D_THREAD_PRIV) 519 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV); 520 521 if (result->character & H_CPU_CHAR_COUNT_CACHE_DISABLED) 522 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED); 523 524 if (result->character & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) 525 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST); 526 527 if (result->behaviour & H_CPU_BEHAV_FLUSH_COUNT_CACHE) 528 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE); 529 530 /* 531 * The features below are enabled by default, so we instead look to see 532 * if firmware has *disabled* them, and clear them if so. 533 */ 534 if (!(result->behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)) 535 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); 536 537 if (!(result->behaviour & H_CPU_BEHAV_L1D_FLUSH_PR)) 538 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); 539 540 if (!(result->behaviour & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR)) 541 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); 542 } 543 544 void pseries_setup_rfi_flush(void) 545 { 546 struct h_cpu_char_result result; 547 enum l1d_flush_type types; 548 bool enable; 549 long rc; 550 551 /* 552 * Set features to the defaults assumed by init_cpu_char_feature_flags() 553 * so it can set/clear again any features that might have changed after 554 * migration, and in case the hypercall fails and it is not even called. 555 */ 556 powerpc_security_features = SEC_FTR_DEFAULT; 557 558 rc = plpar_get_cpu_characteristics(&result); 559 if (rc == H_SUCCESS) 560 init_cpu_char_feature_flags(&result); 561 562 /* 563 * We're the guest so this doesn't apply to us, clear it to simplify 564 * handling of it elsewhere. 565 */ 566 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV); 567 568 types = L1D_FLUSH_FALLBACK; 569 570 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2)) 571 types |= L1D_FLUSH_MTTRIG; 572 573 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30)) 574 types |= L1D_FLUSH_ORI; 575 576 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \ 577 security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR); 578 579 setup_rfi_flush(types, enable); 580 setup_count_cache_flush(); 581 } 582 583 #ifdef CONFIG_PCI_IOV 584 enum rtas_iov_fw_value_map { 585 NUM_RES_PROPERTY = 0, /* Number of Resources */ 586 LOW_INT = 1, /* Lowest 32 bits of Address */ 587 START_OF_ENTRIES = 2, /* Always start of entry */ 588 APERTURE_PROPERTY = 2, /* Start of entry+ to Aperture Size */ 589 WDW_SIZE_PROPERTY = 4, /* Start of entry+ to Window Size */ 590 NEXT_ENTRY = 7 /* Go to next entry on array */ 591 }; 592 593 enum get_iov_fw_value_index { 594 BAR_ADDRS = 1, /* Get Bar Address */ 595 APERTURE_SIZE = 2, /* Get Aperture Size */ 596 WDW_SIZE = 3 /* Get Window Size */ 597 }; 598 599 resource_size_t pseries_get_iov_fw_value(struct pci_dev *dev, int resno, 600 enum get_iov_fw_value_index value) 601 { 602 const int *indexes; 603 struct device_node *dn = pci_device_to_OF_node(dev); 604 int i, num_res, ret = 0; 605 606 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 607 if (!indexes) 608 return 0; 609 610 /* 611 * First element in the array is the number of Bars 612 * returned. Search through the list to find the matching 613 * bar 614 */ 615 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 616 if (resno >= num_res) 617 return 0; /* or an errror */ 618 619 i = START_OF_ENTRIES + NEXT_ENTRY * resno; 620 switch (value) { 621 case BAR_ADDRS: 622 ret = of_read_number(&indexes[i], 2); 623 break; 624 case APERTURE_SIZE: 625 ret = of_read_number(&indexes[i + APERTURE_PROPERTY], 2); 626 break; 627 case WDW_SIZE: 628 ret = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2); 629 break; 630 } 631 632 return ret; 633 } 634 635 void of_pci_set_vf_bar_size(struct pci_dev *dev, const int *indexes) 636 { 637 struct resource *res; 638 resource_size_t base, size; 639 int i, r, num_res; 640 641 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 642 num_res = min_t(int, num_res, PCI_SRIOV_NUM_BARS); 643 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS; 644 i += NEXT_ENTRY, r++) { 645 res = &dev->resource[r + PCI_IOV_RESOURCES]; 646 base = of_read_number(&indexes[i], 2); 647 size = of_read_number(&indexes[i + APERTURE_PROPERTY], 2); 648 res->flags = pci_parse_of_flags(of_read_number 649 (&indexes[i + LOW_INT], 1), 0); 650 res->flags |= (IORESOURCE_MEM_64 | IORESOURCE_PCI_FIXED); 651 res->name = pci_name(dev); 652 res->start = base; 653 res->end = base + size - 1; 654 } 655 } 656 657 void of_pci_parse_iov_addrs(struct pci_dev *dev, const int *indexes) 658 { 659 struct resource *res, *root, *conflict; 660 resource_size_t base, size; 661 int i, r, num_res; 662 663 /* 664 * First element in the array is the number of Bars 665 * returned. Search through the list to find the matching 666 * bars assign them from firmware into resources structure. 667 */ 668 num_res = of_read_number(&indexes[NUM_RES_PROPERTY], 1); 669 for (i = START_OF_ENTRIES, r = 0; r < num_res && r < PCI_SRIOV_NUM_BARS; 670 i += NEXT_ENTRY, r++) { 671 res = &dev->resource[r + PCI_IOV_RESOURCES]; 672 base = of_read_number(&indexes[i], 2); 673 size = of_read_number(&indexes[i + WDW_SIZE_PROPERTY], 2); 674 res->name = pci_name(dev); 675 res->start = base; 676 res->end = base + size - 1; 677 root = &iomem_resource; 678 dev_dbg(&dev->dev, 679 "pSeries IOV BAR %d: trying firmware assignment %pR\n", 680 r + PCI_IOV_RESOURCES, res); 681 conflict = request_resource_conflict(root, res); 682 if (conflict) { 683 dev_info(&dev->dev, 684 "BAR %d: %pR conflicts with %s %pR\n", 685 r + PCI_IOV_RESOURCES, res, 686 conflict->name, conflict); 687 res->flags |= IORESOURCE_UNSET; 688 } 689 } 690 } 691 692 static void pseries_disable_sriov_resources(struct pci_dev *pdev) 693 { 694 int i; 695 696 pci_warn(pdev, "No hypervisor support for SR-IOV on this device, IOV BARs disabled.\n"); 697 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 698 pdev->resource[i + PCI_IOV_RESOURCES].flags = 0; 699 } 700 701 static void pseries_pci_fixup_resources(struct pci_dev *pdev) 702 { 703 const int *indexes; 704 struct device_node *dn = pci_device_to_OF_node(pdev); 705 706 /*Firmware must support open sriov otherwise dont configure*/ 707 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 708 if (indexes) 709 of_pci_set_vf_bar_size(pdev, indexes); 710 else 711 pseries_disable_sriov_resources(pdev); 712 } 713 714 static void pseries_pci_fixup_iov_resources(struct pci_dev *pdev) 715 { 716 const int *indexes; 717 struct device_node *dn = pci_device_to_OF_node(pdev); 718 719 if (!pdev->is_physfn || pci_dev_is_added(pdev)) 720 return; 721 /*Firmware must support open sriov otherwise dont configure*/ 722 indexes = of_get_property(dn, "ibm,open-sriov-vf-bar-info", NULL); 723 if (indexes) 724 of_pci_parse_iov_addrs(pdev, indexes); 725 else 726 pseries_disable_sriov_resources(pdev); 727 } 728 729 static resource_size_t pseries_pci_iov_resource_alignment(struct pci_dev *pdev, 730 int resno) 731 { 732 const __be32 *reg; 733 struct device_node *dn = pci_device_to_OF_node(pdev); 734 735 /*Firmware must support open sriov otherwise report regular alignment*/ 736 reg = of_get_property(dn, "ibm,is-open-sriov-pf", NULL); 737 if (!reg) 738 return pci_iov_resource_size(pdev, resno); 739 740 if (!pdev->is_physfn) 741 return 0; 742 return pseries_get_iov_fw_value(pdev, 743 resno - PCI_IOV_RESOURCES, 744 APERTURE_SIZE); 745 } 746 #endif 747 748 static void __init pSeries_setup_arch(void) 749 { 750 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); 751 752 /* Discover PIC type and setup ppc_md accordingly */ 753 smp_init_pseries(); 754 755 756 /* openpic global configuration register (64-bit format). */ 757 /* openpic Interrupt Source Unit pointer (64-bit format). */ 758 /* python0 facility area (mmio) (64-bit format) REAL address. */ 759 760 /* init to some ~sane value until calibrate_delay() runs */ 761 loops_per_jiffy = 50000000; 762 763 fwnmi_init(); 764 765 pseries_setup_rfi_flush(); 766 setup_stf_barrier(); 767 768 /* By default, only probe PCI (can be overridden by rtas_pci) */ 769 pci_add_flags(PCI_PROBE_ONLY); 770 771 /* Find and initialize PCI host bridges */ 772 init_pci_config_tokens(); 773 find_and_init_phbs(); 774 of_reconfig_notifier_register(&pci_dn_reconfig_nb); 775 776 pSeries_nvram_init(); 777 778 if (firmware_has_feature(FW_FEATURE_LPAR)) { 779 vpa_init(boot_cpuid); 780 ppc_md.power_save = pseries_lpar_idle; 781 ppc_md.enable_pmcs = pseries_lpar_enable_pmcs; 782 #ifdef CONFIG_PCI_IOV 783 ppc_md.pcibios_fixup_resources = 784 pseries_pci_fixup_resources; 785 ppc_md.pcibios_fixup_sriov = 786 pseries_pci_fixup_iov_resources; 787 ppc_md.pcibios_iov_resource_alignment = 788 pseries_pci_iov_resource_alignment; 789 #endif 790 } else { 791 /* No special idle routine */ 792 ppc_md.enable_pmcs = power4_enable_pmcs; 793 } 794 795 ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare; 796 } 797 798 static void pseries_panic(char *str) 799 { 800 panic_flush_kmsg_end(); 801 rtas_os_term(str); 802 } 803 804 static int __init pSeries_init_panel(void) 805 { 806 /* Manually leave the kernel version on the panel. */ 807 #ifdef __BIG_ENDIAN__ 808 ppc_md.progress("Linux ppc64\n", 0); 809 #else 810 ppc_md.progress("Linux ppc64le\n", 0); 811 #endif 812 ppc_md.progress(init_utsname()->version, 0); 813 814 return 0; 815 } 816 machine_arch_initcall(pseries, pSeries_init_panel); 817 818 static int pseries_set_dabr(unsigned long dabr, unsigned long dabrx) 819 { 820 return plpar_hcall_norets(H_SET_DABR, dabr); 821 } 822 823 static int pseries_set_xdabr(unsigned long dabr, unsigned long dabrx) 824 { 825 /* Have to set at least one bit in the DABRX according to PAPR */ 826 if (dabrx == 0 && dabr == 0) 827 dabrx = DABRX_USER; 828 /* PAPR says we can only set kernel and user bits */ 829 dabrx &= DABRX_KERNEL | DABRX_USER; 830 831 return plpar_hcall_norets(H_SET_XDABR, dabr, dabrx); 832 } 833 834 static int pseries_set_dawr(unsigned long dawr, unsigned long dawrx) 835 { 836 /* PAPR says we can't set HYP */ 837 dawrx &= ~DAWRX_HYP; 838 839 return plpar_set_watchpoint0(dawr, dawrx); 840 } 841 842 #define CMO_CHARACTERISTICS_TOKEN 44 843 #define CMO_MAXLENGTH 1026 844 845 void pSeries_coalesce_init(void) 846 { 847 struct hvcall_mpp_x_data mpp_x_data; 848 849 if (firmware_has_feature(FW_FEATURE_CMO) && !h_get_mpp_x(&mpp_x_data)) 850 powerpc_firmware_features |= FW_FEATURE_XCMO; 851 else 852 powerpc_firmware_features &= ~FW_FEATURE_XCMO; 853 } 854 855 /** 856 * fw_cmo_feature_init - FW_FEATURE_CMO is not stored in ibm,hypertas-functions, 857 * handle that here. (Stolen from parse_system_parameter_string) 858 */ 859 static void pSeries_cmo_feature_init(void) 860 { 861 char *ptr, *key, *value, *end; 862 int call_status; 863 int page_order = IOMMU_PAGE_SHIFT_4K; 864 865 pr_debug(" -> fw_cmo_feature_init()\n"); 866 spin_lock(&rtas_data_buf_lock); 867 memset(rtas_data_buf, 0, RTAS_DATA_BUF_SIZE); 868 call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1, 869 NULL, 870 CMO_CHARACTERISTICS_TOKEN, 871 __pa(rtas_data_buf), 872 RTAS_DATA_BUF_SIZE); 873 874 if (call_status != 0) { 875 spin_unlock(&rtas_data_buf_lock); 876 pr_debug("CMO not available\n"); 877 pr_debug(" <- fw_cmo_feature_init()\n"); 878 return; 879 } 880 881 end = rtas_data_buf + CMO_MAXLENGTH - 2; 882 ptr = rtas_data_buf + 2; /* step over strlen value */ 883 key = value = ptr; 884 885 while (*ptr && (ptr <= end)) { 886 /* Separate the key and value by replacing '=' with '\0' and 887 * point the value at the string after the '=' 888 */ 889 if (ptr[0] == '=') { 890 ptr[0] = '\0'; 891 value = ptr + 1; 892 } else if (ptr[0] == '\0' || ptr[0] == ',') { 893 /* Terminate the string containing the key/value pair */ 894 ptr[0] = '\0'; 895 896 if (key == value) { 897 pr_debug("Malformed key/value pair\n"); 898 /* Never found a '=', end processing */ 899 break; 900 } 901 902 if (0 == strcmp(key, "CMOPageSize")) 903 page_order = simple_strtol(value, NULL, 10); 904 else if (0 == strcmp(key, "PrPSP")) 905 CMO_PrPSP = simple_strtol(value, NULL, 10); 906 else if (0 == strcmp(key, "SecPSP")) 907 CMO_SecPSP = simple_strtol(value, NULL, 10); 908 value = key = ptr + 1; 909 } 910 ptr++; 911 } 912 913 /* Page size is returned as the power of 2 of the page size, 914 * convert to the page size in bytes before returning 915 */ 916 CMO_PageSize = 1 << page_order; 917 pr_debug("CMO_PageSize = %lu\n", CMO_PageSize); 918 919 if (CMO_PrPSP != -1 || CMO_SecPSP != -1) { 920 pr_info("CMO enabled\n"); 921 pr_debug("CMO enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP, 922 CMO_SecPSP); 923 powerpc_firmware_features |= FW_FEATURE_CMO; 924 pSeries_coalesce_init(); 925 } else 926 pr_debug("CMO not enabled, PrPSP=%d, SecPSP=%d\n", CMO_PrPSP, 927 CMO_SecPSP); 928 spin_unlock(&rtas_data_buf_lock); 929 pr_debug(" <- fw_cmo_feature_init()\n"); 930 } 931 932 /* 933 * Early initialization. Relocation is on but do not reference unbolted pages 934 */ 935 static void __init pseries_init(void) 936 { 937 pr_debug(" -> pseries_init()\n"); 938 939 #ifdef CONFIG_HVC_CONSOLE 940 if (firmware_has_feature(FW_FEATURE_LPAR)) 941 hvc_vio_init_early(); 942 #endif 943 if (firmware_has_feature(FW_FEATURE_XDABR)) 944 ppc_md.set_dabr = pseries_set_xdabr; 945 else if (firmware_has_feature(FW_FEATURE_DABR)) 946 ppc_md.set_dabr = pseries_set_dabr; 947 948 if (firmware_has_feature(FW_FEATURE_SET_MODE)) 949 ppc_md.set_dawr = pseries_set_dawr; 950 951 pSeries_cmo_feature_init(); 952 iommu_init_early_pSeries(); 953 954 pr_debug(" <- pseries_init()\n"); 955 } 956 957 /** 958 * pseries_power_off - tell firmware about how to power off the system. 959 * 960 * This function calls either the power-off rtas token in normal cases 961 * or the ibm,power-off-ups token (if present & requested) in case of 962 * a power failure. If power-off token is used, power on will only be 963 * possible with power button press. If ibm,power-off-ups token is used 964 * it will allow auto poweron after power is restored. 965 */ 966 static void pseries_power_off(void) 967 { 968 int rc; 969 int rtas_poweroff_ups_token = rtas_token("ibm,power-off-ups"); 970 971 if (rtas_flash_term_hook) 972 rtas_flash_term_hook(SYS_POWER_OFF); 973 974 if (rtas_poweron_auto == 0 || 975 rtas_poweroff_ups_token == RTAS_UNKNOWN_SERVICE) { 976 rc = rtas_call(rtas_token("power-off"), 2, 1, NULL, -1, -1); 977 printk(KERN_INFO "RTAS power-off returned %d\n", rc); 978 } else { 979 rc = rtas_call(rtas_poweroff_ups_token, 0, 1, NULL); 980 printk(KERN_INFO "RTAS ibm,power-off-ups returned %d\n", rc); 981 } 982 for (;;); 983 } 984 985 static int __init pSeries_probe(void) 986 { 987 if (!of_node_is_type(of_root, "chrp")) 988 return 0; 989 990 /* Cell blades firmware claims to be chrp while it's not. Until this 991 * is fixed, we need to avoid those here. 992 */ 993 if (of_machine_is_compatible("IBM,CPBW-1.0") || 994 of_machine_is_compatible("IBM,CBEA")) 995 return 0; 996 997 pm_power_off = pseries_power_off; 998 999 pr_debug("Machine is%s LPAR !\n", 1000 (powerpc_firmware_features & FW_FEATURE_LPAR) ? "" : " not"); 1001 1002 pseries_init(); 1003 1004 return 1; 1005 } 1006 1007 static int pSeries_pci_probe_mode(struct pci_bus *bus) 1008 { 1009 if (firmware_has_feature(FW_FEATURE_LPAR)) 1010 return PCI_PROBE_DEVTREE; 1011 return PCI_PROBE_NORMAL; 1012 } 1013 1014 struct pci_controller_ops pseries_pci_controller_ops = { 1015 .probe_mode = pSeries_pci_probe_mode, 1016 }; 1017 1018 define_machine(pseries) { 1019 .name = "pSeries", 1020 .probe = pSeries_probe, 1021 .setup_arch = pSeries_setup_arch, 1022 .init_IRQ = pseries_init_irq, 1023 .show_cpuinfo = pSeries_show_cpuinfo, 1024 .log_error = pSeries_log_error, 1025 .pcibios_fixup = pSeries_final_fixup, 1026 .restart = rtas_restart, 1027 .halt = rtas_halt, 1028 .panic = pseries_panic, 1029 .get_boot_time = rtas_get_boot_time, 1030 .get_rtc_time = rtas_get_rtc_time, 1031 .set_rtc_time = rtas_set_rtc_time, 1032 .calibrate_decr = generic_calibrate_decr, 1033 .progress = rtas_progress, 1034 .system_reset_exception = pSeries_system_reset_exception, 1035 .machine_check_early = pseries_machine_check_realmode, 1036 .machine_check_exception = pSeries_machine_check_exception, 1037 #ifdef CONFIG_KEXEC_CORE 1038 .machine_kexec = pSeries_machine_kexec, 1039 .kexec_cpu_down = pseries_kexec_cpu_down, 1040 #endif 1041 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 1042 .memory_block_size = pseries_memory_block_size, 1043 #endif 1044 }; 1045