1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation 4 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 5 * 6 * pSeries specific routines for PCI. 7 */ 8 9 #include <linux/init.h> 10 #include <linux/ioport.h> 11 #include <linux/kernel.h> 12 #include <linux/pci.h> 13 #include <linux/string.h> 14 15 #include <asm/eeh.h> 16 #include <asm/pci-bridge.h> 17 #include <asm/ppc-pci.h> 18 #include <asm/pci.h> 19 #include "pseries.h" 20 21 #if 0 22 void pcibios_name_device(struct pci_dev *dev) 23 { 24 struct device_node *dn; 25 26 /* 27 * Add IBM loc code (slot) as a prefix to the device names for service 28 */ 29 dn = pci_device_to_OF_node(dev); 30 if (dn) { 31 const char *loc_code = of_get_property(dn, "ibm,loc-code", 32 NULL); 33 if (loc_code) { 34 int loc_len = strlen(loc_code); 35 if (loc_len < sizeof(dev->dev.name)) { 36 memmove(dev->dev.name+loc_len+1, dev->dev.name, 37 sizeof(dev->dev.name)-loc_len-1); 38 memcpy(dev->dev.name, loc_code, loc_len); 39 dev->dev.name[loc_len] = ' '; 40 dev->dev.name[sizeof(dev->dev.name)-1] = '\0'; 41 } 42 } 43 } 44 } 45 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device); 46 #endif 47 48 #ifdef CONFIG_PCI_IOV 49 #define MAX_VFS_FOR_MAP_PE 256 50 struct pe_map_bar_entry { 51 __be64 bar; /* Input: Virtual Function BAR */ 52 __be16 rid; /* Input: Virtual Function Router ID */ 53 __be16 pe_num; /* Output: Virtual Function PE Number */ 54 __be32 reserved; /* Reserved Space */ 55 }; 56 57 static int pseries_send_map_pe(struct pci_dev *pdev, u16 num_vfs, 58 struct pe_map_bar_entry *vf_pe_array) 59 { 60 struct pci_dn *pdn; 61 int rc; 62 unsigned long buid, addr; 63 int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number"); 64 65 if (ibm_map_pes == RTAS_UNKNOWN_SERVICE) 66 return -EINVAL; 67 68 pdn = pci_get_pdn(pdev); 69 addr = rtas_config_addr(pdn->busno, pdn->devfn, 0); 70 buid = pdn->phb->buid; 71 spin_lock(&rtas_data_buf_lock); 72 memcpy(rtas_data_buf, vf_pe_array, 73 RTAS_DATA_BUF_SIZE); 74 rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr, 75 BUID_HI(buid), BUID_LO(buid), 76 rtas_data_buf, 77 num_vfs * sizeof(struct pe_map_bar_entry)); 78 memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE); 79 spin_unlock(&rtas_data_buf_lock); 80 81 if (rc) 82 dev_err(&pdev->dev, 83 "%s: Failed to associate pes PE#%lx, rc=%x\n", 84 __func__, addr, rc); 85 86 return rc; 87 } 88 89 static void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num) 90 { 91 struct pci_dn *pdn; 92 93 pdn = pci_get_pdn(pdev); 94 pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num); 95 dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n", 96 pci_domain_nr(pdev->bus), 97 pdev->bus->number, 98 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 99 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), 100 pdn->pe_num_map[vf_index]); 101 } 102 103 static int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs) 104 { 105 struct pci_dn *pdn; 106 int i, rc, vf_index; 107 struct pe_map_bar_entry *vf_pe_array; 108 struct resource *res; 109 u64 size; 110 111 vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL); 112 if (!vf_pe_array) 113 return -ENOMEM; 114 115 pdn = pci_get_pdn(pdev); 116 /* create firmware structure to associate pes */ 117 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 118 pdn->pe_num_map[vf_index] = IODA_INVALID_PE; 119 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 120 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 121 if (!res->parent) 122 continue; 123 size = pcibios_iov_resource_alignment(pdev, i + 124 PCI_IOV_RESOURCES); 125 vf_pe_array[vf_index].bar = 126 cpu_to_be64(res->start + size * vf_index); 127 vf_pe_array[vf_index].rid = 128 cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index) 129 << 8) | pci_iov_virtfn_devfn(pdev, 130 vf_index)); 131 vf_pe_array[vf_index].pe_num = 132 cpu_to_be16(IODA_INVALID_PE); 133 } 134 } 135 136 rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array); 137 /* Only zero is success */ 138 if (!rc) 139 for (vf_index = 0; vf_index < num_vfs; vf_index++) 140 pseries_set_pe_num(pdev, vf_index, 141 vf_pe_array[vf_index].pe_num); 142 143 kfree(vf_pe_array); 144 return rc; 145 } 146 147 static int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 148 { 149 struct pci_dn *pdn; 150 int rc; 151 const int *max_vfs; 152 int max_config_vfs; 153 struct device_node *dn = pci_device_to_OF_node(pdev); 154 155 max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL); 156 157 if (!max_vfs) 158 return -EINVAL; 159 160 /* First integer stores max config */ 161 max_config_vfs = of_read_number(&max_vfs[0], 1); 162 if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) { 163 dev_err(&pdev->dev, 164 "Num VFs %x > %x Configurable VFs\n", 165 num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ? 166 MAX_VFS_FOR_MAP_PE : max_config_vfs); 167 return -EINVAL; 168 } 169 170 pdn = pci_get_pdn(pdev); 171 pdn->pe_num_map = kmalloc_array(num_vfs, 172 sizeof(*pdn->pe_num_map), 173 GFP_KERNEL); 174 if (!pdn->pe_num_map) 175 return -ENOMEM; 176 177 rc = pseries_associate_pes(pdev, num_vfs); 178 179 /* Anything other than zero is failure */ 180 if (rc) { 181 dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc); 182 kfree(pdn->pe_num_map); 183 } else { 184 pci_vf_drivers_autoprobe(pdev, false); 185 } 186 187 return rc; 188 } 189 190 static int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 191 { 192 /* Allocate PCI data */ 193 add_sriov_vf_pdns(pdev); 194 return pseries_pci_sriov_enable(pdev, num_vfs); 195 } 196 197 static int pseries_pcibios_sriov_disable(struct pci_dev *pdev) 198 { 199 struct pci_dn *pdn; 200 201 pdn = pci_get_pdn(pdev); 202 /* Releasing pe_num_map */ 203 kfree(pdn->pe_num_map); 204 /* Release PCI data */ 205 remove_sriov_vf_pdns(pdev); 206 pci_vf_drivers_autoprobe(pdev, true); 207 return 0; 208 } 209 #endif 210 211 static void __init pSeries_request_regions(void) 212 { 213 if (!isa_io_base) 214 return; 215 216 request_region(0x20,0x20,"pic1"); 217 request_region(0xa0,0x20,"pic2"); 218 request_region(0x00,0x20,"dma1"); 219 request_region(0x40,0x20,"timer"); 220 request_region(0x80,0x10,"dma page reg"); 221 request_region(0xc0,0x20,"dma2"); 222 } 223 224 void __init pSeries_final_fixup(void) 225 { 226 pSeries_request_regions(); 227 228 eeh_show_enabled(); 229 230 #ifdef CONFIG_PCI_IOV 231 ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable; 232 ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable; 233 #endif 234 } 235 236 /* 237 * Assume the winbond 82c105 is the IDE controller on a 238 * p610/p615/p630. We should probably be more careful in case 239 * someone tries to plug in a similar adapter. 240 */ 241 static void fixup_winbond_82c105(struct pci_dev* dev) 242 { 243 int i; 244 unsigned int reg; 245 246 if (!machine_is(pseries)) 247 return; 248 249 printk("Using INTC for W82c105 IDE controller.\n"); 250 pci_read_config_dword(dev, 0x40, ®); 251 /* Enable LEGIRQ to use INTC instead of ISA interrupts */ 252 pci_write_config_dword(dev, 0x40, reg | (1<<11)); 253 254 for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) { 255 /* zap the 2nd function of the winbond chip */ 256 if (dev->resource[i].flags & IORESOURCE_IO 257 && dev->bus->number == 0 && dev->devfn == 0x81) 258 dev->resource[i].flags &= ~IORESOURCE_IO; 259 if (dev->resource[i].start == 0 && dev->resource[i].end) { 260 dev->resource[i].flags = 0; 261 dev->resource[i].end = 0; 262 } 263 } 264 } 265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, 266 fixup_winbond_82c105); 267 268 static enum pci_bus_speed prop_to_pci_speed(u32 prop) 269 { 270 switch (prop) { 271 case 0x01: 272 return PCIE_SPEED_2_5GT; 273 case 0x02: 274 return PCIE_SPEED_5_0GT; 275 case 0x04: 276 return PCIE_SPEED_8_0GT; 277 case 0x08: 278 return PCIE_SPEED_16_0GT; 279 case 0x10: 280 return PCIE_SPEED_32_0GT; 281 default: 282 pr_debug("Unexpected PCI link speed property value\n"); 283 return PCI_SPEED_UNKNOWN; 284 } 285 } 286 287 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge) 288 { 289 struct device_node *dn, *pdn; 290 struct pci_bus *bus; 291 u32 pcie_link_speed_stats[2]; 292 int rc; 293 294 bus = bridge->bus; 295 296 /* Rely on the pcibios_free_controller_deferred() callback. */ 297 pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred, 298 (void *) pci_bus_to_host(bus)); 299 300 dn = pcibios_get_phb_of_node(bus); 301 if (!dn) 302 return 0; 303 304 for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) { 305 rc = of_property_read_u32_array(pdn, 306 "ibm,pcie-link-speed-stats", 307 &pcie_link_speed_stats[0], 2); 308 if (!rc) 309 break; 310 } 311 312 of_node_put(pdn); 313 314 if (rc) { 315 pr_debug("no ibm,pcie-link-speed-stats property\n"); 316 return 0; 317 } 318 319 bus->max_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[0]); 320 bus->cur_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[1]); 321 return 0; 322 } 323