1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV setup code. 4 * 5 * Copyright 2011 IBM Corp. 6 */ 7 8 #undef DEBUG 9 10 #include <linux/cpu.h> 11 #include <linux/errno.h> 12 #include <linux/sched.h> 13 #include <linux/kernel.h> 14 #include <linux/tty.h> 15 #include <linux/reboot.h> 16 #include <linux/init.h> 17 #include <linux/console.h> 18 #include <linux/delay.h> 19 #include <linux/irq.h> 20 #include <linux/seq_file.h> 21 #include <linux/of.h> 22 #include <linux/of_fdt.h> 23 #include <linux/interrupt.h> 24 #include <linux/bug.h> 25 #include <linux/pci.h> 26 #include <linux/cpufreq.h> 27 #include <linux/memblock.h> 28 29 #include <asm/machdep.h> 30 #include <asm/firmware.h> 31 #include <asm/xics.h> 32 #include <asm/xive.h> 33 #include <asm/opal.h> 34 #include <asm/kexec.h> 35 #include <asm/smp.h> 36 #include <asm/tm.h> 37 #include <asm/setup.h> 38 #include <asm/security_features.h> 39 40 #include "powernv.h" 41 42 43 static bool __init fw_feature_is(const char *state, const char *name, 44 struct device_node *fw_features) 45 { 46 struct device_node *np; 47 bool rc = false; 48 49 np = of_get_child_by_name(fw_features, name); 50 if (np) { 51 rc = of_property_read_bool(np, state); 52 of_node_put(np); 53 } 54 55 return rc; 56 } 57 58 static void __init init_fw_feat_flags(struct device_node *np) 59 { 60 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np)) 61 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31); 62 63 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np)) 64 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED); 65 66 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np)) 67 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30); 68 69 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np)) 70 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2); 71 72 if (fw_feature_is("enabled", "fw-l1d-thread-split", np)) 73 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV); 74 75 if (fw_feature_is("enabled", "fw-count-cache-disabled", np)) 76 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED); 77 78 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np)) 79 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST); 80 81 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np)) 82 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE); 83 84 /* 85 * The features below are enabled by default, so we instead look to see 86 * if firmware has *disabled* them, and clear them if so. 87 */ 88 if (fw_feature_is("disabled", "speculation-policy-favor-security", np)) 89 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); 90 91 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np)) 92 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); 93 94 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np)) 95 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV); 96 97 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np)) 98 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); 99 100 if (fw_feature_is("enabled", "no-need-l1d-flush-msr-pr-1-to-0", np)) 101 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY); 102 103 if (fw_feature_is("enabled", "no-need-l1d-flush-kernel-on-user-access", np)) 104 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS); 105 106 if (fw_feature_is("enabled", "no-need-store-drain-on-priv-state-switch", np)) 107 security_ftr_clear(SEC_FTR_STF_BARRIER); 108 } 109 110 static void __init pnv_setup_security_mitigations(void) 111 { 112 struct device_node *np, *fw_features; 113 enum l1d_flush_type type; 114 bool enable; 115 116 /* Default to fallback in case fw-features are not available */ 117 type = L1D_FLUSH_FALLBACK; 118 119 np = of_find_node_by_name(NULL, "ibm,opal"); 120 fw_features = of_get_child_by_name(np, "fw-features"); 121 of_node_put(np); 122 123 if (fw_features) { 124 init_fw_feat_flags(fw_features); 125 of_node_put(fw_features); 126 127 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2)) 128 type = L1D_FLUSH_MTTRIG; 129 130 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30)) 131 type = L1D_FLUSH_ORI; 132 } 133 134 /* 135 * The issues addressed by the entry and uaccess flush don't affect P7 136 * or P8, so on bare metal disable them explicitly in case firmware does 137 * not include the features to disable them. POWER9 and newer processors 138 * should have the appropriate firmware flags. 139 */ 140 if (pvr_version_is(PVR_POWER7) || pvr_version_is(PVR_POWER7p) || 141 pvr_version_is(PVR_POWER8E) || pvr_version_is(PVR_POWER8NVL) || 142 pvr_version_is(PVR_POWER8)) { 143 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY); 144 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS); 145 } 146 147 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \ 148 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \ 149 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV)); 150 151 setup_rfi_flush(type, enable); 152 setup_count_cache_flush(); 153 154 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 155 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY); 156 setup_entry_flush(enable); 157 158 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 159 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS); 160 setup_uaccess_flush(enable); 161 162 setup_stf_barrier(); 163 } 164 165 static void __init pnv_check_guarded_cores(void) 166 { 167 struct device_node *dn; 168 int bad_count = 0; 169 170 for_each_node_by_type(dn, "cpu") { 171 if (of_property_match_string(dn, "status", "bad") >= 0) 172 bad_count++; 173 } 174 175 if (bad_count) { 176 printk(" _ _______________\n"); 177 pr_cont(" | | / \\\n"); 178 pr_cont(" | | | WARNING! |\n"); 179 pr_cont(" | | | |\n"); 180 pr_cont(" | | | It looks like |\n"); 181 pr_cont(" |_| | you have %*d |\n", 3, bad_count); 182 pr_cont(" _ | guarded cores |\n"); 183 pr_cont(" (_) \\_______________/\n"); 184 } 185 } 186 187 static void __init pnv_setup_arch(void) 188 { 189 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); 190 191 pnv_setup_security_mitigations(); 192 193 /* Initialize SMP */ 194 pnv_smp_init(); 195 196 /* Setup RTC and NVRAM callbacks */ 197 if (firmware_has_feature(FW_FEATURE_OPAL)) 198 opal_nvram_init(); 199 200 /* Enable NAP mode */ 201 powersave_nap = 1; 202 203 pnv_check_guarded_cores(); 204 205 /* XXX PMCS */ 206 } 207 208 static void __init pnv_init(void) 209 { 210 /* 211 * Initialize the LPC bus now so that legacy serial 212 * ports can be found on it 213 */ 214 opal_lpc_init(); 215 216 #ifdef CONFIG_HVC_OPAL 217 if (firmware_has_feature(FW_FEATURE_OPAL)) 218 hvc_opal_init_early(); 219 else 220 #endif 221 add_preferred_console("hvc", 0, NULL); 222 223 #ifdef CONFIG_PPC_64S_HASH_MMU 224 if (!radix_enabled()) { 225 size_t size = sizeof(struct slb_entry) * mmu_slb_size; 226 int i; 227 228 /* Allocate per cpu area to save old slb contents during MCE */ 229 for_each_possible_cpu(i) { 230 paca_ptrs[i]->mce_faulty_slbs = 231 memblock_alloc_node(size, 232 __alignof__(struct slb_entry), 233 cpu_to_node(i)); 234 } 235 } 236 #endif 237 } 238 239 static void __init pnv_init_IRQ(void) 240 { 241 /* Try using a XIVE if available, otherwise use a XICS */ 242 if (!xive_native_init()) 243 xics_init(); 244 245 WARN_ON(!ppc_md.get_irq); 246 } 247 248 static void pnv_show_cpuinfo(struct seq_file *m) 249 { 250 struct device_node *root; 251 const char *model = ""; 252 253 root = of_find_node_by_path("/"); 254 if (root) 255 model = of_get_property(root, "model", NULL); 256 seq_printf(m, "machine\t\t: PowerNV %s\n", model); 257 if (firmware_has_feature(FW_FEATURE_OPAL)) 258 seq_printf(m, "firmware\t: OPAL\n"); 259 else 260 seq_printf(m, "firmware\t: BML\n"); 261 of_node_put(root); 262 if (radix_enabled()) 263 seq_printf(m, "MMU\t\t: Radix\n"); 264 else 265 seq_printf(m, "MMU\t\t: Hash\n"); 266 } 267 268 static void pnv_prepare_going_down(void) 269 { 270 /* 271 * Disable all notifiers from OPAL, we can't 272 * service interrupts anymore anyway 273 */ 274 opal_event_shutdown(); 275 276 /* Print flash update message if one is scheduled. */ 277 opal_flash_update_print_message(); 278 279 smp_send_stop(); 280 281 hard_irq_disable(); 282 } 283 284 static void __noreturn pnv_restart(char *cmd) 285 { 286 long rc; 287 288 pnv_prepare_going_down(); 289 290 do { 291 if (!cmd || !strlen(cmd)) 292 rc = opal_cec_reboot(); 293 else if (strcmp(cmd, "full") == 0) 294 rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL); 295 else if (strcmp(cmd, "mpipl") == 0) 296 rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL); 297 else if (strcmp(cmd, "error") == 0) 298 rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL); 299 else if (strcmp(cmd, "fast") == 0) 300 rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL); 301 else 302 rc = OPAL_UNSUPPORTED; 303 304 if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 305 /* Opal is busy wait for some time and retry */ 306 opal_poll_events(NULL); 307 mdelay(10); 308 309 } else if (cmd && rc) { 310 /* Unknown error while issuing reboot */ 311 if (rc == OPAL_UNSUPPORTED) 312 pr_err("Unsupported '%s' reboot.\n", cmd); 313 else 314 pr_err("Unable to issue '%s' reboot. Err=%ld\n", 315 cmd, rc); 316 pr_info("Forcing a cec-reboot\n"); 317 cmd = NULL; 318 rc = OPAL_BUSY; 319 320 } else if (rc != OPAL_SUCCESS) { 321 /* Unknown error while issuing cec-reboot */ 322 pr_err("Unable to reboot. Err=%ld\n", rc); 323 } 324 325 } while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT); 326 327 for (;;) 328 opal_poll_events(NULL); 329 } 330 331 static void __noreturn pnv_power_off(void) 332 { 333 long rc = OPAL_BUSY; 334 335 pnv_prepare_going_down(); 336 337 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 338 rc = opal_cec_power_down(0); 339 if (rc == OPAL_BUSY_EVENT) 340 opal_poll_events(NULL); 341 else 342 mdelay(10); 343 } 344 for (;;) 345 opal_poll_events(NULL); 346 } 347 348 static void __noreturn pnv_halt(void) 349 { 350 pnv_power_off(); 351 } 352 353 static void pnv_progress(char *s, unsigned short hex) 354 { 355 } 356 357 static void pnv_shutdown(void) 358 { 359 /* Let the PCI code clear up IODA tables */ 360 pnv_pci_shutdown(); 361 362 /* 363 * Stop OPAL activity: Unregister all OPAL interrupts so they 364 * don't fire up while we kexec and make sure all potentially 365 * DMA'ing ops are complete (such as dump retrieval). 366 */ 367 opal_shutdown(); 368 } 369 370 #ifdef CONFIG_KEXEC_CORE 371 static void pnv_kexec_wait_secondaries_down(void) 372 { 373 int my_cpu, i, notified = -1; 374 375 my_cpu = get_cpu(); 376 377 for_each_online_cpu(i) { 378 uint8_t status; 379 int64_t rc, timeout = 1000; 380 381 if (i == my_cpu) 382 continue; 383 384 for (;;) { 385 rc = opal_query_cpu_status(get_hard_smp_processor_id(i), 386 &status); 387 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED) 388 break; 389 barrier(); 390 if (i != notified) { 391 printk(KERN_INFO "kexec: waiting for cpu %d " 392 "(physical %d) to enter OPAL\n", 393 i, paca_ptrs[i]->hw_cpu_id); 394 notified = i; 395 } 396 397 /* 398 * On crash secondaries might be unreachable or hung, 399 * so timeout if we've waited too long 400 * */ 401 mdelay(1); 402 if (timeout-- == 0) { 403 printk(KERN_ERR "kexec: timed out waiting for " 404 "cpu %d (physical %d) to enter OPAL\n", 405 i, paca_ptrs[i]->hw_cpu_id); 406 break; 407 } 408 } 409 } 410 } 411 412 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) 413 { 414 u64 reinit_flags; 415 416 if (xive_enabled()) 417 xive_teardown_cpu(); 418 else 419 xics_kexec_teardown_cpu(secondary); 420 421 /* On OPAL, we return all CPUs to firmware */ 422 if (!firmware_has_feature(FW_FEATURE_OPAL)) 423 return; 424 425 if (secondary) { 426 /* Return secondary CPUs to firmware on OPAL v3 */ 427 mb(); 428 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE; 429 mb(); 430 431 /* Return the CPU to OPAL */ 432 opal_return_cpu(); 433 } else { 434 /* Primary waits for the secondaries to have reached OPAL */ 435 pnv_kexec_wait_secondaries_down(); 436 437 /* Switch XIVE back to emulation mode */ 438 if (xive_enabled()) 439 xive_shutdown(); 440 441 /* 442 * We might be running as little-endian - now that interrupts 443 * are disabled, reset the HILE bit to big-endian so we don't 444 * take interrupts in the wrong endian later 445 * 446 * We reinit to enable both radix and hash on P9 to ensure 447 * the mode used by the next kernel is always supported. 448 */ 449 reinit_flags = OPAL_REINIT_CPUS_HILE_BE; 450 if (cpu_has_feature(CPU_FTR_ARCH_300)) 451 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX | 452 OPAL_REINIT_CPUS_MMU_HASH; 453 opal_reinit_cpus(reinit_flags); 454 } 455 } 456 #endif /* CONFIG_KEXEC_CORE */ 457 458 #ifdef CONFIG_MEMORY_HOTPLUG 459 static unsigned long pnv_memory_block_size(void) 460 { 461 /* 462 * We map the kernel linear region with 1GB large pages on radix. For 463 * memory hot unplug to work our memory block size must be at least 464 * this size. 465 */ 466 if (radix_enabled()) 467 return radix_mem_block_size; 468 else 469 return 256UL * 1024 * 1024; 470 } 471 #endif 472 473 static void __init pnv_setup_machdep_opal(void) 474 { 475 ppc_md.get_boot_time = opal_get_boot_time; 476 ppc_md.restart = pnv_restart; 477 pm_power_off = pnv_power_off; 478 ppc_md.halt = pnv_halt; 479 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */ 480 ppc_md.machine_check_exception = opal_machine_check; 481 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery; 482 if (opal_check_token(OPAL_HANDLE_HMI2)) 483 ppc_md.hmi_exception_early = opal_hmi_exception_early2; 484 else 485 ppc_md.hmi_exception_early = opal_hmi_exception_early; 486 ppc_md.handle_hmi_exception = opal_handle_hmi_exception; 487 } 488 489 static int __init pnv_probe(void) 490 { 491 if (!of_machine_is_compatible("ibm,powernv")) 492 return 0; 493 494 if (firmware_has_feature(FW_FEATURE_OPAL)) 495 pnv_setup_machdep_opal(); 496 497 pr_debug("PowerNV detected !\n"); 498 499 pnv_init(); 500 501 return 1; 502 } 503 504 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 505 void __init pnv_tm_init(void) 506 { 507 if (!firmware_has_feature(FW_FEATURE_OPAL) || 508 !pvr_version_is(PVR_POWER9) || 509 early_cpu_has_feature(CPU_FTR_TM)) 510 return; 511 512 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS) 513 return; 514 515 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n"); 516 cur_cpu_spec->cpu_features |= CPU_FTR_TM; 517 /* Make sure "normal" HTM is off (it should be) */ 518 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM; 519 /* Turn on no suspend mode, and HTM no SC */ 520 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \ 521 PPC_FEATURE2_HTM_NOSC; 522 tm_suspend_disabled = true; 523 } 524 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 525 526 /* 527 * Returns the cpu frequency for 'cpu' in Hz. This is used by 528 * /proc/cpuinfo 529 */ 530 static unsigned long pnv_get_proc_freq(unsigned int cpu) 531 { 532 unsigned long ret_freq; 533 534 ret_freq = cpufreq_get(cpu) * 1000ul; 535 536 /* 537 * If the backend cpufreq driver does not exist, 538 * then fallback to old way of reporting the clockrate. 539 */ 540 if (!ret_freq) 541 ret_freq = ppc_proc_freq; 542 return ret_freq; 543 } 544 545 static long pnv_machine_check_early(struct pt_regs *regs) 546 { 547 long handled = 0; 548 549 if (cur_cpu_spec && cur_cpu_spec->machine_check_early) 550 handled = cur_cpu_spec->machine_check_early(regs); 551 552 return handled; 553 } 554 555 define_machine(powernv) { 556 .name = "PowerNV", 557 .probe = pnv_probe, 558 .setup_arch = pnv_setup_arch, 559 .init_IRQ = pnv_init_IRQ, 560 .show_cpuinfo = pnv_show_cpuinfo, 561 .get_proc_freq = pnv_get_proc_freq, 562 .discover_phbs = pnv_pci_init, 563 .progress = pnv_progress, 564 .machine_shutdown = pnv_shutdown, 565 .power_save = NULL, 566 .calibrate_decr = generic_calibrate_decr, 567 .machine_check_early = pnv_machine_check_early, 568 #ifdef CONFIG_KEXEC_CORE 569 .kexec_cpu_down = pnv_kexec_cpu_down, 570 #endif 571 #ifdef CONFIG_MEMORY_HOTPLUG 572 .memory_block_size = pnv_memory_block_size, 573 #endif 574 }; 575