1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 struct pci_dn; 5 6 enum pnv_phb_type { 7 PNV_PHB_P5IOC2 = 0, 8 PNV_PHB_IODA1 = 1, 9 PNV_PHB_IODA2 = 2, 10 }; 11 12 /* Precise PHB model for error management */ 13 enum pnv_phb_model { 14 PNV_PHB_MODEL_UNKNOWN, 15 PNV_PHB_MODEL_P5IOC2, 16 PNV_PHB_MODEL_P7IOC, 17 PNV_PHB_MODEL_PHB3, 18 }; 19 20 #define PNV_PCI_DIAG_BUF_SIZE 8192 21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 26 27 /* Data associated with a PE, including IOMMU tracking etc.. */ 28 struct pnv_phb; 29 struct pnv_ioda_pe { 30 unsigned long flags; 31 struct pnv_phb *phb; 32 33 /* A PE can be associated with a single device or an 34 * entire bus (& children). In the former case, pdev 35 * is populated, in the later case, pbus is. 36 */ 37 struct pci_dev *pdev; 38 struct pci_bus *pbus; 39 40 /* Effective RID (device RID for a device PE and base bus 41 * RID with devfn 0 for a bus PE) 42 */ 43 unsigned int rid; 44 45 /* PE number */ 46 unsigned int pe_number; 47 48 /* "Weight" assigned to the PE for the sake of DMA resource 49 * allocations 50 */ 51 unsigned int dma_weight; 52 53 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 54 int tce32_seg; 55 int tce32_segcount; 56 struct iommu_table tce32_table; 57 phys_addr_t tce_inval_reg_phys; 58 59 /* 64-bit TCE bypass region */ 60 bool tce_bypass_enabled; 61 uint64_t tce_bypass_base; 62 63 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 64 * and -1 if not supported. (It's actually identical to the 65 * PE number) 66 */ 67 int mve_number; 68 69 /* PEs in compound case */ 70 struct pnv_ioda_pe *master; 71 struct list_head slaves; 72 73 /* Link in list of PE#s */ 74 struct list_head dma_link; 75 struct list_head list; 76 }; 77 78 /* IOC dependent EEH operations */ 79 #ifdef CONFIG_EEH 80 struct pnv_eeh_ops { 81 int (*post_init)(struct pci_controller *hose); 82 int (*set_option)(struct eeh_pe *pe, int option); 83 int (*get_state)(struct eeh_pe *pe); 84 int (*reset)(struct eeh_pe *pe, int option); 85 int (*get_log)(struct eeh_pe *pe, int severity, 86 char *drv_log, unsigned long len); 87 int (*configure_bridge)(struct eeh_pe *pe); 88 int (*err_inject)(struct eeh_pe *pe, int type, int func, 89 unsigned long addr, unsigned long mask); 90 int (*next_error)(struct eeh_pe **pe); 91 }; 92 #endif /* CONFIG_EEH */ 93 94 #define PNV_PHB_FLAG_EEH (1 << 0) 95 96 struct pnv_phb { 97 struct pci_controller *hose; 98 enum pnv_phb_type type; 99 enum pnv_phb_model model; 100 u64 hub_id; 101 u64 opal_id; 102 int flags; 103 void __iomem *regs; 104 int initialized; 105 spinlock_t lock; 106 107 #ifdef CONFIG_EEH 108 struct pnv_eeh_ops *eeh_ops; 109 #endif 110 111 #ifdef CONFIG_DEBUG_FS 112 int has_dbgfs; 113 struct dentry *dbgfs; 114 #endif 115 116 #ifdef CONFIG_PCI_MSI 117 unsigned int msi_base; 118 unsigned int msi32_support; 119 struct msi_bitmap msi_bmp; 120 #endif 121 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 122 unsigned int hwirq, unsigned int virq, 123 unsigned int is_64, struct msi_msg *msg); 124 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 125 int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev, 126 u64 dma_mask); 127 u64 (*dma_get_required_mask)(struct pnv_phb *phb, 128 struct pci_dev *pdev); 129 void (*fixup_phb)(struct pci_controller *hose); 130 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 131 void (*shutdown)(struct pnv_phb *phb); 132 int (*init_m64)(struct pnv_phb *phb); 133 void (*reserve_m64_pe)(struct pnv_phb *phb); 134 int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all); 135 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 136 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 137 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 138 139 union { 140 struct { 141 struct iommu_table iommu_table; 142 } p5ioc2; 143 144 struct { 145 /* Global bridge info */ 146 unsigned int total_pe; 147 unsigned int reserved_pe; 148 149 /* 32-bit MMIO window */ 150 unsigned int m32_size; 151 unsigned int m32_segsize; 152 unsigned int m32_pci_base; 153 154 /* 64-bit MMIO window */ 155 unsigned int m64_bar_idx; 156 unsigned long m64_size; 157 unsigned long m64_segsize; 158 unsigned long m64_base; 159 unsigned long m64_bar_alloc; 160 161 /* IO ports */ 162 unsigned int io_size; 163 unsigned int io_segsize; 164 unsigned int io_pci_base; 165 166 /* PE allocation bitmap */ 167 unsigned long *pe_alloc; 168 169 /* M32 & IO segment maps */ 170 unsigned int *m32_segmap; 171 unsigned int *io_segmap; 172 struct pnv_ioda_pe *pe_array; 173 174 /* IRQ chip */ 175 int irq_chip_init; 176 struct irq_chip irq_chip; 177 178 /* Sorted list of used PE's based 179 * on the sequence of creation 180 */ 181 struct list_head pe_list; 182 183 /* Reverse map of PEs, will have to extend if 184 * we are to support more than 256 PEs, indexed 185 * bus { bus, devfn } 186 */ 187 unsigned char pe_rmap[0x10000]; 188 189 /* 32-bit TCE tables allocation */ 190 unsigned long tce32_count; 191 192 /* Total "weight" for the sake of DMA resources 193 * allocation 194 */ 195 unsigned int dma_weight; 196 unsigned int dma_pe_count; 197 198 /* Sorted list of used PE's, sorted at 199 * boot for resource allocation purposes 200 */ 201 struct list_head pe_dma_list; 202 } ioda; 203 }; 204 205 /* PHB and hub status structure */ 206 union { 207 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 208 struct OpalIoP7IOCPhbErrorData p7ioc; 209 struct OpalIoPhb3ErrorData phb3; 210 struct OpalIoP7IOCErrorData hub_diag; 211 } diag; 212 213 }; 214 215 extern struct pci_ops pnv_pci_ops; 216 #ifdef CONFIG_EEH 217 extern struct pnv_eeh_ops ioda_eeh_ops; 218 #endif 219 220 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 221 unsigned char *log_buff); 222 int pnv_pci_cfg_read(struct device_node *dn, 223 int where, int size, u32 *val); 224 int pnv_pci_cfg_write(struct device_node *dn, 225 int where, int size, u32 val); 226 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 227 void *tce_mem, u64 tce_size, 228 u64 dma_offset, unsigned page_shift); 229 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 230 extern void pnv_pci_init_ioda_hub(struct device_node *np); 231 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 232 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 233 __be64 *startp, __be64 *endp, bool rm); 234 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 235 extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option); 236 237 #endif /* __POWERNV_PCI_H */ 238