1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __POWERNV_PCI_H 3 #define __POWERNV_PCI_H 4 5 #include <linux/compiler.h> /* for __printf */ 6 #include <linux/iommu.h> 7 #include <asm/iommu.h> 8 #include <asm/msi_bitmap.h> 9 10 struct pci_dn; 11 12 enum pnv_phb_type { 13 PNV_PHB_IODA2, 14 PNV_PHB_NPU_OCAPI, 15 }; 16 17 /* Precise PHB model for error management */ 18 enum pnv_phb_model { 19 PNV_PHB_MODEL_UNKNOWN, 20 PNV_PHB_MODEL_P7IOC, 21 PNV_PHB_MODEL_PHB3, 22 }; 23 24 #define PNV_PCI_DIAG_BUF_SIZE 8192 25 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 26 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 27 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 28 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 29 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 30 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 31 32 /* 33 * A brief note on PNV_IODA_PE_BUS_ALL 34 * 35 * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses 36 * the Requester ID field of the PCIe request header to determine the device 37 * (and PE) that initiated a DMA. In legacy PCI individual memory read/write 38 * requests aren't tagged with the RID. To work around this the PCIe-to-PCI 39 * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side. 40 * 41 * PCIe-to-X bridges have a similar issue even though PCI-X requests also have 42 * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take 43 * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe 44 * side of the bridge. 45 * 46 * To work around these problems we use the BUS_ALL flag since every subordinate 47 * bus of the bridge should go into the same PE. 48 */ 49 50 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 51 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 52 53 /* Data associated with a PE, including IOMMU tracking etc.. */ 54 struct pnv_phb; 55 struct pnv_ioda_pe { 56 unsigned long flags; 57 struct pnv_phb *phb; 58 int device_count; 59 60 /* A PE can be associated with a single device or an 61 * entire bus (& children). In the former case, pdev 62 * is populated, in the later case, pbus is. 63 */ 64 #ifdef CONFIG_PCI_IOV 65 struct pci_dev *parent_dev; 66 #endif 67 struct pci_dev *pdev; 68 struct pci_bus *pbus; 69 70 /* Effective RID (device RID for a device PE and base bus 71 * RID with devfn 0 for a bus PE) 72 */ 73 unsigned int rid; 74 75 /* PE number */ 76 unsigned int pe_number; 77 78 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 79 struct iommu_table_group table_group; 80 81 /* 64-bit TCE bypass region */ 82 bool tce_bypass_enabled; 83 uint64_t tce_bypass_base; 84 85 /* 86 * Used to track whether we've done DMA setup for this PE or not. We 87 * want to defer allocating TCE tables, etc until we've added a 88 * non-bridge device to the PE. 89 */ 90 bool dma_setup_done; 91 92 /* MSIs. MVE index is identical for 32 and 64 bit MSI 93 * and -1 if not supported. (It's actually identical to the 94 * PE number) 95 */ 96 int mve_number; 97 98 /* PEs in compound case */ 99 struct pnv_ioda_pe *master; 100 struct list_head slaves; 101 102 /* Link in list of PE#s */ 103 struct list_head list; 104 }; 105 106 #define PNV_PHB_FLAG_EEH (1 << 0) 107 108 struct pnv_phb { 109 struct pci_controller *hose; 110 enum pnv_phb_type type; 111 enum pnv_phb_model model; 112 u64 hub_id; 113 u64 opal_id; 114 int flags; 115 void __iomem *regs; 116 u64 regs_phys; 117 spinlock_t lock; 118 119 #ifdef CONFIG_DEBUG_FS 120 int has_dbgfs; 121 struct dentry *dbgfs; 122 #endif 123 124 unsigned int msi_base; 125 struct msi_bitmap msi_bmp; 126 int (*init_m64)(struct pnv_phb *phb); 127 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 128 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 129 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 130 131 struct { 132 /* Global bridge info */ 133 unsigned int total_pe_num; 134 unsigned int reserved_pe_idx; 135 unsigned int root_pe_idx; 136 137 /* 32-bit MMIO window */ 138 unsigned int m32_size; 139 unsigned int m32_segsize; 140 unsigned int m32_pci_base; 141 142 /* 64-bit MMIO window */ 143 unsigned int m64_bar_idx; 144 unsigned long m64_size; 145 unsigned long m64_segsize; 146 unsigned long m64_base; 147 #define MAX_M64_BARS 64 148 unsigned long m64_bar_alloc; 149 150 /* IO ports */ 151 unsigned int io_size; 152 unsigned int io_segsize; 153 unsigned int io_pci_base; 154 155 /* PE allocation */ 156 struct mutex pe_alloc_mutex; 157 unsigned long *pe_alloc; 158 struct pnv_ioda_pe *pe_array; 159 160 /* M32 & IO segment maps */ 161 unsigned int *m64_segmap; 162 unsigned int *m32_segmap; 163 unsigned int *io_segmap; 164 165 /* IRQ chip */ 166 struct irq_chip irq_chip; 167 168 /* Sorted list of used PE's based 169 * on the sequence of creation 170 */ 171 struct list_head pe_list; 172 struct mutex pe_list_mutex; 173 174 /* Reverse map of PEs, indexed by {bus, devfn} */ 175 unsigned int pe_rmap[0x10000]; 176 } ioda; 177 178 /* PHB and hub diagnostics */ 179 unsigned int diag_data_size; 180 u8 *diag_data; 181 }; 182 183 184 /* IODA PE management */ 185 186 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 187 { 188 /* 189 * WARNING: We cannot rely on the resource flags. The Linux PCI 190 * allocation code sometimes decides to put a 64-bit prefetchable 191 * BAR in the 32-bit window, so we have to compare the addresses. 192 * 193 * For simplicity we only test resource start. 194 */ 195 return (r->start >= phb->ioda.m64_base && 196 r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 197 } 198 199 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 200 { 201 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 202 203 return (resource_flags & flags) == flags; 204 } 205 206 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 207 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 208 209 void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 210 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe); 211 212 struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count); 213 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe); 214 215 #ifdef CONFIG_PCI_IOV 216 /* 217 * For SR-IOV we want to put each VF's MMIO resource in to a separate PE. 218 * This requires a bit of acrobatics with the MMIO -> PE configuration 219 * and this structure is used to keep track of it all. 220 */ 221 struct pnv_iov_data { 222 /* number of VFs enabled */ 223 u16 num_vfs; 224 225 /* pointer to the array of VF PEs. num_vfs long*/ 226 struct pnv_ioda_pe *vf_pe_arr; 227 228 /* Did we map the VF BAR with single-PE IODA BARs? */ 229 bool m64_single_mode[PCI_SRIOV_NUM_BARS]; 230 231 /* 232 * True if we're using any segmented windows. In that case we need 233 * shift the start of the IOV resource the segment corresponding to 234 * the allocated PE. 235 */ 236 bool need_shift; 237 238 /* 239 * Bit mask used to track which m64 windows are used to map the 240 * SR-IOV BARs for this device. 241 */ 242 DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS); 243 244 /* 245 * If we map the SR-IOV BARs with a segmented window then 246 * parts of that window will be "claimed" by other PEs. 247 * 248 * "holes" here is used to reserve the leading portion 249 * of the window that is used by other (non VF) PEs. 250 */ 251 struct resource holes[PCI_SRIOV_NUM_BARS]; 252 }; 253 254 static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev) 255 { 256 return pdev->dev.archdata.iov_data; 257 } 258 259 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev); 260 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno); 261 262 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 263 int pnv_pcibios_sriov_disable(struct pci_dev *pdev); 264 #endif /* CONFIG_PCI_IOV */ 265 266 extern struct pci_ops pnv_pci_ops; 267 268 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 269 unsigned char *log_buff); 270 int pnv_pci_cfg_read(struct pci_dn *pdn, 271 int where, int size, u32 *val); 272 int pnv_pci_cfg_write(struct pci_dn *pdn, 273 int where, int size, u32 val); 274 extern struct iommu_table *pnv_pci_table_alloc(int nid); 275 276 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 277 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 278 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 279 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 280 281 extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn); 282 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 283 extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 284 __u64 window_size, __u32 levels); 285 extern int pnv_eeh_post_init(void); 286 287 __printf(3, 4) 288 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 289 const char *fmt, ...); 290 #define pe_err(pe, fmt, ...) \ 291 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 292 #define pe_warn(pe, fmt, ...) \ 293 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 294 #define pe_info(pe, fmt, ...) \ 295 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 296 297 /* pci-ioda-tce.c */ 298 #define POWERNV_IOMMU_DEFAULT_LEVELS 2 299 #define POWERNV_IOMMU_MAX_LEVELS 5 300 301 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 302 unsigned long uaddr, enum dma_data_direction direction, 303 unsigned long attrs); 304 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 305 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 306 unsigned long *hpa, enum dma_data_direction *direction); 307 extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 308 bool alloc); 309 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 310 311 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 312 __u32 page_shift, __u64 window_size, __u32 levels, 313 bool alloc_userspace_copy, struct iommu_table *tbl); 314 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 315 316 extern long pnv_pci_link_table_and_group(int node, int num, 317 struct iommu_table *tbl, 318 struct iommu_table_group *table_group); 319 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 320 struct iommu_table_group *table_group); 321 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 322 void *tce_mem, u64 tce_size, 323 u64 dma_offset, unsigned int page_shift); 324 325 extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 326 327 static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus) 328 { 329 struct pci_controller *hose = bus->sysdata; 330 331 if (hose) 332 return hose->private_data; 333 334 return NULL; 335 } 336 337 #endif /* __POWERNV_PCI_H */ 338