1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 struct pci_dn; 5 6 enum pnv_phb_type { 7 PNV_PHB_IODA1 = 0, 8 PNV_PHB_IODA2 = 1, 9 PNV_PHB_NPU = 2, 10 }; 11 12 /* Precise PHB model for error management */ 13 enum pnv_phb_model { 14 PNV_PHB_MODEL_UNKNOWN, 15 PNV_PHB_MODEL_P7IOC, 16 PNV_PHB_MODEL_PHB3, 17 PNV_PHB_MODEL_NPU, 18 }; 19 20 #define PNV_PCI_DIAG_BUF_SIZE 8192 21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 26 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 27 28 /* Data associated with a PE, including IOMMU tracking etc.. */ 29 struct pnv_phb; 30 struct pnv_ioda_pe { 31 unsigned long flags; 32 struct pnv_phb *phb; 33 int device_count; 34 35 /* A PE can be associated with a single device or an 36 * entire bus (& children). In the former case, pdev 37 * is populated, in the later case, pbus is. 38 */ 39 #ifdef CONFIG_PCI_IOV 40 struct pci_dev *parent_dev; 41 #endif 42 struct pci_dev *pdev; 43 struct pci_bus *pbus; 44 45 /* Effective RID (device RID for a device PE and base bus 46 * RID with devfn 0 for a bus PE) 47 */ 48 unsigned int rid; 49 50 /* PE number */ 51 unsigned int pe_number; 52 53 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 54 struct iommu_table_group table_group; 55 56 /* 64-bit TCE bypass region */ 57 bool tce_bypass_enabled; 58 uint64_t tce_bypass_base; 59 60 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 61 * and -1 if not supported. (It's actually identical to the 62 * PE number) 63 */ 64 int mve_number; 65 66 /* PEs in compound case */ 67 struct pnv_ioda_pe *master; 68 struct list_head slaves; 69 70 /* Link in list of PE#s */ 71 struct list_head list; 72 }; 73 74 #define PNV_PHB_FLAG_EEH (1 << 0) 75 76 struct pnv_phb { 77 struct pci_controller *hose; 78 enum pnv_phb_type type; 79 enum pnv_phb_model model; 80 u64 hub_id; 81 u64 opal_id; 82 int flags; 83 void __iomem *regs; 84 int initialized; 85 spinlock_t lock; 86 87 #ifdef CONFIG_DEBUG_FS 88 int has_dbgfs; 89 struct dentry *dbgfs; 90 #endif 91 92 #ifdef CONFIG_PCI_MSI 93 unsigned int msi_base; 94 unsigned int msi32_support; 95 struct msi_bitmap msi_bmp; 96 #endif 97 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 98 unsigned int hwirq, unsigned int virq, 99 unsigned int is_64, struct msi_msg *msg); 100 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 101 void (*fixup_phb)(struct pci_controller *hose); 102 int (*init_m64)(struct pnv_phb *phb); 103 void (*reserve_m64_pe)(struct pci_bus *bus, 104 unsigned long *pe_bitmap, bool all); 105 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all); 106 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 107 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 108 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 109 110 struct { 111 /* Global bridge info */ 112 unsigned int total_pe_num; 113 unsigned int reserved_pe_idx; 114 unsigned int root_pe_idx; 115 bool root_pe_populated; 116 117 /* 32-bit MMIO window */ 118 unsigned int m32_size; 119 unsigned int m32_segsize; 120 unsigned int m32_pci_base; 121 122 /* 64-bit MMIO window */ 123 unsigned int m64_bar_idx; 124 unsigned long m64_size; 125 unsigned long m64_segsize; 126 unsigned long m64_base; 127 unsigned long m64_bar_alloc; 128 129 /* IO ports */ 130 unsigned int io_size; 131 unsigned int io_segsize; 132 unsigned int io_pci_base; 133 134 /* PE allocation */ 135 struct mutex pe_alloc_mutex; 136 unsigned long *pe_alloc; 137 struct pnv_ioda_pe *pe_array; 138 139 /* M32 & IO segment maps */ 140 unsigned int *m64_segmap; 141 unsigned int *m32_segmap; 142 unsigned int *io_segmap; 143 144 /* DMA32 segment maps - IODA1 only */ 145 unsigned int dma32_count; 146 unsigned int *dma32_segmap; 147 148 /* IRQ chip */ 149 int irq_chip_init; 150 struct irq_chip irq_chip; 151 152 /* Sorted list of used PE's based 153 * on the sequence of creation 154 */ 155 struct list_head pe_list; 156 struct mutex pe_list_mutex; 157 158 /* Reverse map of PEs, indexed by {bus, devfn} */ 159 unsigned int pe_rmap[0x10000]; 160 161 /* TCE cache invalidate registers (physical and 162 * remapped) 163 */ 164 phys_addr_t tce_inval_reg_phys; 165 __be64 __iomem *tce_inval_reg; 166 } ioda; 167 168 /* PHB and hub status structure */ 169 union { 170 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 171 struct OpalIoP7IOCPhbErrorData p7ioc; 172 struct OpalIoPhb3ErrorData phb3; 173 struct OpalIoP7IOCErrorData hub_diag; 174 } diag; 175 176 }; 177 178 extern struct pci_ops pnv_pci_ops; 179 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 180 unsigned long uaddr, enum dma_data_direction direction, 181 struct dma_attrs *attrs); 182 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 183 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 184 unsigned long *hpa, enum dma_data_direction *direction); 185 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 186 187 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 188 unsigned char *log_buff); 189 int pnv_pci_cfg_read(struct pci_dn *pdn, 190 int where, int size, u32 *val); 191 int pnv_pci_cfg_write(struct pci_dn *pdn, 192 int where, int size, u32 val); 193 extern struct iommu_table *pnv_pci_table_alloc(int nid); 194 195 extern long pnv_pci_link_table_and_group(int node, int num, 196 struct iommu_table *tbl, 197 struct iommu_table_group *table_group); 198 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 199 struct iommu_table_group *table_group); 200 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 201 void *tce_mem, u64 tce_size, 202 u64 dma_offset, unsigned page_shift); 203 extern void pnv_pci_init_ioda_hub(struct device_node *np); 204 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 205 extern void pnv_pci_init_npu_phb(struct device_node *np); 206 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 207 __be64 *startp, __be64 *endp, bool rm); 208 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 209 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 210 211 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 212 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 213 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 214 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 215 216 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 217 const char *fmt, ...); 218 #define pe_err(pe, fmt, ...) \ 219 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 220 #define pe_warn(pe, fmt, ...) \ 221 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 222 #define pe_info(pe, fmt, ...) \ 223 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 224 225 /* Nvlink functions */ 226 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 227 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 228 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 229 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, 230 struct iommu_table *tbl); 231 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num); 232 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe); 233 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe); 234 235 #endif /* __POWERNV_PCI_H */ 236