1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 #include <linux/iommu.h> 5 #include <asm/iommu.h> 6 #include <asm/msi_bitmap.h> 7 8 struct pci_dn; 9 10 enum pnv_phb_type { 11 PNV_PHB_IODA1 = 0, 12 PNV_PHB_IODA2 = 1, 13 PNV_PHB_NPU = 2, 14 }; 15 16 /* Precise PHB model for error management */ 17 enum pnv_phb_model { 18 PNV_PHB_MODEL_UNKNOWN, 19 PNV_PHB_MODEL_P7IOC, 20 PNV_PHB_MODEL_PHB3, 21 PNV_PHB_MODEL_NPU, 22 }; 23 24 #define PNV_PCI_DIAG_BUF_SIZE 8192 25 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 26 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 27 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 28 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 29 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 30 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 31 32 /* Data associated with a PE, including IOMMU tracking etc.. */ 33 struct pnv_phb; 34 struct pnv_ioda_pe { 35 unsigned long flags; 36 struct pnv_phb *phb; 37 int device_count; 38 39 /* A PE can be associated with a single device or an 40 * entire bus (& children). In the former case, pdev 41 * is populated, in the later case, pbus is. 42 */ 43 #ifdef CONFIG_PCI_IOV 44 struct pci_dev *parent_dev; 45 #endif 46 struct pci_dev *pdev; 47 struct pci_bus *pbus; 48 49 /* Effective RID (device RID for a device PE and base bus 50 * RID with devfn 0 for a bus PE) 51 */ 52 unsigned int rid; 53 54 /* PE number */ 55 unsigned int pe_number; 56 57 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 58 struct iommu_table_group table_group; 59 60 /* 64-bit TCE bypass region */ 61 bool tce_bypass_enabled; 62 uint64_t tce_bypass_base; 63 64 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 65 * and -1 if not supported. (It's actually identical to the 66 * PE number) 67 */ 68 int mve_number; 69 70 /* PEs in compound case */ 71 struct pnv_ioda_pe *master; 72 struct list_head slaves; 73 74 /* Link in list of PE#s */ 75 struct list_head list; 76 }; 77 78 #define PNV_PHB_FLAG_EEH (1 << 0) 79 #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */ 80 81 struct pnv_phb { 82 struct pci_controller *hose; 83 enum pnv_phb_type type; 84 enum pnv_phb_model model; 85 u64 hub_id; 86 u64 opal_id; 87 int flags; 88 void __iomem *regs; 89 u64 regs_phys; 90 int initialized; 91 spinlock_t lock; 92 93 #ifdef CONFIG_DEBUG_FS 94 int has_dbgfs; 95 struct dentry *dbgfs; 96 #endif 97 98 #ifdef CONFIG_PCI_MSI 99 unsigned int msi_base; 100 unsigned int msi32_support; 101 struct msi_bitmap msi_bmp; 102 #endif 103 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 104 unsigned int hwirq, unsigned int virq, 105 unsigned int is_64, struct msi_msg *msg); 106 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 107 void (*fixup_phb)(struct pci_controller *hose); 108 int (*init_m64)(struct pnv_phb *phb); 109 void (*reserve_m64_pe)(struct pci_bus *bus, 110 unsigned long *pe_bitmap, bool all); 111 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all); 112 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 113 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 114 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 115 116 struct { 117 /* Global bridge info */ 118 unsigned int total_pe_num; 119 unsigned int reserved_pe_idx; 120 unsigned int root_pe_idx; 121 bool root_pe_populated; 122 123 /* 32-bit MMIO window */ 124 unsigned int m32_size; 125 unsigned int m32_segsize; 126 unsigned int m32_pci_base; 127 128 /* 64-bit MMIO window */ 129 unsigned int m64_bar_idx; 130 unsigned long m64_size; 131 unsigned long m64_segsize; 132 unsigned long m64_base; 133 unsigned long m64_bar_alloc; 134 135 /* IO ports */ 136 unsigned int io_size; 137 unsigned int io_segsize; 138 unsigned int io_pci_base; 139 140 /* PE allocation */ 141 struct mutex pe_alloc_mutex; 142 unsigned long *pe_alloc; 143 struct pnv_ioda_pe *pe_array; 144 145 /* M32 & IO segment maps */ 146 unsigned int *m64_segmap; 147 unsigned int *m32_segmap; 148 unsigned int *io_segmap; 149 150 /* DMA32 segment maps - IODA1 only */ 151 unsigned int dma32_count; 152 unsigned int *dma32_segmap; 153 154 /* IRQ chip */ 155 int irq_chip_init; 156 struct irq_chip irq_chip; 157 158 /* Sorted list of used PE's based 159 * on the sequence of creation 160 */ 161 struct list_head pe_list; 162 struct mutex pe_list_mutex; 163 164 /* Reverse map of PEs, indexed by {bus, devfn} */ 165 unsigned int pe_rmap[0x10000]; 166 } ioda; 167 168 /* PHB and hub status structure */ 169 union { 170 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 171 struct OpalIoP7IOCPhbErrorData p7ioc; 172 struct OpalIoPhb3ErrorData phb3; 173 struct OpalIoP7IOCErrorData hub_diag; 174 } diag; 175 176 #ifdef CONFIG_CXL_BASE 177 struct cxl_afu *cxl_afu; 178 #endif 179 }; 180 181 extern struct pci_ops pnv_pci_ops; 182 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 183 unsigned long uaddr, enum dma_data_direction direction, 184 unsigned long attrs); 185 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 186 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 187 unsigned long *hpa, enum dma_data_direction *direction); 188 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 189 190 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 191 unsigned char *log_buff); 192 int pnv_pci_cfg_read(struct pci_dn *pdn, 193 int where, int size, u32 *val); 194 int pnv_pci_cfg_write(struct pci_dn *pdn, 195 int where, int size, u32 val); 196 extern struct iommu_table *pnv_pci_table_alloc(int nid); 197 198 extern long pnv_pci_link_table_and_group(int node, int num, 199 struct iommu_table *tbl, 200 struct iommu_table_group *table_group); 201 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 202 struct iommu_table_group *table_group); 203 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 204 void *tce_mem, u64 tce_size, 205 u64 dma_offset, unsigned page_shift); 206 extern void pnv_pci_init_ioda_hub(struct device_node *np); 207 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 208 extern void pnv_pci_init_npu_phb(struct device_node *np); 209 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 210 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 211 212 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 213 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 214 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 215 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 216 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 217 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 218 extern bool pnv_pci_enable_device_hook(struct pci_dev *dev); 219 220 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 221 const char *fmt, ...); 222 #define pe_err(pe, fmt, ...) \ 223 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 224 #define pe_warn(pe, fmt, ...) \ 225 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 226 #define pe_info(pe, fmt, ...) \ 227 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 228 229 /* Nvlink functions */ 230 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 231 extern void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 232 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 233 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, 234 struct iommu_table *tbl); 235 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num); 236 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe); 237 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe); 238 239 240 /* cxl functions */ 241 extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev); 242 extern void pnv_cxl_disable_device(struct pci_dev *dev); 243 extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 244 extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev); 245 246 247 /* phb ops (cxl switches these when enabling the kernel api on the phb) */ 248 extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops; 249 250 #endif /* __POWERNV_PCI_H */ 251