1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/pci.h> 14 #include <linux/delay.h> 15 #include <linux/string.h> 16 #include <linux/init.h> 17 #include <linux/irq.h> 18 #include <linux/io.h> 19 #include <linux/msi.h> 20 #include <linux/iommu.h> 21 22 #include <asm/sections.h> 23 #include <asm/io.h> 24 #include <asm/prom.h> 25 #include <asm/pci-bridge.h> 26 #include <asm/machdep.h> 27 #include <asm/msi_bitmap.h> 28 #include <asm/ppc-pci.h> 29 #include <asm/opal.h> 30 #include <asm/iommu.h> 31 #include <asm/tce.h> 32 #include <asm/firmware.h> 33 #include <asm/eeh_event.h> 34 #include <asm/eeh.h> 35 36 #include "powernv.h" 37 #include "pci.h" 38 39 /* Delay in usec */ 40 #define PCI_RESET_DELAY_US 3000000 41 42 #define cfg_dbg(fmt...) do { } while(0) 43 //#define cfg_dbg(fmt...) printk(fmt) 44 45 #ifdef CONFIG_PCI_MSI 46 int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 47 { 48 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 49 struct pnv_phb *phb = hose->private_data; 50 struct msi_desc *entry; 51 struct msi_msg msg; 52 int hwirq; 53 unsigned int virq; 54 int rc; 55 56 if (WARN_ON(!phb) || !phb->msi_bmp.bitmap) 57 return -ENODEV; 58 59 if (pdev->no_64bit_msi && !phb->msi32_support) 60 return -ENODEV; 61 62 for_each_pci_msi_entry(entry, pdev) { 63 if (!entry->msi_attrib.is_64 && !phb->msi32_support) { 64 pr_warn("%s: Supports only 64-bit MSIs\n", 65 pci_name(pdev)); 66 return -ENXIO; 67 } 68 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); 69 if (hwirq < 0) { 70 pr_warn("%s: Failed to find a free MSI\n", 71 pci_name(pdev)); 72 return -ENOSPC; 73 } 74 virq = irq_create_mapping(NULL, phb->msi_base + hwirq); 75 if (virq == NO_IRQ) { 76 pr_warn("%s: Failed to map MSI to linux irq\n", 77 pci_name(pdev)); 78 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 79 return -ENOMEM; 80 } 81 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, 82 virq, entry->msi_attrib.is_64, &msg); 83 if (rc) { 84 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); 85 irq_dispose_mapping(virq); 86 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 87 return rc; 88 } 89 irq_set_msi_desc(virq, entry); 90 pci_write_msi_msg(virq, &msg); 91 } 92 return 0; 93 } 94 95 void pnv_teardown_msi_irqs(struct pci_dev *pdev) 96 { 97 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 98 struct pnv_phb *phb = hose->private_data; 99 struct msi_desc *entry; 100 irq_hw_number_t hwirq; 101 102 if (WARN_ON(!phb)) 103 return; 104 105 for_each_pci_msi_entry(entry, pdev) { 106 if (entry->irq == NO_IRQ) 107 continue; 108 hwirq = virq_to_hw(entry->irq); 109 irq_set_msi_desc(entry->irq, NULL); 110 irq_dispose_mapping(entry->irq); 111 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1); 112 } 113 } 114 #endif /* CONFIG_PCI_MSI */ 115 116 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, 117 struct OpalIoPhbErrorCommon *common) 118 { 119 struct OpalIoP7IOCPhbErrorData *data; 120 int i; 121 122 data = (struct OpalIoP7IOCPhbErrorData *)common; 123 pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n", 124 hose->global_number, be32_to_cpu(common->version)); 125 126 if (data->brdgCtl) 127 pr_info("brdgCtl: %08x\n", 128 be32_to_cpu(data->brdgCtl)); 129 if (data->portStatusReg || data->rootCmplxStatus || 130 data->busAgentStatus) 131 pr_info("UtlSts: %08x %08x %08x\n", 132 be32_to_cpu(data->portStatusReg), 133 be32_to_cpu(data->rootCmplxStatus), 134 be32_to_cpu(data->busAgentStatus)); 135 if (data->deviceStatus || data->slotStatus || 136 data->linkStatus || data->devCmdStatus || 137 data->devSecStatus) 138 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 139 be32_to_cpu(data->deviceStatus), 140 be32_to_cpu(data->slotStatus), 141 be32_to_cpu(data->linkStatus), 142 be32_to_cpu(data->devCmdStatus), 143 be32_to_cpu(data->devSecStatus)); 144 if (data->rootErrorStatus || data->uncorrErrorStatus || 145 data->corrErrorStatus) 146 pr_info("RootErrSts: %08x %08x %08x\n", 147 be32_to_cpu(data->rootErrorStatus), 148 be32_to_cpu(data->uncorrErrorStatus), 149 be32_to_cpu(data->corrErrorStatus)); 150 if (data->tlpHdr1 || data->tlpHdr2 || 151 data->tlpHdr3 || data->tlpHdr4) 152 pr_info("RootErrLog: %08x %08x %08x %08x\n", 153 be32_to_cpu(data->tlpHdr1), 154 be32_to_cpu(data->tlpHdr2), 155 be32_to_cpu(data->tlpHdr3), 156 be32_to_cpu(data->tlpHdr4)); 157 if (data->sourceId || data->errorClass || 158 data->correlator) 159 pr_info("RootErrLog1: %08x %016llx %016llx\n", 160 be32_to_cpu(data->sourceId), 161 be64_to_cpu(data->errorClass), 162 be64_to_cpu(data->correlator)); 163 if (data->p7iocPlssr || data->p7iocCsr) 164 pr_info("PhbSts: %016llx %016llx\n", 165 be64_to_cpu(data->p7iocPlssr), 166 be64_to_cpu(data->p7iocCsr)); 167 if (data->lemFir) 168 pr_info("Lem: %016llx %016llx %016llx\n", 169 be64_to_cpu(data->lemFir), 170 be64_to_cpu(data->lemErrorMask), 171 be64_to_cpu(data->lemWOF)); 172 if (data->phbErrorStatus) 173 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 174 be64_to_cpu(data->phbErrorStatus), 175 be64_to_cpu(data->phbFirstErrorStatus), 176 be64_to_cpu(data->phbErrorLog0), 177 be64_to_cpu(data->phbErrorLog1)); 178 if (data->mmioErrorStatus) 179 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 180 be64_to_cpu(data->mmioErrorStatus), 181 be64_to_cpu(data->mmioFirstErrorStatus), 182 be64_to_cpu(data->mmioErrorLog0), 183 be64_to_cpu(data->mmioErrorLog1)); 184 if (data->dma0ErrorStatus) 185 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 186 be64_to_cpu(data->dma0ErrorStatus), 187 be64_to_cpu(data->dma0FirstErrorStatus), 188 be64_to_cpu(data->dma0ErrorLog0), 189 be64_to_cpu(data->dma0ErrorLog1)); 190 if (data->dma1ErrorStatus) 191 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 192 be64_to_cpu(data->dma1ErrorStatus), 193 be64_to_cpu(data->dma1FirstErrorStatus), 194 be64_to_cpu(data->dma1ErrorLog0), 195 be64_to_cpu(data->dma1ErrorLog1)); 196 197 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { 198 if ((data->pestA[i] >> 63) == 0 && 199 (data->pestB[i] >> 63) == 0) 200 continue; 201 202 pr_info("PE[%3d] A/B: %016llx %016llx\n", 203 i, be64_to_cpu(data->pestA[i]), 204 be64_to_cpu(data->pestB[i])); 205 } 206 } 207 208 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, 209 struct OpalIoPhbErrorCommon *common) 210 { 211 struct OpalIoPhb3ErrorData *data; 212 int i; 213 214 data = (struct OpalIoPhb3ErrorData*)common; 215 pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n", 216 hose->global_number, be32_to_cpu(common->version)); 217 if (data->brdgCtl) 218 pr_info("brdgCtl: %08x\n", 219 be32_to_cpu(data->brdgCtl)); 220 if (data->portStatusReg || data->rootCmplxStatus || 221 data->busAgentStatus) 222 pr_info("UtlSts: %08x %08x %08x\n", 223 be32_to_cpu(data->portStatusReg), 224 be32_to_cpu(data->rootCmplxStatus), 225 be32_to_cpu(data->busAgentStatus)); 226 if (data->deviceStatus || data->slotStatus || 227 data->linkStatus || data->devCmdStatus || 228 data->devSecStatus) 229 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 230 be32_to_cpu(data->deviceStatus), 231 be32_to_cpu(data->slotStatus), 232 be32_to_cpu(data->linkStatus), 233 be32_to_cpu(data->devCmdStatus), 234 be32_to_cpu(data->devSecStatus)); 235 if (data->rootErrorStatus || data->uncorrErrorStatus || 236 data->corrErrorStatus) 237 pr_info("RootErrSts: %08x %08x %08x\n", 238 be32_to_cpu(data->rootErrorStatus), 239 be32_to_cpu(data->uncorrErrorStatus), 240 be32_to_cpu(data->corrErrorStatus)); 241 if (data->tlpHdr1 || data->tlpHdr2 || 242 data->tlpHdr3 || data->tlpHdr4) 243 pr_info("RootErrLog: %08x %08x %08x %08x\n", 244 be32_to_cpu(data->tlpHdr1), 245 be32_to_cpu(data->tlpHdr2), 246 be32_to_cpu(data->tlpHdr3), 247 be32_to_cpu(data->tlpHdr4)); 248 if (data->sourceId || data->errorClass || 249 data->correlator) 250 pr_info("RootErrLog1: %08x %016llx %016llx\n", 251 be32_to_cpu(data->sourceId), 252 be64_to_cpu(data->errorClass), 253 be64_to_cpu(data->correlator)); 254 if (data->nFir) 255 pr_info("nFir: %016llx %016llx %016llx\n", 256 be64_to_cpu(data->nFir), 257 be64_to_cpu(data->nFirMask), 258 be64_to_cpu(data->nFirWOF)); 259 if (data->phbPlssr || data->phbCsr) 260 pr_info("PhbSts: %016llx %016llx\n", 261 be64_to_cpu(data->phbPlssr), 262 be64_to_cpu(data->phbCsr)); 263 if (data->lemFir) 264 pr_info("Lem: %016llx %016llx %016llx\n", 265 be64_to_cpu(data->lemFir), 266 be64_to_cpu(data->lemErrorMask), 267 be64_to_cpu(data->lemWOF)); 268 if (data->phbErrorStatus) 269 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 270 be64_to_cpu(data->phbErrorStatus), 271 be64_to_cpu(data->phbFirstErrorStatus), 272 be64_to_cpu(data->phbErrorLog0), 273 be64_to_cpu(data->phbErrorLog1)); 274 if (data->mmioErrorStatus) 275 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 276 be64_to_cpu(data->mmioErrorStatus), 277 be64_to_cpu(data->mmioFirstErrorStatus), 278 be64_to_cpu(data->mmioErrorLog0), 279 be64_to_cpu(data->mmioErrorLog1)); 280 if (data->dma0ErrorStatus) 281 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 282 be64_to_cpu(data->dma0ErrorStatus), 283 be64_to_cpu(data->dma0FirstErrorStatus), 284 be64_to_cpu(data->dma0ErrorLog0), 285 be64_to_cpu(data->dma0ErrorLog1)); 286 if (data->dma1ErrorStatus) 287 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 288 be64_to_cpu(data->dma1ErrorStatus), 289 be64_to_cpu(data->dma1FirstErrorStatus), 290 be64_to_cpu(data->dma1ErrorLog0), 291 be64_to_cpu(data->dma1ErrorLog1)); 292 293 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { 294 if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 && 295 (be64_to_cpu(data->pestB[i]) >> 63) == 0) 296 continue; 297 298 pr_info("PE[%3d] A/B: %016llx %016llx\n", 299 i, be64_to_cpu(data->pestA[i]), 300 be64_to_cpu(data->pestB[i])); 301 } 302 } 303 304 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 305 unsigned char *log_buff) 306 { 307 struct OpalIoPhbErrorCommon *common; 308 309 if (!hose || !log_buff) 310 return; 311 312 common = (struct OpalIoPhbErrorCommon *)log_buff; 313 switch (be32_to_cpu(common->ioType)) { 314 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: 315 pnv_pci_dump_p7ioc_diag_data(hose, common); 316 break; 317 case OPAL_PHB_ERROR_DATA_TYPE_PHB3: 318 pnv_pci_dump_phb3_diag_data(hose, common); 319 break; 320 default: 321 pr_warn("%s: Unrecognized ioType %d\n", 322 __func__, be32_to_cpu(common->ioType)); 323 } 324 } 325 326 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) 327 { 328 unsigned long flags, rc; 329 int has_diag, ret = 0; 330 331 spin_lock_irqsave(&phb->lock, flags); 332 333 /* Fetch PHB diag-data */ 334 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, 335 PNV_PCI_DIAG_BUF_SIZE); 336 has_diag = (rc == OPAL_SUCCESS); 337 338 /* If PHB supports compound PE, to handle it */ 339 if (phb->unfreeze_pe) { 340 ret = phb->unfreeze_pe(phb, 341 pe_no, 342 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 343 } else { 344 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 345 pe_no, 346 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 347 if (rc) { 348 pr_warn("%s: Failure %ld clearing frozen " 349 "PHB#%x-PE#%x\n", 350 __func__, rc, phb->hose->global_number, 351 pe_no); 352 ret = -EIO; 353 } 354 } 355 356 /* 357 * For now, let's only display the diag buffer when we fail to clear 358 * the EEH status. We'll do more sensible things later when we have 359 * proper EEH support. We need to make sure we don't pollute ourselves 360 * with the normal errors generated when probing empty slots 361 */ 362 if (has_diag && ret) 363 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); 364 365 spin_unlock_irqrestore(&phb->lock, flags); 366 } 367 368 static void pnv_pci_config_check_eeh(struct pci_dn *pdn) 369 { 370 struct pnv_phb *phb = pdn->phb->private_data; 371 u8 fstate; 372 __be16 pcierr; 373 int pe_no; 374 s64 rc; 375 376 /* 377 * Get the PE#. During the PCI probe stage, we might not 378 * setup that yet. So all ER errors should be mapped to 379 * reserved PE. 380 */ 381 pe_no = pdn->pe_number; 382 if (pe_no == IODA_INVALID_PE) { 383 pe_no = phb->ioda.reserved_pe; 384 } 385 386 /* 387 * Fetch frozen state. If the PHB support compound PE, 388 * we need handle that case. 389 */ 390 if (phb->get_pe_state) { 391 fstate = phb->get_pe_state(phb, pe_no); 392 } else { 393 rc = opal_pci_eeh_freeze_status(phb->opal_id, 394 pe_no, 395 &fstate, 396 &pcierr, 397 NULL); 398 if (rc) { 399 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n", 400 __func__, rc, phb->hose->global_number, pe_no); 401 return; 402 } 403 } 404 405 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", 406 (pdn->busno << 8) | (pdn->devfn), pe_no, fstate); 407 408 /* Clear the frozen state if applicable */ 409 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE || 410 fstate == OPAL_EEH_STOPPED_DMA_FREEZE || 411 fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) { 412 /* 413 * If PHB supports compound PE, freeze it for 414 * consistency. 415 */ 416 if (phb->freeze_pe) 417 phb->freeze_pe(phb, pe_no); 418 419 pnv_pci_handle_eeh_config(phb, pe_no); 420 } 421 } 422 423 int pnv_pci_cfg_read(struct pci_dn *pdn, 424 int where, int size, u32 *val) 425 { 426 struct pnv_phb *phb = pdn->phb->private_data; 427 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 428 s64 rc; 429 430 switch (size) { 431 case 1: { 432 u8 v8; 433 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); 434 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; 435 break; 436 } 437 case 2: { 438 __be16 v16; 439 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, 440 &v16); 441 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; 442 break; 443 } 444 case 4: { 445 __be32 v32; 446 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); 447 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; 448 break; 449 } 450 default: 451 return PCIBIOS_FUNC_NOT_SUPPORTED; 452 } 453 454 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 455 __func__, pdn->busno, pdn->devfn, where, size, *val); 456 return PCIBIOS_SUCCESSFUL; 457 } 458 459 int pnv_pci_cfg_write(struct pci_dn *pdn, 460 int where, int size, u32 val) 461 { 462 struct pnv_phb *phb = pdn->phb->private_data; 463 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 464 465 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 466 pdn->busno, pdn->devfn, where, size, val); 467 switch (size) { 468 case 1: 469 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); 470 break; 471 case 2: 472 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); 473 break; 474 case 4: 475 opal_pci_config_write_word(phb->opal_id, bdfn, where, val); 476 break; 477 default: 478 return PCIBIOS_FUNC_NOT_SUPPORTED; 479 } 480 481 return PCIBIOS_SUCCESSFUL; 482 } 483 484 #if CONFIG_EEH 485 static bool pnv_pci_cfg_check(struct pci_dn *pdn) 486 { 487 struct eeh_dev *edev = NULL; 488 struct pnv_phb *phb = pdn->phb->private_data; 489 490 /* EEH not enabled ? */ 491 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 492 return true; 493 494 /* PE reset or device removed ? */ 495 edev = pdn->edev; 496 if (edev) { 497 if (edev->pe && 498 (edev->pe->state & EEH_PE_CFG_BLOCKED)) 499 return false; 500 501 if (edev->mode & EEH_DEV_REMOVED) 502 return false; 503 } 504 505 return true; 506 } 507 #else 508 static inline pnv_pci_cfg_check(struct pci_dn *pdn) 509 { 510 return true; 511 } 512 #endif /* CONFIG_EEH */ 513 514 static int pnv_pci_read_config(struct pci_bus *bus, 515 unsigned int devfn, 516 int where, int size, u32 *val) 517 { 518 struct pci_dn *pdn; 519 struct pnv_phb *phb; 520 int ret; 521 522 *val = 0xFFFFFFFF; 523 pdn = pci_get_pdn_by_devfn(bus, devfn); 524 if (!pdn) 525 return PCIBIOS_DEVICE_NOT_FOUND; 526 527 if (!pnv_pci_cfg_check(pdn)) 528 return PCIBIOS_DEVICE_NOT_FOUND; 529 530 ret = pnv_pci_cfg_read(pdn, where, size, val); 531 phb = pdn->phb->private_data; 532 if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) { 533 if (*val == EEH_IO_ERROR_VALUE(size) && 534 eeh_dev_check_failure(pdn->edev)) 535 return PCIBIOS_DEVICE_NOT_FOUND; 536 } else { 537 pnv_pci_config_check_eeh(pdn); 538 } 539 540 return ret; 541 } 542 543 static int pnv_pci_write_config(struct pci_bus *bus, 544 unsigned int devfn, 545 int where, int size, u32 val) 546 { 547 struct pci_dn *pdn; 548 struct pnv_phb *phb; 549 int ret; 550 551 pdn = pci_get_pdn_by_devfn(bus, devfn); 552 if (!pdn) 553 return PCIBIOS_DEVICE_NOT_FOUND; 554 555 if (!pnv_pci_cfg_check(pdn)) 556 return PCIBIOS_DEVICE_NOT_FOUND; 557 558 ret = pnv_pci_cfg_write(pdn, where, size, val); 559 phb = pdn->phb->private_data; 560 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 561 pnv_pci_config_check_eeh(pdn); 562 563 return ret; 564 } 565 566 struct pci_ops pnv_pci_ops = { 567 .read = pnv_pci_read_config, 568 .write = pnv_pci_write_config, 569 }; 570 571 static __be64 *pnv_tce(struct iommu_table *tbl, long idx) 572 { 573 __be64 *tmp = ((__be64 *)tbl->it_base); 574 int level = tbl->it_indirect_levels; 575 const long shift = ilog2(tbl->it_level_size); 576 unsigned long mask = (tbl->it_level_size - 1) << (level * shift); 577 578 while (level) { 579 int n = (idx & mask) >> (level * shift); 580 unsigned long tce = be64_to_cpu(tmp[n]); 581 582 tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE)); 583 idx &= ~mask; 584 mask >>= shift; 585 --level; 586 } 587 588 return tmp + idx; 589 } 590 591 int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 592 unsigned long uaddr, enum dma_data_direction direction, 593 struct dma_attrs *attrs) 594 { 595 u64 proto_tce = iommu_direction_to_tce_perm(direction); 596 u64 rpn = __pa(uaddr) >> tbl->it_page_shift; 597 long i; 598 599 if (proto_tce & TCE_PCI_WRITE) 600 proto_tce |= TCE_PCI_READ; 601 602 for (i = 0; i < npages; i++) { 603 unsigned long newtce = proto_tce | 604 ((rpn + i) << tbl->it_page_shift); 605 unsigned long idx = index - tbl->it_offset + i; 606 607 *(pnv_tce(tbl, idx)) = cpu_to_be64(newtce); 608 } 609 610 return 0; 611 } 612 613 #ifdef CONFIG_IOMMU_API 614 int pnv_tce_xchg(struct iommu_table *tbl, long index, 615 unsigned long *hpa, enum dma_data_direction *direction) 616 { 617 u64 proto_tce = iommu_direction_to_tce_perm(*direction); 618 unsigned long newtce = *hpa | proto_tce, oldtce; 619 unsigned long idx = index - tbl->it_offset; 620 621 BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl)); 622 623 if (newtce & TCE_PCI_WRITE) 624 newtce |= TCE_PCI_READ; 625 626 oldtce = xchg(pnv_tce(tbl, idx), cpu_to_be64(newtce)); 627 *hpa = be64_to_cpu(oldtce) & ~(TCE_PCI_READ | TCE_PCI_WRITE); 628 *direction = iommu_tce_direction(oldtce); 629 630 return 0; 631 } 632 #endif 633 634 void pnv_tce_free(struct iommu_table *tbl, long index, long npages) 635 { 636 long i; 637 638 for (i = 0; i < npages; i++) { 639 unsigned long idx = index - tbl->it_offset + i; 640 641 *(pnv_tce(tbl, idx)) = cpu_to_be64(0); 642 } 643 } 644 645 unsigned long pnv_tce_get(struct iommu_table *tbl, long index) 646 { 647 return *(pnv_tce(tbl, index - tbl->it_offset)); 648 } 649 650 struct iommu_table *pnv_pci_table_alloc(int nid) 651 { 652 struct iommu_table *tbl; 653 654 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, nid); 655 INIT_LIST_HEAD_RCU(&tbl->it_group_list); 656 657 return tbl; 658 } 659 660 long pnv_pci_link_table_and_group(int node, int num, 661 struct iommu_table *tbl, 662 struct iommu_table_group *table_group) 663 { 664 struct iommu_table_group_link *tgl = NULL; 665 666 if (WARN_ON(!tbl || !table_group)) 667 return -EINVAL; 668 669 tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL, 670 node); 671 if (!tgl) 672 return -ENOMEM; 673 674 tgl->table_group = table_group; 675 list_add_rcu(&tgl->next, &tbl->it_group_list); 676 677 table_group->tables[num] = tbl; 678 679 return 0; 680 } 681 682 static void pnv_iommu_table_group_link_free(struct rcu_head *head) 683 { 684 struct iommu_table_group_link *tgl = container_of(head, 685 struct iommu_table_group_link, rcu); 686 687 kfree(tgl); 688 } 689 690 void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 691 struct iommu_table_group *table_group) 692 { 693 long i; 694 bool found; 695 struct iommu_table_group_link *tgl; 696 697 if (!tbl || !table_group) 698 return; 699 700 /* Remove link to a group from table's list of attached groups */ 701 found = false; 702 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 703 if (tgl->table_group == table_group) { 704 list_del_rcu(&tgl->next); 705 call_rcu(&tgl->rcu, pnv_iommu_table_group_link_free); 706 found = true; 707 break; 708 } 709 } 710 if (WARN_ON(!found)) 711 return; 712 713 /* Clean a pointer to iommu_table in iommu_table_group::tables[] */ 714 found = false; 715 for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { 716 if (table_group->tables[i] == tbl) { 717 table_group->tables[i] = NULL; 718 found = true; 719 break; 720 } 721 } 722 WARN_ON(!found); 723 } 724 725 void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 726 void *tce_mem, u64 tce_size, 727 u64 dma_offset, unsigned page_shift) 728 { 729 tbl->it_blocksize = 16; 730 tbl->it_base = (unsigned long)tce_mem; 731 tbl->it_page_shift = page_shift; 732 tbl->it_offset = dma_offset >> tbl->it_page_shift; 733 tbl->it_index = 0; 734 tbl->it_size = tce_size >> 3; 735 tbl->it_busno = 0; 736 tbl->it_type = TCE_PCI; 737 } 738 739 void pnv_pci_dma_dev_setup(struct pci_dev *pdev) 740 { 741 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 742 struct pnv_phb *phb = hose->private_data; 743 #ifdef CONFIG_PCI_IOV 744 struct pnv_ioda_pe *pe; 745 struct pci_dn *pdn; 746 747 /* Fix the VF pdn PE number */ 748 if (pdev->is_virtfn) { 749 pdn = pci_get_pdn(pdev); 750 WARN_ON(pdn->pe_number != IODA_INVALID_PE); 751 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 752 if (pe->rid == ((pdev->bus->number << 8) | 753 (pdev->devfn & 0xff))) { 754 pdn->pe_number = pe->pe_number; 755 pe->pdev = pdev; 756 break; 757 } 758 } 759 } 760 #endif /* CONFIG_PCI_IOV */ 761 762 if (phb && phb->dma_dev_setup) 763 phb->dma_dev_setup(phb, pdev); 764 } 765 766 void pnv_pci_dma_bus_setup(struct pci_bus *bus) 767 { 768 struct pci_controller *hose = bus->sysdata; 769 struct pnv_phb *phb = hose->private_data; 770 struct pnv_ioda_pe *pe; 771 772 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 773 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 774 continue; 775 776 if (!pe->pbus) 777 continue; 778 779 if (bus->number == ((pe->rid >> 8) & 0xFF)) { 780 pe->pbus = bus; 781 break; 782 } 783 } 784 } 785 786 void pnv_pci_shutdown(void) 787 { 788 struct pci_controller *hose; 789 790 list_for_each_entry(hose, &hose_list, list_node) 791 if (hose->controller_ops.shutdown) 792 hose->controller_ops.shutdown(hose); 793 } 794 795 /* Fixup wrong class code in p7ioc and p8 root complex */ 796 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) 797 { 798 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 799 } 800 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); 801 802 void __init pnv_pci_init(void) 803 { 804 struct device_node *np; 805 806 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); 807 808 /* If we don't have OPAL, eg. in sim, just skip PCI probe */ 809 if (!firmware_has_feature(FW_FEATURE_OPAL)) 810 return; 811 812 /* Look for IODA IO-Hubs. */ 813 for_each_compatible_node(np, NULL, "ibm,ioda-hub") { 814 pnv_pci_init_ioda_hub(np); 815 } 816 817 /* Look for ioda2 built-in PHB3's */ 818 for_each_compatible_node(np, NULL, "ibm,ioda2-phb") 819 pnv_pci_init_ioda2_phb(np); 820 821 /* Look for NPU PHBs */ 822 for_each_compatible_node(np, NULL, "ibm,ioda2-npu-phb") 823 pnv_pci_init_npu_phb(np); 824 825 /* Setup the linkage between OF nodes and PHBs */ 826 pci_devs_phb_init(); 827 828 /* Configure IOMMU DMA hooks */ 829 set_pci_dma_ops(&dma_iommu_ops); 830 } 831 832 machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init); 833