1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/crash_dump.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/string.h> 20 #include <linux/init.h> 21 #include <linux/bootmem.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/msi.h> 25 #include <linux/memblock.h> 26 #include <linux/iommu.h> 27 #include <linux/rculist.h> 28 #include <linux/sizes.h> 29 30 #include <asm/sections.h> 31 #include <asm/io.h> 32 #include <asm/prom.h> 33 #include <asm/pci-bridge.h> 34 #include <asm/machdep.h> 35 #include <asm/msi_bitmap.h> 36 #include <asm/ppc-pci.h> 37 #include <asm/opal.h> 38 #include <asm/iommu.h> 39 #include <asm/tce.h> 40 #include <asm/xics.h> 41 #include <asm/debug.h> 42 #include <asm/firmware.h> 43 #include <asm/pnv-pci.h> 44 #include <asm/mmzone.h> 45 46 #include <misc/cxl-base.h> 47 48 #include "powernv.h" 49 #include "pci.h" 50 51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ 52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ 53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 54 55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 56 #define POWERNV_IOMMU_MAX_LEVELS 5 57 58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; 59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 60 61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 62 const char *fmt, ...) 63 { 64 struct va_format vaf; 65 va_list args; 66 char pfix[32]; 67 68 va_start(args, fmt); 69 70 vaf.fmt = fmt; 71 vaf.va = &args; 72 73 if (pe->flags & PNV_IODA_PE_DEV) 74 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 75 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 76 sprintf(pfix, "%04x:%02x ", 77 pci_domain_nr(pe->pbus), pe->pbus->number); 78 #ifdef CONFIG_PCI_IOV 79 else if (pe->flags & PNV_IODA_PE_VF) 80 sprintf(pfix, "%04x:%02x:%2x.%d", 81 pci_domain_nr(pe->parent_dev->bus), 82 (pe->rid & 0xff00) >> 8, 83 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); 84 #endif /* CONFIG_PCI_IOV*/ 85 86 printk("%spci %s: [PE# %.3d] %pV", 87 level, pfix, pe->pe_number, &vaf); 88 89 va_end(args); 90 } 91 92 static bool pnv_iommu_bypass_disabled __read_mostly; 93 94 static int __init iommu_setup(char *str) 95 { 96 if (!str) 97 return -EINVAL; 98 99 while (*str) { 100 if (!strncmp(str, "nobypass", 8)) { 101 pnv_iommu_bypass_disabled = true; 102 pr_info("PowerNV: IOMMU bypass window disabled.\n"); 103 break; 104 } 105 str += strcspn(str, ","); 106 if (*str == ',') 107 str++; 108 } 109 110 return 0; 111 } 112 early_param("iommu", iommu_setup); 113 114 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) 115 { 116 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == 117 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); 118 } 119 120 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) 121 { 122 phb->ioda.pe_array[pe_no].phb = phb; 123 phb->ioda.pe_array[pe_no].pe_number = pe_no; 124 125 return &phb->ioda.pe_array[pe_no]; 126 } 127 128 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) 129 { 130 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { 131 pr_warn("%s: Invalid PE %d on PHB#%x\n", 132 __func__, pe_no, phb->hose->global_number); 133 return; 134 } 135 136 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) 137 pr_debug("%s: PE %d was reserved on PHB#%x\n", 138 __func__, pe_no, phb->hose->global_number); 139 140 pnv_ioda_init_pe(phb, pe_no); 141 } 142 143 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) 144 { 145 unsigned long pe = phb->ioda.total_pe_num - 1; 146 147 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { 148 if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) 149 return pnv_ioda_init_pe(phb, pe); 150 } 151 152 return NULL; 153 } 154 155 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) 156 { 157 struct pnv_phb *phb = pe->phb; 158 159 WARN_ON(pe->pdev); 160 161 memset(pe, 0, sizeof(struct pnv_ioda_pe)); 162 clear_bit(pe->pe_number, phb->ioda.pe_alloc); 163 } 164 165 /* The default M64 BAR is shared by all PEs */ 166 static int pnv_ioda2_init_m64(struct pnv_phb *phb) 167 { 168 const char *desc; 169 struct resource *r; 170 s64 rc; 171 172 /* Configure the default M64 BAR */ 173 rc = opal_pci_set_phb_mem_window(phb->opal_id, 174 OPAL_M64_WINDOW_TYPE, 175 phb->ioda.m64_bar_idx, 176 phb->ioda.m64_base, 177 0, /* unused */ 178 phb->ioda.m64_size); 179 if (rc != OPAL_SUCCESS) { 180 desc = "configuring"; 181 goto fail; 182 } 183 184 /* Enable the default M64 BAR */ 185 rc = opal_pci_phb_mmio_enable(phb->opal_id, 186 OPAL_M64_WINDOW_TYPE, 187 phb->ioda.m64_bar_idx, 188 OPAL_ENABLE_M64_SPLIT); 189 if (rc != OPAL_SUCCESS) { 190 desc = "enabling"; 191 goto fail; 192 } 193 194 /* Mark the M64 BAR assigned */ 195 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); 196 197 /* 198 * Exclude the segments for reserved and root bus PE, which 199 * are first or last two PEs. 200 */ 201 r = &phb->hose->mem_resources[1]; 202 if (phb->ioda.reserved_pe_idx == 0) 203 r->start += (2 * phb->ioda.m64_segsize); 204 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 205 r->end -= (2 * phb->ioda.m64_segsize); 206 else 207 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", 208 phb->ioda.reserved_pe_idx); 209 210 return 0; 211 212 fail: 213 pr_warn(" Failure %lld %s M64 BAR#%d\n", 214 rc, desc, phb->ioda.m64_bar_idx); 215 opal_pci_phb_mmio_enable(phb->opal_id, 216 OPAL_M64_WINDOW_TYPE, 217 phb->ioda.m64_bar_idx, 218 OPAL_DISABLE_M64); 219 return -EIO; 220 } 221 222 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, 223 unsigned long *pe_bitmap) 224 { 225 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 226 struct pnv_phb *phb = hose->private_data; 227 struct resource *r; 228 resource_size_t base, sgsz, start, end; 229 int segno, i; 230 231 base = phb->ioda.m64_base; 232 sgsz = phb->ioda.m64_segsize; 233 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 234 r = &pdev->resource[i]; 235 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) 236 continue; 237 238 start = _ALIGN_DOWN(r->start - base, sgsz); 239 end = _ALIGN_UP(r->end - base, sgsz); 240 for (segno = start / sgsz; segno < end / sgsz; segno++) { 241 if (pe_bitmap) 242 set_bit(segno, pe_bitmap); 243 else 244 pnv_ioda_reserve_pe(phb, segno); 245 } 246 } 247 } 248 249 static int pnv_ioda1_init_m64(struct pnv_phb *phb) 250 { 251 struct resource *r; 252 int index; 253 254 /* 255 * There are 16 M64 BARs, each of which has 8 segments. So 256 * there are as many M64 segments as the maximum number of 257 * PEs, which is 128. 258 */ 259 for (index = 0; index < PNV_IODA1_M64_NUM; index++) { 260 unsigned long base, segsz = phb->ioda.m64_segsize; 261 int64_t rc; 262 263 base = phb->ioda.m64_base + 264 index * PNV_IODA1_M64_SEGS * segsz; 265 rc = opal_pci_set_phb_mem_window(phb->opal_id, 266 OPAL_M64_WINDOW_TYPE, index, base, 0, 267 PNV_IODA1_M64_SEGS * segsz); 268 if (rc != OPAL_SUCCESS) { 269 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", 270 rc, phb->hose->global_number, index); 271 goto fail; 272 } 273 274 rc = opal_pci_phb_mmio_enable(phb->opal_id, 275 OPAL_M64_WINDOW_TYPE, index, 276 OPAL_ENABLE_M64_SPLIT); 277 if (rc != OPAL_SUCCESS) { 278 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", 279 rc, phb->hose->global_number, index); 280 goto fail; 281 } 282 } 283 284 /* 285 * Exclude the segments for reserved and root bus PE, which 286 * are first or last two PEs. 287 */ 288 r = &phb->hose->mem_resources[1]; 289 if (phb->ioda.reserved_pe_idx == 0) 290 r->start += (2 * phb->ioda.m64_segsize); 291 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) 292 r->end -= (2 * phb->ioda.m64_segsize); 293 else 294 WARN(1, "Wrong reserved PE#%d on PHB#%d\n", 295 phb->ioda.reserved_pe_idx, phb->hose->global_number); 296 297 return 0; 298 299 fail: 300 for ( ; index >= 0; index--) 301 opal_pci_phb_mmio_enable(phb->opal_id, 302 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); 303 304 return -EIO; 305 } 306 307 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, 308 unsigned long *pe_bitmap, 309 bool all) 310 { 311 struct pci_dev *pdev; 312 313 list_for_each_entry(pdev, &bus->devices, bus_list) { 314 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); 315 316 if (all && pdev->subordinate) 317 pnv_ioda_reserve_m64_pe(pdev->subordinate, 318 pe_bitmap, all); 319 } 320 } 321 322 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) 323 { 324 struct pci_controller *hose = pci_bus_to_host(bus); 325 struct pnv_phb *phb = hose->private_data; 326 struct pnv_ioda_pe *master_pe, *pe; 327 unsigned long size, *pe_alloc; 328 int i; 329 330 /* Root bus shouldn't use M64 */ 331 if (pci_is_root_bus(bus)) 332 return NULL; 333 334 /* Allocate bitmap */ 335 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); 336 pe_alloc = kzalloc(size, GFP_KERNEL); 337 if (!pe_alloc) { 338 pr_warn("%s: Out of memory !\n", 339 __func__); 340 return NULL; 341 } 342 343 /* Figure out reserved PE numbers by the PE */ 344 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); 345 346 /* 347 * the current bus might not own M64 window and that's all 348 * contributed by its child buses. For the case, we needn't 349 * pick M64 dependent PE#. 350 */ 351 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { 352 kfree(pe_alloc); 353 return NULL; 354 } 355 356 /* 357 * Figure out the master PE and put all slave PEs to master 358 * PE's list to form compound PE. 359 */ 360 master_pe = NULL; 361 i = -1; 362 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < 363 phb->ioda.total_pe_num) { 364 pe = &phb->ioda.pe_array[i]; 365 366 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; 367 if (!master_pe) { 368 pe->flags |= PNV_IODA_PE_MASTER; 369 INIT_LIST_HEAD(&pe->slaves); 370 master_pe = pe; 371 } else { 372 pe->flags |= PNV_IODA_PE_SLAVE; 373 pe->master = master_pe; 374 list_add_tail(&pe->list, &master_pe->slaves); 375 } 376 377 /* 378 * P7IOC supports M64DT, which helps mapping M64 segment 379 * to one particular PE#. However, PHB3 has fixed mapping 380 * between M64 segment and PE#. In order to have same logic 381 * for P7IOC and PHB3, we enforce fixed mapping between M64 382 * segment and PE# on P7IOC. 383 */ 384 if (phb->type == PNV_PHB_IODA1) { 385 int64_t rc; 386 387 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 388 pe->pe_number, OPAL_M64_WINDOW_TYPE, 389 pe->pe_number / PNV_IODA1_M64_SEGS, 390 pe->pe_number % PNV_IODA1_M64_SEGS); 391 if (rc != OPAL_SUCCESS) 392 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", 393 __func__, rc, phb->hose->global_number, 394 pe->pe_number); 395 } 396 } 397 398 kfree(pe_alloc); 399 return master_pe; 400 } 401 402 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) 403 { 404 struct pci_controller *hose = phb->hose; 405 struct device_node *dn = hose->dn; 406 struct resource *res; 407 const u32 *r; 408 u64 pci_addr; 409 410 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { 411 pr_info(" Not support M64 window\n"); 412 return; 413 } 414 415 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 416 pr_info(" Firmware too old to support M64 window\n"); 417 return; 418 } 419 420 r = of_get_property(dn, "ibm,opal-m64-window", NULL); 421 if (!r) { 422 pr_info(" No <ibm,opal-m64-window> on %s\n", 423 dn->full_name); 424 return; 425 } 426 427 res = &hose->mem_resources[1]; 428 res->name = dn->full_name; 429 res->start = of_translate_address(dn, r + 2); 430 res->end = res->start + of_read_number(r + 4, 2) - 1; 431 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 432 pci_addr = of_read_number(r, 2); 433 hose->mem_offset[1] = res->start - pci_addr; 434 435 phb->ioda.m64_size = resource_size(res); 436 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; 437 phb->ioda.m64_base = pci_addr; 438 439 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", 440 res->start, res->end, pci_addr); 441 442 /* Use last M64 BAR to cover M64 window */ 443 phb->ioda.m64_bar_idx = 15; 444 if (phb->type == PNV_PHB_IODA1) 445 phb->init_m64 = pnv_ioda1_init_m64; 446 else 447 phb->init_m64 = pnv_ioda2_init_m64; 448 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; 449 phb->pick_m64_pe = pnv_ioda_pick_m64_pe; 450 } 451 452 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) 453 { 454 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; 455 struct pnv_ioda_pe *slave; 456 s64 rc; 457 458 /* Fetch master PE */ 459 if (pe->flags & PNV_IODA_PE_SLAVE) { 460 pe = pe->master; 461 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) 462 return; 463 464 pe_no = pe->pe_number; 465 } 466 467 /* Freeze master PE */ 468 rc = opal_pci_eeh_freeze_set(phb->opal_id, 469 pe_no, 470 OPAL_EEH_ACTION_SET_FREEZE_ALL); 471 if (rc != OPAL_SUCCESS) { 472 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 473 __func__, rc, phb->hose->global_number, pe_no); 474 return; 475 } 476 477 /* Freeze slave PEs */ 478 if (!(pe->flags & PNV_IODA_PE_MASTER)) 479 return; 480 481 list_for_each_entry(slave, &pe->slaves, list) { 482 rc = opal_pci_eeh_freeze_set(phb->opal_id, 483 slave->pe_number, 484 OPAL_EEH_ACTION_SET_FREEZE_ALL); 485 if (rc != OPAL_SUCCESS) 486 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 487 __func__, rc, phb->hose->global_number, 488 slave->pe_number); 489 } 490 } 491 492 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) 493 { 494 struct pnv_ioda_pe *pe, *slave; 495 s64 rc; 496 497 /* Find master PE */ 498 pe = &phb->ioda.pe_array[pe_no]; 499 if (pe->flags & PNV_IODA_PE_SLAVE) { 500 pe = pe->master; 501 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 502 pe_no = pe->pe_number; 503 } 504 505 /* Clear frozen state for master PE */ 506 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); 507 if (rc != OPAL_SUCCESS) { 508 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 509 __func__, rc, opt, phb->hose->global_number, pe_no); 510 return -EIO; 511 } 512 513 if (!(pe->flags & PNV_IODA_PE_MASTER)) 514 return 0; 515 516 /* Clear frozen state for slave PEs */ 517 list_for_each_entry(slave, &pe->slaves, list) { 518 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 519 slave->pe_number, 520 opt); 521 if (rc != OPAL_SUCCESS) { 522 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", 523 __func__, rc, opt, phb->hose->global_number, 524 slave->pe_number); 525 return -EIO; 526 } 527 } 528 529 return 0; 530 } 531 532 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) 533 { 534 struct pnv_ioda_pe *slave, *pe; 535 u8 fstate, state; 536 __be16 pcierr; 537 s64 rc; 538 539 /* Sanity check on PE number */ 540 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) 541 return OPAL_EEH_STOPPED_PERM_UNAVAIL; 542 543 /* 544 * Fetch the master PE and the PE instance might be 545 * not initialized yet. 546 */ 547 pe = &phb->ioda.pe_array[pe_no]; 548 if (pe->flags & PNV_IODA_PE_SLAVE) { 549 pe = pe->master; 550 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); 551 pe_no = pe->pe_number; 552 } 553 554 /* Check the master PE */ 555 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, 556 &state, &pcierr, NULL); 557 if (rc != OPAL_SUCCESS) { 558 pr_warn("%s: Failure %lld getting " 559 "PHB#%x-PE#%x state\n", 560 __func__, rc, 561 phb->hose->global_number, pe_no); 562 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 563 } 564 565 /* Check the slave PE */ 566 if (!(pe->flags & PNV_IODA_PE_MASTER)) 567 return state; 568 569 list_for_each_entry(slave, &pe->slaves, list) { 570 rc = opal_pci_eeh_freeze_status(phb->opal_id, 571 slave->pe_number, 572 &fstate, 573 &pcierr, 574 NULL); 575 if (rc != OPAL_SUCCESS) { 576 pr_warn("%s: Failure %lld getting " 577 "PHB#%x-PE#%x state\n", 578 __func__, rc, 579 phb->hose->global_number, slave->pe_number); 580 return OPAL_EEH_STOPPED_TEMP_UNAVAIL; 581 } 582 583 /* 584 * Override the result based on the ascending 585 * priority. 586 */ 587 if (fstate > state) 588 state = fstate; 589 } 590 591 return state; 592 } 593 594 /* Currently those 2 are only used when MSIs are enabled, this will change 595 * but in the meantime, we need to protect them to avoid warnings 596 */ 597 #ifdef CONFIG_PCI_MSI 598 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) 599 { 600 struct pci_controller *hose = pci_bus_to_host(dev->bus); 601 struct pnv_phb *phb = hose->private_data; 602 struct pci_dn *pdn = pci_get_pdn(dev); 603 604 if (!pdn) 605 return NULL; 606 if (pdn->pe_number == IODA_INVALID_PE) 607 return NULL; 608 return &phb->ioda.pe_array[pdn->pe_number]; 609 } 610 #endif /* CONFIG_PCI_MSI */ 611 612 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, 613 struct pnv_ioda_pe *parent, 614 struct pnv_ioda_pe *child, 615 bool is_add) 616 { 617 const char *desc = is_add ? "adding" : "removing"; 618 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : 619 OPAL_REMOVE_PE_FROM_DOMAIN; 620 struct pnv_ioda_pe *slave; 621 long rc; 622 623 /* Parent PE affects child PE */ 624 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 625 child->pe_number, op); 626 if (rc != OPAL_SUCCESS) { 627 pe_warn(child, "OPAL error %ld %s to parent PELTV\n", 628 rc, desc); 629 return -ENXIO; 630 } 631 632 if (!(child->flags & PNV_IODA_PE_MASTER)) 633 return 0; 634 635 /* Compound case: parent PE affects slave PEs */ 636 list_for_each_entry(slave, &child->slaves, list) { 637 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, 638 slave->pe_number, op); 639 if (rc != OPAL_SUCCESS) { 640 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", 641 rc, desc); 642 return -ENXIO; 643 } 644 } 645 646 return 0; 647 } 648 649 static int pnv_ioda_set_peltv(struct pnv_phb *phb, 650 struct pnv_ioda_pe *pe, 651 bool is_add) 652 { 653 struct pnv_ioda_pe *slave; 654 struct pci_dev *pdev = NULL; 655 int ret; 656 657 /* 658 * Clear PE frozen state. If it's master PE, we need 659 * clear slave PE frozen state as well. 660 */ 661 if (is_add) { 662 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 663 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 664 if (pe->flags & PNV_IODA_PE_MASTER) { 665 list_for_each_entry(slave, &pe->slaves, list) 666 opal_pci_eeh_freeze_clear(phb->opal_id, 667 slave->pe_number, 668 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 669 } 670 } 671 672 /* 673 * Associate PE in PELT. We need add the PE into the 674 * corresponding PELT-V as well. Otherwise, the error 675 * originated from the PE might contribute to other 676 * PEs. 677 */ 678 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); 679 if (ret) 680 return ret; 681 682 /* For compound PEs, any one affects all of them */ 683 if (pe->flags & PNV_IODA_PE_MASTER) { 684 list_for_each_entry(slave, &pe->slaves, list) { 685 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); 686 if (ret) 687 return ret; 688 } 689 } 690 691 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 692 pdev = pe->pbus->self; 693 else if (pe->flags & PNV_IODA_PE_DEV) 694 pdev = pe->pdev->bus->self; 695 #ifdef CONFIG_PCI_IOV 696 else if (pe->flags & PNV_IODA_PE_VF) 697 pdev = pe->parent_dev; 698 #endif /* CONFIG_PCI_IOV */ 699 while (pdev) { 700 struct pci_dn *pdn = pci_get_pdn(pdev); 701 struct pnv_ioda_pe *parent; 702 703 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 704 parent = &phb->ioda.pe_array[pdn->pe_number]; 705 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); 706 if (ret) 707 return ret; 708 } 709 710 pdev = pdev->bus->self; 711 } 712 713 return 0; 714 } 715 716 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 717 { 718 struct pci_dev *parent; 719 uint8_t bcomp, dcomp, fcomp; 720 int64_t rc; 721 long rid_end, rid; 722 723 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ 724 if (pe->pbus) { 725 int count; 726 727 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 728 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 729 parent = pe->pbus->self; 730 if (pe->flags & PNV_IODA_PE_BUS_ALL) 731 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 732 else 733 count = 1; 734 735 switch(count) { 736 case 1: bcomp = OpalPciBusAll; break; 737 case 2: bcomp = OpalPciBus7Bits; break; 738 case 4: bcomp = OpalPciBus6Bits; break; 739 case 8: bcomp = OpalPciBus5Bits; break; 740 case 16: bcomp = OpalPciBus4Bits; break; 741 case 32: bcomp = OpalPciBus3Bits; break; 742 default: 743 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 744 count); 745 /* Do an exact match only */ 746 bcomp = OpalPciBusAll; 747 } 748 rid_end = pe->rid + (count << 8); 749 } else { 750 #ifdef CONFIG_PCI_IOV 751 if (pe->flags & PNV_IODA_PE_VF) 752 parent = pe->parent_dev; 753 else 754 #endif 755 parent = pe->pdev->bus->self; 756 bcomp = OpalPciBusAll; 757 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 758 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 759 rid_end = pe->rid + 1; 760 } 761 762 /* Clear the reverse map */ 763 for (rid = pe->rid; rid < rid_end; rid++) 764 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; 765 766 /* Release from all parents PELT-V */ 767 while (parent) { 768 struct pci_dn *pdn = pci_get_pdn(parent); 769 if (pdn && pdn->pe_number != IODA_INVALID_PE) { 770 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, 771 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 772 /* XXX What to do in case of error ? */ 773 } 774 parent = parent->bus->self; 775 } 776 777 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, 778 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 779 780 /* Disassociate PE in PELT */ 781 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, 782 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); 783 if (rc) 784 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); 785 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 786 bcomp, dcomp, fcomp, OPAL_UNMAP_PE); 787 if (rc) 788 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 789 790 pe->pbus = NULL; 791 pe->pdev = NULL; 792 #ifdef CONFIG_PCI_IOV 793 pe->parent_dev = NULL; 794 #endif 795 796 return 0; 797 } 798 799 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 800 { 801 struct pci_dev *parent; 802 uint8_t bcomp, dcomp, fcomp; 803 long rc, rid_end, rid; 804 805 /* Bus validation ? */ 806 if (pe->pbus) { 807 int count; 808 809 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 810 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 811 parent = pe->pbus->self; 812 if (pe->flags & PNV_IODA_PE_BUS_ALL) 813 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; 814 else 815 count = 1; 816 817 switch(count) { 818 case 1: bcomp = OpalPciBusAll; break; 819 case 2: bcomp = OpalPciBus7Bits; break; 820 case 4: bcomp = OpalPciBus6Bits; break; 821 case 8: bcomp = OpalPciBus5Bits; break; 822 case 16: bcomp = OpalPciBus4Bits; break; 823 case 32: bcomp = OpalPciBus3Bits; break; 824 default: 825 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", 826 count); 827 /* Do an exact match only */ 828 bcomp = OpalPciBusAll; 829 } 830 rid_end = pe->rid + (count << 8); 831 } else { 832 #ifdef CONFIG_PCI_IOV 833 if (pe->flags & PNV_IODA_PE_VF) 834 parent = pe->parent_dev; 835 else 836 #endif /* CONFIG_PCI_IOV */ 837 parent = pe->pdev->bus->self; 838 bcomp = OpalPciBusAll; 839 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 840 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 841 rid_end = pe->rid + 1; 842 } 843 844 /* 845 * Associate PE in PELT. We need add the PE into the 846 * corresponding PELT-V as well. Otherwise, the error 847 * originated from the PE might contribute to other 848 * PEs. 849 */ 850 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, 851 bcomp, dcomp, fcomp, OPAL_MAP_PE); 852 if (rc) { 853 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); 854 return -ENXIO; 855 } 856 857 /* 858 * Configure PELTV. NPUs don't have a PELTV table so skip 859 * configuration on them. 860 */ 861 if (phb->type != PNV_PHB_NPU) 862 pnv_ioda_set_peltv(phb, pe, true); 863 864 /* Setup reverse map */ 865 for (rid = pe->rid; rid < rid_end; rid++) 866 phb->ioda.pe_rmap[rid] = pe->pe_number; 867 868 /* Setup one MVTs on IODA1 */ 869 if (phb->type != PNV_PHB_IODA1) { 870 pe->mve_number = 0; 871 goto out; 872 } 873 874 pe->mve_number = pe->pe_number; 875 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); 876 if (rc != OPAL_SUCCESS) { 877 pe_err(pe, "OPAL error %ld setting up MVE %d\n", 878 rc, pe->mve_number); 879 pe->mve_number = -1; 880 } else { 881 rc = opal_pci_set_mve_enable(phb->opal_id, 882 pe->mve_number, OPAL_ENABLE_MVE); 883 if (rc) { 884 pe_err(pe, "OPAL error %ld enabling MVE %d\n", 885 rc, pe->mve_number); 886 pe->mve_number = -1; 887 } 888 } 889 890 out: 891 return 0; 892 } 893 894 #ifdef CONFIG_PCI_IOV 895 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 896 { 897 struct pci_dn *pdn = pci_get_pdn(dev); 898 int i; 899 struct resource *res, res2; 900 resource_size_t size; 901 u16 num_vfs; 902 903 if (!dev->is_physfn) 904 return -EINVAL; 905 906 /* 907 * "offset" is in VFs. The M64 windows are sized so that when they 908 * are segmented, each segment is the same size as the IOV BAR. 909 * Each segment is in a separate PE, and the high order bits of the 910 * address are the PE number. Therefore, each VF's BAR is in a 911 * separate PE, and changing the IOV BAR start address changes the 912 * range of PEs the VFs are in. 913 */ 914 num_vfs = pdn->num_vfs; 915 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 916 res = &dev->resource[i + PCI_IOV_RESOURCES]; 917 if (!res->flags || !res->parent) 918 continue; 919 920 /* 921 * The actual IOV BAR range is determined by the start address 922 * and the actual size for num_vfs VFs BAR. This check is to 923 * make sure that after shifting, the range will not overlap 924 * with another device. 925 */ 926 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 927 res2.flags = res->flags; 928 res2.start = res->start + (size * offset); 929 res2.end = res2.start + (size * num_vfs) - 1; 930 931 if (res2.end > res->end) { 932 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 933 i, &res2, res, num_vfs, offset); 934 return -EBUSY; 935 } 936 } 937 938 /* 939 * After doing so, there would be a "hole" in the /proc/iomem when 940 * offset is a positive value. It looks like the device return some 941 * mmio back to the system, which actually no one could use it. 942 */ 943 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 944 res = &dev->resource[i + PCI_IOV_RESOURCES]; 945 if (!res->flags || !res->parent) 946 continue; 947 948 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 949 res2 = *res; 950 res->start += size * offset; 951 952 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 953 i, &res2, res, (offset > 0) ? "En" : "Dis", 954 num_vfs, offset); 955 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 956 } 957 return 0; 958 } 959 #endif /* CONFIG_PCI_IOV */ 960 961 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 962 { 963 struct pci_controller *hose = pci_bus_to_host(dev->bus); 964 struct pnv_phb *phb = hose->private_data; 965 struct pci_dn *pdn = pci_get_pdn(dev); 966 struct pnv_ioda_pe *pe; 967 968 if (!pdn) { 969 pr_err("%s: Device tree node not associated properly\n", 970 pci_name(dev)); 971 return NULL; 972 } 973 if (pdn->pe_number != IODA_INVALID_PE) 974 return NULL; 975 976 pe = pnv_ioda_alloc_pe(phb); 977 if (!pe) { 978 pr_warning("%s: Not enough PE# available, disabling device\n", 979 pci_name(dev)); 980 return NULL; 981 } 982 983 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the 984 * pointer in the PE data structure, both should be destroyed at the 985 * same time. However, this needs to be looked at more closely again 986 * once we actually start removing things (Hotplug, SR-IOV, ...) 987 * 988 * At some point we want to remove the PDN completely anyways 989 */ 990 pci_dev_get(dev); 991 pdn->pcidev = dev; 992 pdn->pe_number = pe->pe_number; 993 pe->flags = PNV_IODA_PE_DEV; 994 pe->pdev = dev; 995 pe->pbus = NULL; 996 pe->mve_number = -1; 997 pe->rid = dev->bus->number << 8 | pdn->devfn; 998 999 pe_info(pe, "Associated device to PE\n"); 1000 1001 if (pnv_ioda_configure_pe(phb, pe)) { 1002 /* XXX What do we do here ? */ 1003 pnv_ioda_free_pe(pe); 1004 pdn->pe_number = IODA_INVALID_PE; 1005 pe->pdev = NULL; 1006 pci_dev_put(dev); 1007 return NULL; 1008 } 1009 1010 /* Put PE to the list */ 1011 list_add_tail(&pe->list, &phb->ioda.pe_list); 1012 1013 return pe; 1014 } 1015 1016 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) 1017 { 1018 struct pci_dev *dev; 1019 1020 list_for_each_entry(dev, &bus->devices, bus_list) { 1021 struct pci_dn *pdn = pci_get_pdn(dev); 1022 1023 if (pdn == NULL) { 1024 pr_warn("%s: No device node associated with device !\n", 1025 pci_name(dev)); 1026 continue; 1027 } 1028 1029 /* 1030 * In partial hotplug case, the PCI device might be still 1031 * associated with the PE and needn't attach it to the PE 1032 * again. 1033 */ 1034 if (pdn->pe_number != IODA_INVALID_PE) 1035 continue; 1036 1037 pe->device_count++; 1038 pdn->pcidev = dev; 1039 pdn->pe_number = pe->pe_number; 1040 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1041 pnv_ioda_setup_same_PE(dev->subordinate, pe); 1042 } 1043 } 1044 1045 /* 1046 * There're 2 types of PCI bus sensitive PEs: One that is compromised of 1047 * single PCI bus. Another one that contains the primary PCI bus and its 1048 * subordinate PCI devices and buses. The second type of PE is normally 1049 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. 1050 */ 1051 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) 1052 { 1053 struct pci_controller *hose = pci_bus_to_host(bus); 1054 struct pnv_phb *phb = hose->private_data; 1055 struct pnv_ioda_pe *pe = NULL; 1056 unsigned int pe_num; 1057 1058 /* 1059 * In partial hotplug case, the PE instance might be still alive. 1060 * We should reuse it instead of allocating a new one. 1061 */ 1062 pe_num = phb->ioda.pe_rmap[bus->number << 8]; 1063 if (pe_num != IODA_INVALID_PE) { 1064 pe = &phb->ioda.pe_array[pe_num]; 1065 pnv_ioda_setup_same_PE(bus, pe); 1066 return NULL; 1067 } 1068 1069 /* PE number for root bus should have been reserved */ 1070 if (pci_is_root_bus(bus) && 1071 phb->ioda.root_pe_idx != IODA_INVALID_PE) 1072 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; 1073 1074 /* Check if PE is determined by M64 */ 1075 if (!pe && phb->pick_m64_pe) 1076 pe = phb->pick_m64_pe(bus, all); 1077 1078 /* The PE number isn't pinned by M64 */ 1079 if (!pe) 1080 pe = pnv_ioda_alloc_pe(phb); 1081 1082 if (!pe) { 1083 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", 1084 __func__, pci_domain_nr(bus), bus->number); 1085 return NULL; 1086 } 1087 1088 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); 1089 pe->pbus = bus; 1090 pe->pdev = NULL; 1091 pe->mve_number = -1; 1092 pe->rid = bus->busn_res.start << 8; 1093 1094 if (all) 1095 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", 1096 bus->busn_res.start, bus->busn_res.end, pe->pe_number); 1097 else 1098 pe_info(pe, "Secondary bus %d associated with PE#%d\n", 1099 bus->busn_res.start, pe->pe_number); 1100 1101 if (pnv_ioda_configure_pe(phb, pe)) { 1102 /* XXX What do we do here ? */ 1103 pnv_ioda_free_pe(pe); 1104 pe->pbus = NULL; 1105 return NULL; 1106 } 1107 1108 /* Associate it with all child devices */ 1109 pnv_ioda_setup_same_PE(bus, pe); 1110 1111 /* Put PE to the list */ 1112 list_add_tail(&pe->list, &phb->ioda.pe_list); 1113 1114 return pe; 1115 } 1116 1117 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) 1118 { 1119 int pe_num, found_pe = false, rc; 1120 long rid; 1121 struct pnv_ioda_pe *pe; 1122 struct pci_dev *gpu_pdev; 1123 struct pci_dn *npu_pdn; 1124 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); 1125 struct pnv_phb *phb = hose->private_data; 1126 1127 /* 1128 * Due to a hardware errata PE#0 on the NPU is reserved for 1129 * error handling. This means we only have three PEs remaining 1130 * which need to be assigned to four links, implying some 1131 * links must share PEs. 1132 * 1133 * To achieve this we assign PEs such that NPUs linking the 1134 * same GPU get assigned the same PE. 1135 */ 1136 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); 1137 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { 1138 pe = &phb->ioda.pe_array[pe_num]; 1139 if (!pe->pdev) 1140 continue; 1141 1142 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { 1143 /* 1144 * This device has the same peer GPU so should 1145 * be assigned the same PE as the existing 1146 * peer NPU. 1147 */ 1148 dev_info(&npu_pdev->dev, 1149 "Associating to existing PE %d\n", pe_num); 1150 pci_dev_get(npu_pdev); 1151 npu_pdn = pci_get_pdn(npu_pdev); 1152 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; 1153 npu_pdn->pcidev = npu_pdev; 1154 npu_pdn->pe_number = pe_num; 1155 phb->ioda.pe_rmap[rid] = pe->pe_number; 1156 1157 /* Map the PE to this link */ 1158 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, 1159 OpalPciBusAll, 1160 OPAL_COMPARE_RID_DEVICE_NUMBER, 1161 OPAL_COMPARE_RID_FUNCTION_NUMBER, 1162 OPAL_MAP_PE); 1163 WARN_ON(rc != OPAL_SUCCESS); 1164 found_pe = true; 1165 break; 1166 } 1167 } 1168 1169 if (!found_pe) 1170 /* 1171 * Could not find an existing PE so allocate a new 1172 * one. 1173 */ 1174 return pnv_ioda_setup_dev_PE(npu_pdev); 1175 else 1176 return pe; 1177 } 1178 1179 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) 1180 { 1181 struct pci_dev *pdev; 1182 1183 list_for_each_entry(pdev, &bus->devices, bus_list) 1184 pnv_ioda_setup_npu_PE(pdev); 1185 } 1186 1187 static void pnv_pci_ioda_setup_PEs(void) 1188 { 1189 struct pci_controller *hose, *tmp; 1190 struct pnv_phb *phb; 1191 1192 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1193 phb = hose->private_data; 1194 if (phb->type == PNV_PHB_NPU) { 1195 /* PE#0 is needed for error reporting */ 1196 pnv_ioda_reserve_pe(phb, 0); 1197 pnv_ioda_setup_npu_PEs(hose->bus); 1198 } 1199 } 1200 } 1201 1202 #ifdef CONFIG_PCI_IOV 1203 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 1204 { 1205 struct pci_bus *bus; 1206 struct pci_controller *hose; 1207 struct pnv_phb *phb; 1208 struct pci_dn *pdn; 1209 int i, j; 1210 int m64_bars; 1211 1212 bus = pdev->bus; 1213 hose = pci_bus_to_host(bus); 1214 phb = hose->private_data; 1215 pdn = pci_get_pdn(pdev); 1216 1217 if (pdn->m64_single_mode) 1218 m64_bars = num_vfs; 1219 else 1220 m64_bars = 1; 1221 1222 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 1223 for (j = 0; j < m64_bars; j++) { 1224 if (pdn->m64_map[j][i] == IODA_INVALID_M64) 1225 continue; 1226 opal_pci_phb_mmio_enable(phb->opal_id, 1227 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); 1228 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); 1229 pdn->m64_map[j][i] = IODA_INVALID_M64; 1230 } 1231 1232 kfree(pdn->m64_map); 1233 return 0; 1234 } 1235 1236 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 1237 { 1238 struct pci_bus *bus; 1239 struct pci_controller *hose; 1240 struct pnv_phb *phb; 1241 struct pci_dn *pdn; 1242 unsigned int win; 1243 struct resource *res; 1244 int i, j; 1245 int64_t rc; 1246 int total_vfs; 1247 resource_size_t size, start; 1248 int pe_num; 1249 int m64_bars; 1250 1251 bus = pdev->bus; 1252 hose = pci_bus_to_host(bus); 1253 phb = hose->private_data; 1254 pdn = pci_get_pdn(pdev); 1255 total_vfs = pci_sriov_get_totalvfs(pdev); 1256 1257 if (pdn->m64_single_mode) 1258 m64_bars = num_vfs; 1259 else 1260 m64_bars = 1; 1261 1262 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); 1263 if (!pdn->m64_map) 1264 return -ENOMEM; 1265 /* Initialize the m64_map to IODA_INVALID_M64 */ 1266 for (i = 0; i < m64_bars ; i++) 1267 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 1268 pdn->m64_map[i][j] = IODA_INVALID_M64; 1269 1270 1271 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1272 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 1273 if (!res->flags || !res->parent) 1274 continue; 1275 1276 for (j = 0; j < m64_bars; j++) { 1277 do { 1278 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 1279 phb->ioda.m64_bar_idx + 1, 0); 1280 1281 if (win >= phb->ioda.m64_bar_idx + 1) 1282 goto m64_failed; 1283 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 1284 1285 pdn->m64_map[j][i] = win; 1286 1287 if (pdn->m64_single_mode) { 1288 size = pci_iov_resource_size(pdev, 1289 PCI_IOV_RESOURCES + i); 1290 start = res->start + size * j; 1291 } else { 1292 size = resource_size(res); 1293 start = res->start; 1294 } 1295 1296 /* Map the M64 here */ 1297 if (pdn->m64_single_mode) { 1298 pe_num = pdn->pe_num_map[j]; 1299 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 1300 pe_num, OPAL_M64_WINDOW_TYPE, 1301 pdn->m64_map[j][i], 0); 1302 } 1303 1304 rc = opal_pci_set_phb_mem_window(phb->opal_id, 1305 OPAL_M64_WINDOW_TYPE, 1306 pdn->m64_map[j][i], 1307 start, 1308 0, /* unused */ 1309 size); 1310 1311 1312 if (rc != OPAL_SUCCESS) { 1313 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 1314 win, rc); 1315 goto m64_failed; 1316 } 1317 1318 if (pdn->m64_single_mode) 1319 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1320 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); 1321 else 1322 rc = opal_pci_phb_mmio_enable(phb->opal_id, 1323 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); 1324 1325 if (rc != OPAL_SUCCESS) { 1326 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 1327 win, rc); 1328 goto m64_failed; 1329 } 1330 } 1331 } 1332 return 0; 1333 1334 m64_failed: 1335 pnv_pci_vf_release_m64(pdev, num_vfs); 1336 return -EBUSY; 1337 } 1338 1339 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 1340 int num); 1341 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 1342 1343 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) 1344 { 1345 struct iommu_table *tbl; 1346 int64_t rc; 1347 1348 tbl = pe->table_group.tables[0]; 1349 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 1350 if (rc) 1351 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 1352 1353 pnv_pci_ioda2_set_bypass(pe, false); 1354 if (pe->table_group.group) { 1355 iommu_group_put(pe->table_group.group); 1356 BUG_ON(pe->table_group.group); 1357 } 1358 pnv_pci_ioda2_table_free_pages(tbl); 1359 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); 1360 } 1361 1362 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 1363 { 1364 struct pci_bus *bus; 1365 struct pci_controller *hose; 1366 struct pnv_phb *phb; 1367 struct pnv_ioda_pe *pe, *pe_n; 1368 struct pci_dn *pdn; 1369 1370 bus = pdev->bus; 1371 hose = pci_bus_to_host(bus); 1372 phb = hose->private_data; 1373 pdn = pci_get_pdn(pdev); 1374 1375 if (!pdev->is_physfn) 1376 return; 1377 1378 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 1379 if (pe->parent_dev != pdev) 1380 continue; 1381 1382 pnv_pci_ioda2_release_dma_pe(pdev, pe); 1383 1384 /* Remove from list */ 1385 mutex_lock(&phb->ioda.pe_list_mutex); 1386 list_del(&pe->list); 1387 mutex_unlock(&phb->ioda.pe_list_mutex); 1388 1389 pnv_ioda_deconfigure_pe(phb, pe); 1390 1391 pnv_ioda_free_pe(pe); 1392 } 1393 } 1394 1395 void pnv_pci_sriov_disable(struct pci_dev *pdev) 1396 { 1397 struct pci_bus *bus; 1398 struct pci_controller *hose; 1399 struct pnv_phb *phb; 1400 struct pnv_ioda_pe *pe; 1401 struct pci_dn *pdn; 1402 struct pci_sriov *iov; 1403 u16 num_vfs, i; 1404 1405 bus = pdev->bus; 1406 hose = pci_bus_to_host(bus); 1407 phb = hose->private_data; 1408 pdn = pci_get_pdn(pdev); 1409 iov = pdev->sriov; 1410 num_vfs = pdn->num_vfs; 1411 1412 /* Release VF PEs */ 1413 pnv_ioda_release_vf_PE(pdev); 1414 1415 if (phb->type == PNV_PHB_IODA2) { 1416 if (!pdn->m64_single_mode) 1417 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); 1418 1419 /* Release M64 windows */ 1420 pnv_pci_vf_release_m64(pdev, num_vfs); 1421 1422 /* Release PE numbers */ 1423 if (pdn->m64_single_mode) { 1424 for (i = 0; i < num_vfs; i++) { 1425 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1426 continue; 1427 1428 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1429 pnv_ioda_free_pe(pe); 1430 } 1431 } else 1432 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1433 /* Releasing pe_num_map */ 1434 kfree(pdn->pe_num_map); 1435 } 1436 } 1437 1438 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1439 struct pnv_ioda_pe *pe); 1440 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 1441 { 1442 struct pci_bus *bus; 1443 struct pci_controller *hose; 1444 struct pnv_phb *phb; 1445 struct pnv_ioda_pe *pe; 1446 int pe_num; 1447 u16 vf_index; 1448 struct pci_dn *pdn; 1449 1450 bus = pdev->bus; 1451 hose = pci_bus_to_host(bus); 1452 phb = hose->private_data; 1453 pdn = pci_get_pdn(pdev); 1454 1455 if (!pdev->is_physfn) 1456 return; 1457 1458 /* Reserve PE for each VF */ 1459 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 1460 if (pdn->m64_single_mode) 1461 pe_num = pdn->pe_num_map[vf_index]; 1462 else 1463 pe_num = *pdn->pe_num_map + vf_index; 1464 1465 pe = &phb->ioda.pe_array[pe_num]; 1466 pe->pe_number = pe_num; 1467 pe->phb = phb; 1468 pe->flags = PNV_IODA_PE_VF; 1469 pe->pbus = NULL; 1470 pe->parent_dev = pdev; 1471 pe->mve_number = -1; 1472 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | 1473 pci_iov_virtfn_devfn(pdev, vf_index); 1474 1475 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", 1476 hose->global_number, pdev->bus->number, 1477 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), 1478 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); 1479 1480 if (pnv_ioda_configure_pe(phb, pe)) { 1481 /* XXX What do we do here ? */ 1482 pnv_ioda_free_pe(pe); 1483 pe->pdev = NULL; 1484 continue; 1485 } 1486 1487 /* Put PE to the list */ 1488 mutex_lock(&phb->ioda.pe_list_mutex); 1489 list_add_tail(&pe->list, &phb->ioda.pe_list); 1490 mutex_unlock(&phb->ioda.pe_list_mutex); 1491 1492 pnv_pci_ioda2_setup_dma_pe(phb, pe); 1493 } 1494 } 1495 1496 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1497 { 1498 struct pci_bus *bus; 1499 struct pci_controller *hose; 1500 struct pnv_phb *phb; 1501 struct pnv_ioda_pe *pe; 1502 struct pci_dn *pdn; 1503 int ret; 1504 u16 i; 1505 1506 bus = pdev->bus; 1507 hose = pci_bus_to_host(bus); 1508 phb = hose->private_data; 1509 pdn = pci_get_pdn(pdev); 1510 1511 if (phb->type == PNV_PHB_IODA2) { 1512 if (!pdn->vfs_expanded) { 1513 dev_info(&pdev->dev, "don't support this SRIOV device" 1514 " with non 64bit-prefetchable IOV BAR\n"); 1515 return -ENOSPC; 1516 } 1517 1518 /* 1519 * When M64 BARs functions in Single PE mode, the number of VFs 1520 * could be enabled must be less than the number of M64 BARs. 1521 */ 1522 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 1523 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 1524 return -EBUSY; 1525 } 1526 1527 /* Allocating pe_num_map */ 1528 if (pdn->m64_single_mode) 1529 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, 1530 GFP_KERNEL); 1531 else 1532 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); 1533 1534 if (!pdn->pe_num_map) 1535 return -ENOMEM; 1536 1537 if (pdn->m64_single_mode) 1538 for (i = 0; i < num_vfs; i++) 1539 pdn->pe_num_map[i] = IODA_INVALID_PE; 1540 1541 /* Calculate available PE for required VFs */ 1542 if (pdn->m64_single_mode) { 1543 for (i = 0; i < num_vfs; i++) { 1544 pe = pnv_ioda_alloc_pe(phb); 1545 if (!pe) { 1546 ret = -EBUSY; 1547 goto m64_failed; 1548 } 1549 1550 pdn->pe_num_map[i] = pe->pe_number; 1551 } 1552 } else { 1553 mutex_lock(&phb->ioda.pe_alloc_mutex); 1554 *pdn->pe_num_map = bitmap_find_next_zero_area( 1555 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 1556 0, num_vfs, 0); 1557 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { 1558 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1559 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 1560 kfree(pdn->pe_num_map); 1561 return -EBUSY; 1562 } 1563 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1564 mutex_unlock(&phb->ioda.pe_alloc_mutex); 1565 } 1566 pdn->num_vfs = num_vfs; 1567 1568 /* Assign M64 window accordingly */ 1569 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 1570 if (ret) { 1571 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 1572 goto m64_failed; 1573 } 1574 1575 /* 1576 * When using one M64 BAR to map one IOV BAR, we need to shift 1577 * the IOV BAR according to the PE# allocated to the VFs. 1578 * Otherwise, the PE# for the VF will conflict with others. 1579 */ 1580 if (!pdn->m64_single_mode) { 1581 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); 1582 if (ret) 1583 goto m64_failed; 1584 } 1585 } 1586 1587 /* Setup VF PEs */ 1588 pnv_ioda_setup_vf_PE(pdev, num_vfs); 1589 1590 return 0; 1591 1592 m64_failed: 1593 if (pdn->m64_single_mode) { 1594 for (i = 0; i < num_vfs; i++) { 1595 if (pdn->pe_num_map[i] == IODA_INVALID_PE) 1596 continue; 1597 1598 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; 1599 pnv_ioda_free_pe(pe); 1600 } 1601 } else 1602 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); 1603 1604 /* Releasing pe_num_map */ 1605 kfree(pdn->pe_num_map); 1606 1607 return ret; 1608 } 1609 1610 int pcibios_sriov_disable(struct pci_dev *pdev) 1611 { 1612 pnv_pci_sriov_disable(pdev); 1613 1614 /* Release PCI data */ 1615 remove_dev_pci_data(pdev); 1616 return 0; 1617 } 1618 1619 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 1620 { 1621 /* Allocate PCI data */ 1622 add_dev_pci_data(pdev); 1623 1624 return pnv_pci_sriov_enable(pdev, num_vfs); 1625 } 1626 #endif /* CONFIG_PCI_IOV */ 1627 1628 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1629 { 1630 struct pci_dn *pdn = pci_get_pdn(pdev); 1631 struct pnv_ioda_pe *pe; 1632 1633 /* 1634 * The function can be called while the PE# 1635 * hasn't been assigned. Do nothing for the 1636 * case. 1637 */ 1638 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 1639 return; 1640 1641 pe = &phb->ioda.pe_array[pdn->pe_number]; 1642 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1643 set_dma_offset(&pdev->dev, pe->tce_bypass_base); 1644 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); 1645 /* 1646 * Note: iommu_add_device() will fail here as 1647 * for physical PE: the device is already added by now; 1648 * for virtual PE: sysfs entries are not ready yet and 1649 * tce_iommu_bus_notifier will add the device to a group later. 1650 */ 1651 } 1652 1653 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 1654 { 1655 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1656 struct pnv_phb *phb = hose->private_data; 1657 struct pci_dn *pdn = pci_get_pdn(pdev); 1658 struct pnv_ioda_pe *pe; 1659 uint64_t top; 1660 bool bypass = false; 1661 1662 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1663 return -ENODEV;; 1664 1665 pe = &phb->ioda.pe_array[pdn->pe_number]; 1666 if (pe->tce_bypass_enabled) { 1667 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; 1668 bypass = (dma_mask >= top); 1669 } 1670 1671 if (bypass) { 1672 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); 1673 set_dma_ops(&pdev->dev, &dma_direct_ops); 1674 } else { 1675 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1676 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1677 } 1678 *pdev->dev.dma_mask = dma_mask; 1679 1680 /* Update peer npu devices */ 1681 pnv_npu_try_dma_set_bypass(pdev, bypass); 1682 1683 return 0; 1684 } 1685 1686 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) 1687 { 1688 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 1689 struct pnv_phb *phb = hose->private_data; 1690 struct pci_dn *pdn = pci_get_pdn(pdev); 1691 struct pnv_ioda_pe *pe; 1692 u64 end, mask; 1693 1694 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) 1695 return 0; 1696 1697 pe = &phb->ioda.pe_array[pdn->pe_number]; 1698 if (!pe->tce_bypass_enabled) 1699 return __dma_get_required_mask(&pdev->dev); 1700 1701 1702 end = pe->tce_bypass_base + memblock_end_of_DRAM(); 1703 mask = 1ULL << (fls64(end) - 1); 1704 mask += mask - 1; 1705 1706 return mask; 1707 } 1708 1709 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, 1710 struct pci_bus *bus) 1711 { 1712 struct pci_dev *dev; 1713 1714 list_for_each_entry(dev, &bus->devices, bus_list) { 1715 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); 1716 set_dma_offset(&dev->dev, pe->tce_bypass_base); 1717 iommu_add_device(&dev->dev); 1718 1719 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1720 pnv_ioda_setup_bus_dma(pe, dev->subordinate); 1721 } 1722 } 1723 1724 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, 1725 unsigned long index, unsigned long npages, bool rm) 1726 { 1727 struct iommu_table_group_link *tgl = list_first_entry_or_null( 1728 &tbl->it_group_list, struct iommu_table_group_link, 1729 next); 1730 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1731 struct pnv_ioda_pe, table_group); 1732 __be64 __iomem *invalidate = rm ? 1733 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1734 pe->phb->ioda.tce_inval_reg; 1735 unsigned long start, end, inc; 1736 const unsigned shift = tbl->it_page_shift; 1737 1738 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); 1739 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + 1740 npages - 1); 1741 1742 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 1743 if (tbl->it_busno) { 1744 start <<= shift; 1745 end <<= shift; 1746 inc = 128ull << shift; 1747 start |= tbl->it_busno; 1748 end |= tbl->it_busno; 1749 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 1750 /* p7ioc-style invalidation, 2 TCEs per write */ 1751 start |= (1ull << 63); 1752 end |= (1ull << 63); 1753 inc = 16; 1754 } else { 1755 /* Default (older HW) */ 1756 inc = 128; 1757 } 1758 1759 end |= inc - 1; /* round up end to be different than start */ 1760 1761 mb(); /* Ensure above stores are visible */ 1762 while (start <= end) { 1763 if (rm) 1764 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1765 else 1766 __raw_writeq(cpu_to_be64(start), invalidate); 1767 start += inc; 1768 } 1769 1770 /* 1771 * The iommu layer will do another mb() for us on build() 1772 * and we don't care on free() 1773 */ 1774 } 1775 1776 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 1777 long npages, unsigned long uaddr, 1778 enum dma_data_direction direction, 1779 struct dma_attrs *attrs) 1780 { 1781 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1782 attrs); 1783 1784 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1785 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1786 1787 return ret; 1788 } 1789 1790 #ifdef CONFIG_IOMMU_API 1791 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, 1792 unsigned long *hpa, enum dma_data_direction *direction) 1793 { 1794 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1795 1796 if (!ret && (tbl->it_type & 1797 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1798 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); 1799 1800 return ret; 1801 } 1802 #endif 1803 1804 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 1805 long npages) 1806 { 1807 pnv_tce_free(tbl, index, npages); 1808 1809 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1810 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); 1811 } 1812 1813 static struct iommu_table_ops pnv_ioda1_iommu_ops = { 1814 .set = pnv_ioda1_tce_build, 1815 #ifdef CONFIG_IOMMU_API 1816 .exchange = pnv_ioda1_tce_xchg, 1817 #endif 1818 .clear = pnv_ioda1_tce_free, 1819 .get = pnv_tce_get, 1820 }; 1821 1822 #define TCE_KILL_INVAL_ALL PPC_BIT(0) 1823 #define TCE_KILL_INVAL_PE PPC_BIT(1) 1824 #define TCE_KILL_INVAL_TCE PPC_BIT(2) 1825 1826 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) 1827 { 1828 const unsigned long val = TCE_KILL_INVAL_ALL; 1829 1830 mb(); /* Ensure previous TCE table stores are visible */ 1831 if (rm) 1832 __raw_rm_writeq(cpu_to_be64(val), 1833 (__be64 __iomem *) 1834 phb->ioda.tce_inval_reg_phys); 1835 else 1836 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 1837 } 1838 1839 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) 1840 { 1841 /* 01xb - invalidate TCEs that match the specified PE# */ 1842 unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); 1843 struct pnv_phb *phb = pe->phb; 1844 1845 if (!phb->ioda.tce_inval_reg) 1846 return; 1847 1848 mb(); /* Ensure above stores are visible */ 1849 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); 1850 } 1851 1852 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, 1853 __be64 __iomem *invalidate, unsigned shift, 1854 unsigned long index, unsigned long npages) 1855 { 1856 unsigned long start, end, inc; 1857 1858 /* We'll invalidate DMA address in PE scope */ 1859 start = TCE_KILL_INVAL_TCE; 1860 start |= (pe_number & 0xFF); 1861 end = start; 1862 1863 /* Figure out the start, end and step */ 1864 start |= (index << shift); 1865 end |= ((index + npages - 1) << shift); 1866 inc = (0x1ull << shift); 1867 mb(); 1868 1869 while (start <= end) { 1870 if (rm) 1871 __raw_rm_writeq(cpu_to_be64(start), invalidate); 1872 else 1873 __raw_writeq(cpu_to_be64(start), invalidate); 1874 start += inc; 1875 } 1876 } 1877 1878 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, 1879 unsigned long index, unsigned long npages, bool rm) 1880 { 1881 struct iommu_table_group_link *tgl; 1882 1883 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 1884 struct pnv_ioda_pe *pe = container_of(tgl->table_group, 1885 struct pnv_ioda_pe, table_group); 1886 __be64 __iomem *invalidate = rm ? 1887 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : 1888 pe->phb->ioda.tce_inval_reg; 1889 1890 if (pe->phb->type == PNV_PHB_NPU) { 1891 /* 1892 * The NVLink hardware does not support TCE kill 1893 * per TCE entry so we have to invalidate 1894 * the entire cache for it. 1895 */ 1896 pnv_pci_ioda2_tce_invalidate_entire(pe->phb, rm); 1897 continue; 1898 } 1899 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, 1900 invalidate, tbl->it_page_shift, 1901 index, npages); 1902 } 1903 } 1904 1905 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 1906 long npages, unsigned long uaddr, 1907 enum dma_data_direction direction, 1908 struct dma_attrs *attrs) 1909 { 1910 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, 1911 attrs); 1912 1913 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) 1914 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1915 1916 return ret; 1917 } 1918 1919 #ifdef CONFIG_IOMMU_API 1920 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, 1921 unsigned long *hpa, enum dma_data_direction *direction) 1922 { 1923 long ret = pnv_tce_xchg(tbl, index, hpa, direction); 1924 1925 if (!ret && (tbl->it_type & 1926 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) 1927 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); 1928 1929 return ret; 1930 } 1931 #endif 1932 1933 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 1934 long npages) 1935 { 1936 pnv_tce_free(tbl, index, npages); 1937 1938 if (tbl->it_type & TCE_PCI_SWINV_FREE) 1939 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); 1940 } 1941 1942 static void pnv_ioda2_table_free(struct iommu_table *tbl) 1943 { 1944 pnv_pci_ioda2_table_free_pages(tbl); 1945 iommu_free_table(tbl, "pnv"); 1946 } 1947 1948 static struct iommu_table_ops pnv_ioda2_iommu_ops = { 1949 .set = pnv_ioda2_tce_build, 1950 #ifdef CONFIG_IOMMU_API 1951 .exchange = pnv_ioda2_tce_xchg, 1952 #endif 1953 .clear = pnv_ioda2_tce_free, 1954 .get = pnv_tce_get, 1955 .free = pnv_ioda2_table_free, 1956 }; 1957 1958 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) 1959 { 1960 unsigned int *weight = (unsigned int *)data; 1961 1962 /* This is quite simplistic. The "base" weight of a device 1963 * is 10. 0 means no DMA is to be accounted for it. 1964 */ 1965 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) 1966 return 0; 1967 1968 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || 1969 dev->class == PCI_CLASS_SERIAL_USB_OHCI || 1970 dev->class == PCI_CLASS_SERIAL_USB_EHCI) 1971 *weight += 3; 1972 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) 1973 *weight += 15; 1974 else 1975 *weight += 10; 1976 1977 return 0; 1978 } 1979 1980 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) 1981 { 1982 unsigned int weight = 0; 1983 1984 /* SRIOV VF has same DMA32 weight as its PF */ 1985 #ifdef CONFIG_PCI_IOV 1986 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { 1987 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); 1988 return weight; 1989 } 1990 #endif 1991 1992 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { 1993 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); 1994 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { 1995 struct pci_dev *pdev; 1996 1997 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) 1998 pnv_pci_ioda_dev_dma_weight(pdev, &weight); 1999 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { 2000 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); 2001 } 2002 2003 return weight; 2004 } 2005 2006 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, 2007 struct pnv_ioda_pe *pe) 2008 { 2009 2010 struct page *tce_mem = NULL; 2011 struct iommu_table *tbl; 2012 unsigned int weight, total_weight = 0; 2013 unsigned int tce32_segsz, base, segs, avail, i; 2014 int64_t rc; 2015 void *addr; 2016 2017 /* XXX FIXME: Handle 64-bit only DMA devices */ 2018 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 2019 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 2020 weight = pnv_pci_ioda_pe_dma_weight(pe); 2021 if (!weight) 2022 return; 2023 2024 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, 2025 &total_weight); 2026 segs = (weight * phb->ioda.dma32_count) / total_weight; 2027 if (!segs) 2028 segs = 1; 2029 2030 /* 2031 * Allocate contiguous DMA32 segments. We begin with the expected 2032 * number of segments. With one more attempt, the number of DMA32 2033 * segments to be allocated is decreased by one until one segment 2034 * is allocated successfully. 2035 */ 2036 do { 2037 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { 2038 for (avail = 0, i = base; i < base + segs; i++) { 2039 if (phb->ioda.dma32_segmap[i] == 2040 IODA_INVALID_PE) 2041 avail++; 2042 } 2043 2044 if (avail == segs) 2045 goto found; 2046 } 2047 } while (--segs); 2048 2049 if (!segs) { 2050 pe_warn(pe, "No available DMA32 segments\n"); 2051 return; 2052 } 2053 2054 found: 2055 tbl = pnv_pci_table_alloc(phb->hose->node); 2056 iommu_register_group(&pe->table_group, phb->hose->global_number, 2057 pe->pe_number); 2058 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); 2059 2060 /* Grab a 32-bit TCE table */ 2061 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", 2062 weight, total_weight, base, segs); 2063 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", 2064 base * PNV_IODA1_DMA32_SEGSIZE, 2065 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); 2066 2067 /* XXX Currently, we allocate one big contiguous table for the 2068 * TCEs. We only really need one chunk per 256M of TCE space 2069 * (ie per segment) but that's an optimization for later, it 2070 * requires some added smarts with our get/put_tce implementation 2071 * 2072 * Each TCE page is 4KB in size and each TCE entry occupies 8 2073 * bytes 2074 */ 2075 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); 2076 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, 2077 get_order(tce32_segsz * segs)); 2078 if (!tce_mem) { 2079 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); 2080 goto fail; 2081 } 2082 addr = page_address(tce_mem); 2083 memset(addr, 0, tce32_segsz * segs); 2084 2085 /* Configure HW */ 2086 for (i = 0; i < segs; i++) { 2087 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2088 pe->pe_number, 2089 base + i, 1, 2090 __pa(addr) + tce32_segsz * i, 2091 tce32_segsz, IOMMU_PAGE_SIZE_4K); 2092 if (rc) { 2093 pe_err(pe, " Failed to configure 32-bit TCE table," 2094 " err %ld\n", rc); 2095 goto fail; 2096 } 2097 } 2098 2099 /* Setup DMA32 segment mapping */ 2100 for (i = base; i < base + segs; i++) 2101 phb->ioda.dma32_segmap[i] = pe->pe_number; 2102 2103 /* Setup linux iommu table */ 2104 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, 2105 base * PNV_IODA1_DMA32_SEGSIZE, 2106 IOMMU_PAGE_SHIFT_4K); 2107 2108 /* OPAL variant of P7IOC SW invalidated TCEs */ 2109 if (phb->ioda.tce_inval_reg) 2110 tbl->it_type |= (TCE_PCI_SWINV_CREATE | 2111 TCE_PCI_SWINV_FREE | 2112 TCE_PCI_SWINV_PAIR); 2113 2114 tbl->it_ops = &pnv_ioda1_iommu_ops; 2115 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; 2116 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; 2117 iommu_init_table(tbl, phb->hose->node); 2118 2119 if (pe->flags & PNV_IODA_PE_DEV) { 2120 /* 2121 * Setting table base here only for carrying iommu_group 2122 * further down to let iommu_add_device() do the job. 2123 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2124 */ 2125 set_iommu_table_base(&pe->pdev->dev, tbl); 2126 iommu_add_device(&pe->pdev->dev); 2127 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2128 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2129 2130 return; 2131 fail: 2132 /* XXX Failure: Try to fallback to 64-bit only ? */ 2133 if (tce_mem) 2134 __free_pages(tce_mem, get_order(tce32_segsz * segs)); 2135 if (tbl) { 2136 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); 2137 iommu_free_table(tbl, "pnv"); 2138 } 2139 } 2140 2141 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, 2142 int num, struct iommu_table *tbl) 2143 { 2144 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2145 table_group); 2146 struct pnv_phb *phb = pe->phb; 2147 int64_t rc; 2148 const unsigned long size = tbl->it_indirect_levels ? 2149 tbl->it_level_size : tbl->it_size; 2150 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; 2151 const __u64 win_size = tbl->it_size << tbl->it_page_shift; 2152 2153 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, 2154 start_addr, start_addr + win_size - 1, 2155 IOMMU_PAGE_SIZE(tbl)); 2156 2157 /* 2158 * Map TCE table through TVT. The TVE index is the PE number 2159 * shifted by 1 bit for 32-bits DMA space. 2160 */ 2161 rc = opal_pci_map_pe_dma_window(phb->opal_id, 2162 pe->pe_number, 2163 (pe->pe_number << 1) + num, 2164 tbl->it_indirect_levels + 1, 2165 __pa(tbl->it_base), 2166 size << 3, 2167 IOMMU_PAGE_SIZE(tbl)); 2168 if (rc) { 2169 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); 2170 return rc; 2171 } 2172 2173 pnv_pci_link_table_and_group(phb->hose->node, num, 2174 tbl, &pe->table_group); 2175 pnv_pci_ioda2_tce_invalidate_pe(pe); 2176 2177 return 0; 2178 } 2179 2180 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) 2181 { 2182 uint16_t window_id = (pe->pe_number << 1 ) + 1; 2183 int64_t rc; 2184 2185 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); 2186 if (enable) { 2187 phys_addr_t top = memblock_end_of_DRAM(); 2188 2189 top = roundup_pow_of_two(top); 2190 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2191 pe->pe_number, 2192 window_id, 2193 pe->tce_bypass_base, 2194 top); 2195 } else { 2196 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, 2197 pe->pe_number, 2198 window_id, 2199 pe->tce_bypass_base, 2200 0); 2201 } 2202 if (rc) 2203 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); 2204 else 2205 pe->tce_bypass_enabled = enable; 2206 } 2207 2208 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2209 __u32 page_shift, __u64 window_size, __u32 levels, 2210 struct iommu_table *tbl); 2211 2212 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, 2213 int num, __u32 page_shift, __u64 window_size, __u32 levels, 2214 struct iommu_table **ptbl) 2215 { 2216 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2217 table_group); 2218 int nid = pe->phb->hose->node; 2219 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; 2220 long ret; 2221 struct iommu_table *tbl; 2222 2223 tbl = pnv_pci_table_alloc(nid); 2224 if (!tbl) 2225 return -ENOMEM; 2226 2227 ret = pnv_pci_ioda2_table_alloc_pages(nid, 2228 bus_offset, page_shift, window_size, 2229 levels, tbl); 2230 if (ret) { 2231 iommu_free_table(tbl, "pnv"); 2232 return ret; 2233 } 2234 2235 tbl->it_ops = &pnv_ioda2_iommu_ops; 2236 if (pe->phb->ioda.tce_inval_reg) 2237 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2238 2239 *ptbl = tbl; 2240 2241 return 0; 2242 } 2243 2244 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) 2245 { 2246 struct iommu_table *tbl = NULL; 2247 long rc; 2248 2249 /* 2250 * crashkernel= specifies the kdump kernel's maximum memory at 2251 * some offset and there is no guaranteed the result is a power 2252 * of 2, which will cause errors later. 2253 */ 2254 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); 2255 2256 /* 2257 * In memory constrained environments, e.g. kdump kernel, the 2258 * DMA window can be larger than available memory, which will 2259 * cause errors later. 2260 */ 2261 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); 2262 2263 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, 2264 IOMMU_PAGE_SHIFT_4K, 2265 window_size, 2266 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); 2267 if (rc) { 2268 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", 2269 rc); 2270 return rc; 2271 } 2272 2273 iommu_init_table(tbl, pe->phb->hose->node); 2274 2275 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); 2276 if (rc) { 2277 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", 2278 rc); 2279 pnv_ioda2_table_free(tbl); 2280 return rc; 2281 } 2282 2283 if (!pnv_iommu_bypass_disabled) 2284 pnv_pci_ioda2_set_bypass(pe, true); 2285 2286 /* OPAL variant of PHB3 invalidated TCEs */ 2287 if (pe->phb->ioda.tce_inval_reg) 2288 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 2289 2290 /* 2291 * Setting table base here only for carrying iommu_group 2292 * further down to let iommu_add_device() do the job. 2293 * pnv_pci_ioda_dma_dev_setup will override it later anyway. 2294 */ 2295 if (pe->flags & PNV_IODA_PE_DEV) 2296 set_iommu_table_base(&pe->pdev->dev, tbl); 2297 2298 return 0; 2299 } 2300 2301 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) 2302 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, 2303 int num) 2304 { 2305 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2306 table_group); 2307 struct pnv_phb *phb = pe->phb; 2308 long ret; 2309 2310 pe_info(pe, "Removing DMA window #%d\n", num); 2311 2312 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 2313 (pe->pe_number << 1) + num, 2314 0/* levels */, 0/* table address */, 2315 0/* table size */, 0/* page size */); 2316 if (ret) 2317 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); 2318 else 2319 pnv_pci_ioda2_tce_invalidate_pe(pe); 2320 2321 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 2322 2323 return ret; 2324 } 2325 #endif 2326 2327 #ifdef CONFIG_IOMMU_API 2328 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2329 __u64 window_size, __u32 levels) 2330 { 2331 unsigned long bytes = 0; 2332 const unsigned window_shift = ilog2(window_size); 2333 unsigned entries_shift = window_shift - page_shift; 2334 unsigned table_shift = entries_shift + 3; 2335 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); 2336 unsigned long direct_table_size; 2337 2338 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || 2339 (window_size > memory_hotplug_max()) || 2340 !is_power_of_2(window_size)) 2341 return 0; 2342 2343 /* Calculate a direct table size from window_size and levels */ 2344 entries_shift = (entries_shift + levels - 1) / levels; 2345 table_shift = entries_shift + 3; 2346 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); 2347 direct_table_size = 1UL << table_shift; 2348 2349 for ( ; levels; --levels) { 2350 bytes += _ALIGN_UP(tce_table_size, direct_table_size); 2351 2352 tce_table_size /= direct_table_size; 2353 tce_table_size <<= 3; 2354 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); 2355 } 2356 2357 return bytes; 2358 } 2359 2360 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) 2361 { 2362 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2363 table_group); 2364 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ 2365 struct iommu_table *tbl = pe->table_group.tables[0]; 2366 2367 pnv_pci_ioda2_set_bypass(pe, false); 2368 pnv_pci_ioda2_unset_window(&pe->table_group, 0); 2369 pnv_ioda2_table_free(tbl); 2370 } 2371 2372 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) 2373 { 2374 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, 2375 table_group); 2376 2377 pnv_pci_ioda2_setup_default_config(pe); 2378 } 2379 2380 static struct iommu_table_group_ops pnv_pci_ioda2_ops = { 2381 .get_table_size = pnv_pci_ioda2_get_table_size, 2382 .create_table = pnv_pci_ioda2_create_table, 2383 .set_window = pnv_pci_ioda2_set_window, 2384 .unset_window = pnv_pci_ioda2_unset_window, 2385 .take_ownership = pnv_ioda2_take_ownership, 2386 .release_ownership = pnv_ioda2_release_ownership, 2387 }; 2388 2389 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) 2390 { 2391 struct pci_controller *hose; 2392 struct pnv_phb *phb; 2393 struct pnv_ioda_pe **ptmppe = opaque; 2394 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); 2395 struct pci_dn *pdn = pci_get_pdn(pdev); 2396 2397 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2398 return 0; 2399 2400 hose = pci_bus_to_host(pdev->bus); 2401 phb = hose->private_data; 2402 if (phb->type != PNV_PHB_NPU) 2403 return 0; 2404 2405 *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; 2406 2407 return 1; 2408 } 2409 2410 /* 2411 * This returns PE of associated NPU. 2412 * This assumes that NPU is in the same IOMMU group with GPU and there is 2413 * no other PEs. 2414 */ 2415 static struct pnv_ioda_pe *gpe_table_group_to_npe( 2416 struct iommu_table_group *table_group) 2417 { 2418 struct pnv_ioda_pe *npe = NULL; 2419 int ret = iommu_group_for_each_dev(table_group->group, &npe, 2420 gpe_table_group_to_npe_cb); 2421 2422 BUG_ON(!ret || !npe); 2423 2424 return npe; 2425 } 2426 2427 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, 2428 int num, struct iommu_table *tbl) 2429 { 2430 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); 2431 2432 if (ret) 2433 return ret; 2434 2435 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); 2436 if (ret) 2437 pnv_pci_ioda2_unset_window(table_group, num); 2438 2439 return ret; 2440 } 2441 2442 static long pnv_pci_ioda2_npu_unset_window( 2443 struct iommu_table_group *table_group, 2444 int num) 2445 { 2446 long ret = pnv_pci_ioda2_unset_window(table_group, num); 2447 2448 if (ret) 2449 return ret; 2450 2451 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); 2452 } 2453 2454 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) 2455 { 2456 /* 2457 * Detach NPU first as pnv_ioda2_take_ownership() will destroy 2458 * the iommu_table if 32bit DMA is enabled. 2459 */ 2460 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); 2461 pnv_ioda2_take_ownership(table_group); 2462 } 2463 2464 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { 2465 .get_table_size = pnv_pci_ioda2_get_table_size, 2466 .create_table = pnv_pci_ioda2_create_table, 2467 .set_window = pnv_pci_ioda2_npu_set_window, 2468 .unset_window = pnv_pci_ioda2_npu_unset_window, 2469 .take_ownership = pnv_ioda2_npu_take_ownership, 2470 .release_ownership = pnv_ioda2_release_ownership, 2471 }; 2472 2473 static void pnv_pci_ioda_setup_iommu_api(void) 2474 { 2475 struct pci_controller *hose, *tmp; 2476 struct pnv_phb *phb; 2477 struct pnv_ioda_pe *pe, *gpe; 2478 2479 /* 2480 * Now we have all PHBs discovered, time to add NPU devices to 2481 * the corresponding IOMMU groups. 2482 */ 2483 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 2484 phb = hose->private_data; 2485 2486 if (phb->type != PNV_PHB_NPU) 2487 continue; 2488 2489 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 2490 gpe = pnv_pci_npu_setup_iommu(pe); 2491 if (gpe) 2492 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; 2493 } 2494 } 2495 } 2496 #else /* !CONFIG_IOMMU_API */ 2497 static void pnv_pci_ioda_setup_iommu_api(void) { }; 2498 #endif 2499 2500 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) 2501 { 2502 const __be64 *swinvp; 2503 2504 /* OPAL variant of PHB3 invalidated TCEs */ 2505 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); 2506 if (!swinvp) 2507 return; 2508 2509 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); 2510 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); 2511 } 2512 2513 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, 2514 unsigned levels, unsigned long limit, 2515 unsigned long *current_offset, unsigned long *total_allocated) 2516 { 2517 struct page *tce_mem = NULL; 2518 __be64 *addr, *tmp; 2519 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; 2520 unsigned long allocated = 1UL << (order + PAGE_SHIFT); 2521 unsigned entries = 1UL << (shift - 3); 2522 long i; 2523 2524 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); 2525 if (!tce_mem) { 2526 pr_err("Failed to allocate a TCE memory, order=%d\n", order); 2527 return NULL; 2528 } 2529 addr = page_address(tce_mem); 2530 memset(addr, 0, allocated); 2531 *total_allocated += allocated; 2532 2533 --levels; 2534 if (!levels) { 2535 *current_offset += allocated; 2536 return addr; 2537 } 2538 2539 for (i = 0; i < entries; ++i) { 2540 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, 2541 levels, limit, current_offset, total_allocated); 2542 if (!tmp) 2543 break; 2544 2545 addr[i] = cpu_to_be64(__pa(tmp) | 2546 TCE_PCI_READ | TCE_PCI_WRITE); 2547 2548 if (*current_offset >= limit) 2549 break; 2550 } 2551 2552 return addr; 2553 } 2554 2555 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2556 unsigned long size, unsigned level); 2557 2558 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 2559 __u32 page_shift, __u64 window_size, __u32 levels, 2560 struct iommu_table *tbl) 2561 { 2562 void *addr; 2563 unsigned long offset = 0, level_shift, total_allocated = 0; 2564 const unsigned window_shift = ilog2(window_size); 2565 unsigned entries_shift = window_shift - page_shift; 2566 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); 2567 const unsigned long tce_table_size = 1UL << table_shift; 2568 2569 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) 2570 return -EINVAL; 2571 2572 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) 2573 return -EINVAL; 2574 2575 /* Adjust direct table size from window_size and levels */ 2576 entries_shift = (entries_shift + levels - 1) / levels; 2577 level_shift = entries_shift + 3; 2578 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); 2579 2580 /* Allocate TCE table */ 2581 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, 2582 levels, tce_table_size, &offset, &total_allocated); 2583 2584 /* addr==NULL means that the first level allocation failed */ 2585 if (!addr) 2586 return -ENOMEM; 2587 2588 /* 2589 * First level was allocated but some lower level failed as 2590 * we did not allocate as much as we wanted, 2591 * release partially allocated table. 2592 */ 2593 if (offset < tce_table_size) { 2594 pnv_pci_ioda2_table_do_free_pages(addr, 2595 1ULL << (level_shift - 3), levels - 1); 2596 return -ENOMEM; 2597 } 2598 2599 /* Setup linux iommu table */ 2600 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, 2601 page_shift); 2602 tbl->it_level_size = 1ULL << (level_shift - 3); 2603 tbl->it_indirect_levels = levels - 1; 2604 tbl->it_allocated_size = total_allocated; 2605 2606 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", 2607 window_size, tce_table_size, bus_offset); 2608 2609 return 0; 2610 } 2611 2612 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, 2613 unsigned long size, unsigned level) 2614 { 2615 const unsigned long addr_ul = (unsigned long) addr & 2616 ~(TCE_PCI_READ | TCE_PCI_WRITE); 2617 2618 if (level) { 2619 long i; 2620 u64 *tmp = (u64 *) addr_ul; 2621 2622 for (i = 0; i < size; ++i) { 2623 unsigned long hpa = be64_to_cpu(tmp[i]); 2624 2625 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) 2626 continue; 2627 2628 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, 2629 level - 1); 2630 } 2631 } 2632 2633 free_pages(addr_ul, get_order(size << 3)); 2634 } 2635 2636 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) 2637 { 2638 const unsigned long size = tbl->it_indirect_levels ? 2639 tbl->it_level_size : tbl->it_size; 2640 2641 if (!tbl->it_size) 2642 return; 2643 2644 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, 2645 tbl->it_indirect_levels); 2646 } 2647 2648 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 2649 struct pnv_ioda_pe *pe) 2650 { 2651 int64_t rc; 2652 2653 if (!pnv_pci_ioda_pe_dma_weight(pe)) 2654 return; 2655 2656 /* TVE #1 is selected by PCI address bit 59 */ 2657 pe->tce_bypass_base = 1ull << 59; 2658 2659 iommu_register_group(&pe->table_group, phb->hose->global_number, 2660 pe->pe_number); 2661 2662 /* The PE will reserve all possible 32-bits space */ 2663 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", 2664 phb->ioda.m32_pci_base); 2665 2666 /* Setup linux iommu table */ 2667 pe->table_group.tce32_start = 0; 2668 pe->table_group.tce32_size = phb->ioda.m32_pci_base; 2669 pe->table_group.max_dynamic_windows_supported = 2670 IOMMU_TABLE_GROUP_MAX_TABLES; 2671 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; 2672 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; 2673 #ifdef CONFIG_IOMMU_API 2674 pe->table_group.ops = &pnv_pci_ioda2_ops; 2675 #endif 2676 2677 rc = pnv_pci_ioda2_setup_default_config(pe); 2678 if (rc) 2679 return; 2680 2681 if (pe->flags & PNV_IODA_PE_DEV) 2682 iommu_add_device(&pe->pdev->dev); 2683 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 2684 pnv_ioda_setup_bus_dma(pe, pe->pbus); 2685 } 2686 2687 #ifdef CONFIG_PCI_MSI 2688 static void pnv_ioda2_msi_eoi(struct irq_data *d) 2689 { 2690 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 2691 struct irq_chip *chip = irq_data_get_irq_chip(d); 2692 struct pnv_phb *phb = container_of(chip, struct pnv_phb, 2693 ioda.irq_chip); 2694 int64_t rc; 2695 2696 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); 2697 WARN_ON_ONCE(rc); 2698 2699 icp_native_eoi(d); 2700 } 2701 2702 2703 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 2704 { 2705 struct irq_data *idata; 2706 struct irq_chip *ichip; 2707 2708 if (phb->type != PNV_PHB_IODA2) 2709 return; 2710 2711 if (!phb->ioda.irq_chip_init) { 2712 /* 2713 * First time we setup an MSI IRQ, we need to setup the 2714 * corresponding IRQ chip to route correctly. 2715 */ 2716 idata = irq_get_irq_data(virq); 2717 ichip = irq_data_get_irq_chip(idata); 2718 phb->ioda.irq_chip_init = 1; 2719 phb->ioda.irq_chip = *ichip; 2720 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; 2721 } 2722 irq_set_chip(virq, &phb->ioda.irq_chip); 2723 } 2724 2725 #ifdef CONFIG_CXL_BASE 2726 2727 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 2728 { 2729 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2730 2731 return of_node_get(hose->dn); 2732 } 2733 EXPORT_SYMBOL(pnv_pci_get_phb_node); 2734 2735 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 2736 { 2737 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2738 struct pnv_phb *phb = hose->private_data; 2739 struct pnv_ioda_pe *pe; 2740 int rc; 2741 2742 pe = pnv_ioda_get_pe(dev); 2743 if (!pe) 2744 return -ENODEV; 2745 2746 pe_info(pe, "Switching PHB to CXL\n"); 2747 2748 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 2749 if (rc == OPAL_UNSUPPORTED) 2750 dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n"); 2751 else if (rc) 2752 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 2753 2754 return rc; 2755 } 2756 EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 2757 2758 /* Find PHB for cxl dev and allocate MSI hwirqs? 2759 * Returns the absolute hardware IRQ number 2760 */ 2761 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 2762 { 2763 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2764 struct pnv_phb *phb = hose->private_data; 2765 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 2766 2767 if (hwirq < 0) { 2768 dev_warn(&dev->dev, "Failed to find a free MSI\n"); 2769 return -ENOSPC; 2770 } 2771 2772 return phb->msi_base + hwirq; 2773 } 2774 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 2775 2776 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 2777 { 2778 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2779 struct pnv_phb *phb = hose->private_data; 2780 2781 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 2782 } 2783 EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 2784 2785 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 2786 struct pci_dev *dev) 2787 { 2788 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2789 struct pnv_phb *phb = hose->private_data; 2790 int i, hwirq; 2791 2792 for (i = 1; i < CXL_IRQ_RANGES; i++) { 2793 if (!irqs->range[i]) 2794 continue; 2795 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 2796 i, irqs->offset[i], 2797 irqs->range[i]); 2798 hwirq = irqs->offset[i] - phb->msi_base; 2799 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 2800 irqs->range[i]); 2801 } 2802 } 2803 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 2804 2805 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 2806 struct pci_dev *dev, int num) 2807 { 2808 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2809 struct pnv_phb *phb = hose->private_data; 2810 int i, hwirq, try; 2811 2812 memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 2813 2814 /* 0 is reserved for the multiplexed PSL DSI interrupt */ 2815 for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 2816 try = num; 2817 while (try) { 2818 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 2819 if (hwirq >= 0) 2820 break; 2821 try /= 2; 2822 } 2823 if (!try) 2824 goto fail; 2825 2826 irqs->offset[i] = phb->msi_base + hwirq; 2827 irqs->range[i] = try; 2828 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 2829 i, irqs->offset[i], irqs->range[i]); 2830 num -= try; 2831 } 2832 if (num) 2833 goto fail; 2834 2835 return 0; 2836 fail: 2837 pnv_cxl_release_hwirq_ranges(irqs, dev); 2838 return -ENOSPC; 2839 } 2840 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 2841 2842 int pnv_cxl_get_irq_count(struct pci_dev *dev) 2843 { 2844 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2845 struct pnv_phb *phb = hose->private_data; 2846 2847 return phb->msi_bmp.irq_count; 2848 } 2849 EXPORT_SYMBOL(pnv_cxl_get_irq_count); 2850 2851 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 2852 unsigned int virq) 2853 { 2854 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2855 struct pnv_phb *phb = hose->private_data; 2856 unsigned int xive_num = hwirq - phb->msi_base; 2857 struct pnv_ioda_pe *pe; 2858 int rc; 2859 2860 if (!(pe = pnv_ioda_get_pe(dev))) 2861 return -ENODEV; 2862 2863 /* Assign XIVE to PE */ 2864 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2865 if (rc) { 2866 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 2867 "hwirq 0x%x XIVE 0x%x PE\n", 2868 pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 2869 return -EIO; 2870 } 2871 set_msi_irq_chip(phb, virq); 2872 2873 return 0; 2874 } 2875 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 2876 #endif 2877 2878 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 2879 unsigned int hwirq, unsigned int virq, 2880 unsigned int is_64, struct msi_msg *msg) 2881 { 2882 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); 2883 unsigned int xive_num = hwirq - phb->msi_base; 2884 __be32 data; 2885 int rc; 2886 2887 /* No PE assigned ? bail out ... no MSI for you ! */ 2888 if (pe == NULL) 2889 return -ENXIO; 2890 2891 /* Check if we have an MVE */ 2892 if (pe->mve_number < 0) 2893 return -ENXIO; 2894 2895 /* Force 32-bit MSI on some broken devices */ 2896 if (dev->no_64bit_msi) 2897 is_64 = 0; 2898 2899 /* Assign XIVE to PE */ 2900 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 2901 if (rc) { 2902 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", 2903 pci_name(dev), rc, xive_num); 2904 return -EIO; 2905 } 2906 2907 if (is_64) { 2908 __be64 addr64; 2909 2910 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, 2911 &addr64, &data); 2912 if (rc) { 2913 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", 2914 pci_name(dev), rc); 2915 return -EIO; 2916 } 2917 msg->address_hi = be64_to_cpu(addr64) >> 32; 2918 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; 2919 } else { 2920 __be32 addr32; 2921 2922 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, 2923 &addr32, &data); 2924 if (rc) { 2925 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", 2926 pci_name(dev), rc); 2927 return -EIO; 2928 } 2929 msg->address_hi = 0; 2930 msg->address_lo = be32_to_cpu(addr32); 2931 } 2932 msg->data = be32_to_cpu(data); 2933 2934 set_msi_irq_chip(phb, virq); 2935 2936 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," 2937 " address=%x_%08x data=%x PE# %d\n", 2938 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, 2939 msg->address_hi, msg->address_lo, data, pe->pe_number); 2940 2941 return 0; 2942 } 2943 2944 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 2945 { 2946 unsigned int count; 2947 const __be32 *prop = of_get_property(phb->hose->dn, 2948 "ibm,opal-msi-ranges", NULL); 2949 if (!prop) { 2950 /* BML Fallback */ 2951 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); 2952 } 2953 if (!prop) 2954 return; 2955 2956 phb->msi_base = be32_to_cpup(prop); 2957 count = be32_to_cpup(prop + 1); 2958 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 2959 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 2960 phb->hose->global_number); 2961 return; 2962 } 2963 2964 phb->msi_setup = pnv_pci_ioda_msi_setup; 2965 phb->msi32_support = 1; 2966 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 2967 count, phb->msi_base); 2968 } 2969 #else 2970 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2971 #endif /* CONFIG_PCI_MSI */ 2972 2973 #ifdef CONFIG_PCI_IOV 2974 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 2975 { 2976 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 2977 struct pnv_phb *phb = hose->private_data; 2978 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 2979 struct resource *res; 2980 int i; 2981 resource_size_t size, total_vf_bar_sz; 2982 struct pci_dn *pdn; 2983 int mul, total_vfs; 2984 2985 if (!pdev->is_physfn || pdev->is_added) 2986 return; 2987 2988 pdn = pci_get_pdn(pdev); 2989 pdn->vfs_expanded = 0; 2990 pdn->m64_single_mode = false; 2991 2992 total_vfs = pci_sriov_get_totalvfs(pdev); 2993 mul = phb->ioda.total_pe_num; 2994 total_vf_bar_sz = 0; 2995 2996 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 2997 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 2998 if (!res->flags || res->parent) 2999 continue; 3000 if (!pnv_pci_is_mem_pref_64(res->flags)) { 3001 dev_warn(&pdev->dev, "Don't support SR-IOV with" 3002 " non M64 VF BAR%d: %pR. \n", 3003 i, res); 3004 goto truncate_iov; 3005 } 3006 3007 total_vf_bar_sz += pci_iov_resource_size(pdev, 3008 i + PCI_IOV_RESOURCES); 3009 3010 /* 3011 * If bigger than quarter of M64 segment size, just round up 3012 * power of two. 3013 * 3014 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 3015 * with other devices, IOV BAR size is expanded to be 3016 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 3017 * segment size , the expanded size would equal to half of the 3018 * whole M64 space size, which will exhaust the M64 Space and 3019 * limit the system flexibility. This is a design decision to 3020 * set the boundary to quarter of the M64 segment size. 3021 */ 3022 if (total_vf_bar_sz > gate) { 3023 mul = roundup_pow_of_two(total_vfs); 3024 dev_info(&pdev->dev, 3025 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 3026 total_vf_bar_sz, gate, mul); 3027 pdn->m64_single_mode = true; 3028 break; 3029 } 3030 } 3031 3032 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3033 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3034 if (!res->flags || res->parent) 3035 continue; 3036 3037 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 3038 /* 3039 * On PHB3, the minimum size alignment of M64 BAR in single 3040 * mode is 32MB. 3041 */ 3042 if (pdn->m64_single_mode && (size < SZ_32M)) 3043 goto truncate_iov; 3044 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 3045 res->end = res->start + size * mul - 1; 3046 dev_dbg(&pdev->dev, " %pR\n", res); 3047 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 3048 i, res, mul); 3049 } 3050 pdn->vfs_expanded = mul; 3051 3052 return; 3053 3054 truncate_iov: 3055 /* To save MMIO space, IOV BAR is truncated. */ 3056 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 3057 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 3058 res->flags = 0; 3059 res->end = res->start - 1; 3060 } 3061 } 3062 #endif /* CONFIG_PCI_IOV */ 3063 3064 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, 3065 struct resource *res) 3066 { 3067 struct pnv_phb *phb = pe->phb; 3068 struct pci_bus_region region; 3069 int index; 3070 int64_t rc; 3071 3072 if (!res || !res->flags || res->start > res->end) 3073 return; 3074 3075 if (res->flags & IORESOURCE_IO) { 3076 region.start = res->start - phb->ioda.io_pci_base; 3077 region.end = res->end - phb->ioda.io_pci_base; 3078 index = region.start / phb->ioda.io_segsize; 3079 3080 while (index < phb->ioda.total_pe_num && 3081 region.start <= region.end) { 3082 phb->ioda.io_segmap[index] = pe->pe_number; 3083 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3084 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); 3085 if (rc != OPAL_SUCCESS) { 3086 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", 3087 __func__, rc, index, pe->pe_number); 3088 break; 3089 } 3090 3091 region.start += phb->ioda.io_segsize; 3092 index++; 3093 } 3094 } else if ((res->flags & IORESOURCE_MEM) && 3095 !pnv_pci_is_mem_pref_64(res->flags)) { 3096 region.start = res->start - 3097 phb->hose->mem_offset[0] - 3098 phb->ioda.m32_pci_base; 3099 region.end = res->end - 3100 phb->hose->mem_offset[0] - 3101 phb->ioda.m32_pci_base; 3102 index = region.start / phb->ioda.m32_segsize; 3103 3104 while (index < phb->ioda.total_pe_num && 3105 region.start <= region.end) { 3106 phb->ioda.m32_segmap[index] = pe->pe_number; 3107 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3108 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); 3109 if (rc != OPAL_SUCCESS) { 3110 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", 3111 __func__, rc, index, pe->pe_number); 3112 break; 3113 } 3114 3115 region.start += phb->ioda.m32_segsize; 3116 index++; 3117 } 3118 } 3119 } 3120 3121 /* 3122 * This function is supposed to be called on basis of PE from top 3123 * to bottom style. So the the I/O or MMIO segment assigned to 3124 * parent PE could be overrided by its child PEs if necessary. 3125 */ 3126 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) 3127 { 3128 struct pci_dev *pdev; 3129 int i; 3130 3131 /* 3132 * NOTE: We only care PCI bus based PE for now. For PCI 3133 * device based PE, for example SRIOV sensitive VF should 3134 * be figured out later. 3135 */ 3136 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); 3137 3138 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { 3139 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 3140 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); 3141 3142 /* 3143 * If the PE contains all subordinate PCI buses, the 3144 * windows of the child bridges should be mapped to 3145 * the PE as well. 3146 */ 3147 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) 3148 continue; 3149 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 3150 pnv_ioda_setup_pe_res(pe, 3151 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); 3152 } 3153 } 3154 3155 static void pnv_pci_ioda_create_dbgfs(void) 3156 { 3157 #ifdef CONFIG_DEBUG_FS 3158 struct pci_controller *hose, *tmp; 3159 struct pnv_phb *phb; 3160 char name[16]; 3161 3162 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 3163 phb = hose->private_data; 3164 3165 /* Notify initialization of PHB done */ 3166 phb->initialized = 1; 3167 3168 sprintf(name, "PCI%04x", hose->global_number); 3169 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); 3170 if (!phb->dbgfs) 3171 pr_warning("%s: Error on creating debugfs on PHB#%x\n", 3172 __func__, hose->global_number); 3173 } 3174 #endif /* CONFIG_DEBUG_FS */ 3175 } 3176 3177 static void pnv_pci_ioda_fixup(void) 3178 { 3179 pnv_pci_ioda_setup_PEs(); 3180 pnv_pci_ioda_setup_iommu_api(); 3181 pnv_pci_ioda_create_dbgfs(); 3182 3183 #ifdef CONFIG_EEH 3184 eeh_init(); 3185 eeh_addr_cache_build(); 3186 #endif 3187 } 3188 3189 /* 3190 * Returns the alignment for I/O or memory windows for P2P 3191 * bridges. That actually depends on how PEs are segmented. 3192 * For now, we return I/O or M32 segment size for PE sensitive 3193 * P2P bridges. Otherwise, the default values (4KiB for I/O, 3194 * 1MiB for memory) will be returned. 3195 * 3196 * The current PCI bus might be put into one PE, which was 3197 * create against the parent PCI bridge. For that case, we 3198 * needn't enlarge the alignment so that we can save some 3199 * resources. 3200 */ 3201 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, 3202 unsigned long type) 3203 { 3204 struct pci_dev *bridge; 3205 struct pci_controller *hose = pci_bus_to_host(bus); 3206 struct pnv_phb *phb = hose->private_data; 3207 int num_pci_bridges = 0; 3208 3209 bridge = bus->self; 3210 while (bridge) { 3211 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { 3212 num_pci_bridges++; 3213 if (num_pci_bridges >= 2) 3214 return 1; 3215 } 3216 3217 bridge = bridge->bus->self; 3218 } 3219 3220 /* We fail back to M32 if M64 isn't supported */ 3221 if (phb->ioda.m64_segsize && 3222 pnv_pci_is_mem_pref_64(type)) 3223 return phb->ioda.m64_segsize; 3224 if (type & IORESOURCE_MEM) 3225 return phb->ioda.m32_segsize; 3226 3227 return phb->ioda.io_segsize; 3228 } 3229 3230 /* 3231 * We are updating root port or the upstream port of the 3232 * bridge behind the root port with PHB's windows in order 3233 * to accommodate the changes on required resources during 3234 * PCI (slot) hotplug, which is connected to either root 3235 * port or the downstream ports of PCIe switch behind the 3236 * root port. 3237 */ 3238 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, 3239 unsigned long type) 3240 { 3241 struct pci_controller *hose = pci_bus_to_host(bus); 3242 struct pnv_phb *phb = hose->private_data; 3243 struct pci_dev *bridge = bus->self; 3244 struct resource *r, *w; 3245 bool msi_region = false; 3246 int i; 3247 3248 /* Check if we need apply fixup to the bridge's windows */ 3249 if (!pci_is_root_bus(bridge->bus) && 3250 !pci_is_root_bus(bridge->bus->self->bus)) 3251 return; 3252 3253 /* Fixup the resources */ 3254 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 3255 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; 3256 if (!r->flags || !r->parent) 3257 continue; 3258 3259 w = NULL; 3260 if (r->flags & type & IORESOURCE_IO) 3261 w = &hose->io_resource; 3262 else if (pnv_pci_is_mem_pref_64(r->flags) && 3263 (type & IORESOURCE_PREFETCH) && 3264 phb->ioda.m64_segsize) 3265 w = &hose->mem_resources[1]; 3266 else if (r->flags & type & IORESOURCE_MEM) { 3267 w = &hose->mem_resources[0]; 3268 msi_region = true; 3269 } 3270 3271 r->start = w->start; 3272 r->end = w->end; 3273 3274 /* The 64KB 32-bits MSI region shouldn't be included in 3275 * the 32-bits bridge window. Otherwise, we can see strange 3276 * issues. One of them is EEH error observed on Garrison. 3277 * 3278 * Exclude top 1MB region which is the minimal alignment of 3279 * 32-bits bridge window. 3280 */ 3281 if (msi_region) { 3282 r->end += 0x10000; 3283 r->end -= 0x100000; 3284 } 3285 } 3286 } 3287 3288 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) 3289 { 3290 struct pci_controller *hose = pci_bus_to_host(bus); 3291 struct pnv_phb *phb = hose->private_data; 3292 struct pci_dev *bridge = bus->self; 3293 struct pnv_ioda_pe *pe; 3294 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); 3295 3296 /* Extend bridge's windows if necessary */ 3297 pnv_pci_fixup_bridge_resources(bus, type); 3298 3299 /* The PE for root bus should be realized before any one else */ 3300 if (!phb->ioda.root_pe_populated) { 3301 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); 3302 if (pe) { 3303 phb->ioda.root_pe_idx = pe->pe_number; 3304 phb->ioda.root_pe_populated = true; 3305 } 3306 } 3307 3308 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ 3309 if (list_empty(&bus->devices)) 3310 return; 3311 3312 /* Reserve PEs according to used M64 resources */ 3313 if (phb->reserve_m64_pe) 3314 phb->reserve_m64_pe(bus, NULL, all); 3315 3316 /* 3317 * Assign PE. We might run here because of partial hotplug. 3318 * For the case, we just pick up the existing PE and should 3319 * not allocate resources again. 3320 */ 3321 pe = pnv_ioda_setup_bus_PE(bus, all); 3322 if (!pe) 3323 return; 3324 3325 pnv_ioda_setup_pe_seg(pe); 3326 switch (phb->type) { 3327 case PNV_PHB_IODA1: 3328 pnv_pci_ioda1_setup_dma_pe(phb, pe); 3329 break; 3330 case PNV_PHB_IODA2: 3331 pnv_pci_ioda2_setup_dma_pe(phb, pe); 3332 break; 3333 default: 3334 pr_warn("%s: No DMA for PHB#%d (type %d)\n", 3335 __func__, phb->hose->global_number, phb->type); 3336 } 3337 } 3338 3339 #ifdef CONFIG_PCI_IOV 3340 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 3341 int resno) 3342 { 3343 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3344 struct pnv_phb *phb = hose->private_data; 3345 struct pci_dn *pdn = pci_get_pdn(pdev); 3346 resource_size_t align; 3347 3348 /* 3349 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 3350 * SR-IOV. While from hardware perspective, the range mapped by M64 3351 * BAR should be size aligned. 3352 * 3353 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 3354 * powernv-specific hardware restriction is gone. But if just use the 3355 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 3356 * in one segment of M64 #15, which introduces the PE conflict between 3357 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 3358 * m64_segsize. 3359 * 3360 * This function returns the total IOV BAR size if M64 BAR is in 3361 * Shared PE mode or just VF BAR size if not. 3362 * If the M64 BAR is in Single PE mode, return the VF BAR size or 3363 * M64 segment size if IOV BAR size is less. 3364 */ 3365 align = pci_iov_resource_size(pdev, resno); 3366 if (!pdn->vfs_expanded) 3367 return align; 3368 if (pdn->m64_single_mode) 3369 return max(align, (resource_size_t)phb->ioda.m64_segsize); 3370 3371 return pdn->vfs_expanded * align; 3372 } 3373 #endif /* CONFIG_PCI_IOV */ 3374 3375 /* Prevent enabling devices for which we couldn't properly 3376 * assign a PE 3377 */ 3378 static bool pnv_pci_enable_device_hook(struct pci_dev *dev) 3379 { 3380 struct pci_controller *hose = pci_bus_to_host(dev->bus); 3381 struct pnv_phb *phb = hose->private_data; 3382 struct pci_dn *pdn; 3383 3384 /* The function is probably called while the PEs have 3385 * not be created yet. For example, resource reassignment 3386 * during PCI probe period. We just skip the check if 3387 * PEs isn't ready. 3388 */ 3389 if (!phb->initialized) 3390 return true; 3391 3392 pdn = pci_get_pdn(dev); 3393 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3394 return false; 3395 3396 return true; 3397 } 3398 3399 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, 3400 int num) 3401 { 3402 struct pnv_ioda_pe *pe = container_of(table_group, 3403 struct pnv_ioda_pe, table_group); 3404 struct pnv_phb *phb = pe->phb; 3405 unsigned int idx; 3406 long rc; 3407 3408 pe_info(pe, "Removing DMA window #%d\n", num); 3409 for (idx = 0; idx < phb->ioda.dma32_count; idx++) { 3410 if (phb->ioda.dma32_segmap[idx] != pe->pe_number) 3411 continue; 3412 3413 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, 3414 idx, 0, 0ul, 0ul, 0ul); 3415 if (rc != OPAL_SUCCESS) { 3416 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", 3417 rc, idx); 3418 return rc; 3419 } 3420 3421 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; 3422 } 3423 3424 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); 3425 return OPAL_SUCCESS; 3426 } 3427 3428 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) 3429 { 3430 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3431 struct iommu_table *tbl = pe->table_group.tables[0]; 3432 int64_t rc; 3433 3434 if (!weight) 3435 return; 3436 3437 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); 3438 if (rc != OPAL_SUCCESS) 3439 return; 3440 3441 pnv_pci_ioda1_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); 3442 if (pe->table_group.group) { 3443 iommu_group_put(pe->table_group.group); 3444 WARN_ON(pe->table_group.group); 3445 } 3446 3447 free_pages(tbl->it_base, get_order(tbl->it_size << 3)); 3448 iommu_free_table(tbl, "pnv"); 3449 } 3450 3451 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) 3452 { 3453 struct iommu_table *tbl = pe->table_group.tables[0]; 3454 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); 3455 #ifdef CONFIG_IOMMU_API 3456 int64_t rc; 3457 #endif 3458 3459 if (!weight) 3460 return; 3461 3462 #ifdef CONFIG_IOMMU_API 3463 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); 3464 if (rc) 3465 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); 3466 #endif 3467 3468 pnv_pci_ioda2_set_bypass(pe, false); 3469 if (pe->table_group.group) { 3470 iommu_group_put(pe->table_group.group); 3471 WARN_ON(pe->table_group.group); 3472 } 3473 3474 pnv_pci_ioda2_table_free_pages(tbl); 3475 iommu_free_table(tbl, "pnv"); 3476 } 3477 3478 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, 3479 unsigned short win, 3480 unsigned int *map) 3481 { 3482 struct pnv_phb *phb = pe->phb; 3483 int idx; 3484 int64_t rc; 3485 3486 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { 3487 if (map[idx] != pe->pe_number) 3488 continue; 3489 3490 if (win == OPAL_M64_WINDOW_TYPE) 3491 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3492 phb->ioda.reserved_pe_idx, win, 3493 idx / PNV_IODA1_M64_SEGS, 3494 idx % PNV_IODA1_M64_SEGS); 3495 else 3496 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 3497 phb->ioda.reserved_pe_idx, win, 0, idx); 3498 3499 if (rc != OPAL_SUCCESS) 3500 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", 3501 rc, win, idx); 3502 3503 map[idx] = IODA_INVALID_PE; 3504 } 3505 } 3506 3507 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) 3508 { 3509 struct pnv_phb *phb = pe->phb; 3510 3511 if (phb->type == PNV_PHB_IODA1) { 3512 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, 3513 phb->ioda.io_segmap); 3514 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3515 phb->ioda.m32_segmap); 3516 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, 3517 phb->ioda.m64_segmap); 3518 } else if (phb->type == PNV_PHB_IODA2) { 3519 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, 3520 phb->ioda.m32_segmap); 3521 } 3522 } 3523 3524 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) 3525 { 3526 struct pnv_phb *phb = pe->phb; 3527 struct pnv_ioda_pe *slave, *tmp; 3528 3529 /* Release slave PEs in compound PE */ 3530 if (pe->flags & PNV_IODA_PE_MASTER) { 3531 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) 3532 pnv_ioda_release_pe(slave); 3533 } 3534 3535 list_del(&pe->list); 3536 switch (phb->type) { 3537 case PNV_PHB_IODA1: 3538 pnv_pci_ioda1_release_pe_dma(pe); 3539 break; 3540 case PNV_PHB_IODA2: 3541 pnv_pci_ioda2_release_pe_dma(pe); 3542 break; 3543 default: 3544 WARN_ON(1); 3545 } 3546 3547 pnv_ioda_release_pe_seg(pe); 3548 pnv_ioda_deconfigure_pe(pe->phb, pe); 3549 pnv_ioda_free_pe(pe); 3550 } 3551 3552 static void pnv_pci_release_device(struct pci_dev *pdev) 3553 { 3554 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 3555 struct pnv_phb *phb = hose->private_data; 3556 struct pci_dn *pdn = pci_get_pdn(pdev); 3557 struct pnv_ioda_pe *pe; 3558 3559 if (pdev->is_virtfn) 3560 return; 3561 3562 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 3563 return; 3564 3565 pe = &phb->ioda.pe_array[pdn->pe_number]; 3566 WARN_ON(--pe->device_count < 0); 3567 if (pe->device_count == 0) 3568 pnv_ioda_release_pe(pe); 3569 } 3570 3571 static void pnv_pci_ioda_shutdown(struct pci_controller *hose) 3572 { 3573 struct pnv_phb *phb = hose->private_data; 3574 3575 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, 3576 OPAL_ASSERT_RESET); 3577 } 3578 3579 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 3580 .dma_dev_setup = pnv_pci_dma_dev_setup, 3581 .dma_bus_setup = pnv_pci_dma_bus_setup, 3582 #ifdef CONFIG_PCI_MSI 3583 .setup_msi_irqs = pnv_setup_msi_irqs, 3584 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3585 #endif 3586 .enable_device_hook = pnv_pci_enable_device_hook, 3587 .release_device = pnv_pci_release_device, 3588 .window_alignment = pnv_pci_window_alignment, 3589 .setup_bridge = pnv_pci_setup_bridge, 3590 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3591 .dma_set_mask = pnv_pci_ioda_dma_set_mask, 3592 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, 3593 .shutdown = pnv_pci_ioda_shutdown, 3594 }; 3595 3596 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) 3597 { 3598 dev_err_once(&npdev->dev, 3599 "%s operation unsupported for NVLink devices\n", 3600 __func__); 3601 return -EPERM; 3602 } 3603 3604 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { 3605 .dma_dev_setup = pnv_pci_dma_dev_setup, 3606 #ifdef CONFIG_PCI_MSI 3607 .setup_msi_irqs = pnv_setup_msi_irqs, 3608 .teardown_msi_irqs = pnv_teardown_msi_irqs, 3609 #endif 3610 .enable_device_hook = pnv_pci_enable_device_hook, 3611 .window_alignment = pnv_pci_window_alignment, 3612 .reset_secondary_bus = pnv_pci_reset_secondary_bus, 3613 .dma_set_mask = pnv_npu_dma_set_mask, 3614 .shutdown = pnv_pci_ioda_shutdown, 3615 }; 3616 3617 static void __init pnv_pci_init_ioda_phb(struct device_node *np, 3618 u64 hub_id, int ioda_type) 3619 { 3620 struct pci_controller *hose; 3621 struct pnv_phb *phb; 3622 unsigned long size, m64map_off, m32map_off, pemap_off; 3623 unsigned long iomap_off = 0, dma32map_off = 0; 3624 const __be64 *prop64; 3625 const __be32 *prop32; 3626 int len; 3627 unsigned int segno; 3628 u64 phb_id; 3629 void *aux; 3630 long rc; 3631 3632 pr_info("Initializing %s PHB (%s)\n", 3633 pnv_phb_names[ioda_type], of_node_full_name(np)); 3634 3635 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 3636 if (!prop64) { 3637 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 3638 return; 3639 } 3640 phb_id = be64_to_cpup(prop64); 3641 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); 3642 3643 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 3644 3645 /* Allocate PCI controller */ 3646 phb->hose = hose = pcibios_alloc_controller(np); 3647 if (!phb->hose) { 3648 pr_err(" Can't allocate PCI controller for %s\n", 3649 np->full_name); 3650 memblock_free(__pa(phb), sizeof(struct pnv_phb)); 3651 return; 3652 } 3653 3654 spin_lock_init(&phb->lock); 3655 prop32 = of_get_property(np, "bus-range", &len); 3656 if (prop32 && len == 8) { 3657 hose->first_busno = be32_to_cpu(prop32[0]); 3658 hose->last_busno = be32_to_cpu(prop32[1]); 3659 } else { 3660 pr_warn(" Broken <bus-range> on %s\n", np->full_name); 3661 hose->first_busno = 0; 3662 hose->last_busno = 0xff; 3663 } 3664 hose->private_data = phb; 3665 phb->hub_id = hub_id; 3666 phb->opal_id = phb_id; 3667 phb->type = ioda_type; 3668 mutex_init(&phb->ioda.pe_alloc_mutex); 3669 3670 /* Detect specific models for error handling */ 3671 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 3672 phb->model = PNV_PHB_MODEL_P7IOC; 3673 else if (of_device_is_compatible(np, "ibm,power8-pciex")) 3674 phb->model = PNV_PHB_MODEL_PHB3; 3675 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) 3676 phb->model = PNV_PHB_MODEL_NPU; 3677 else 3678 phb->model = PNV_PHB_MODEL_UNKNOWN; 3679 3680 /* Parse 32-bit and IO ranges (if any) */ 3681 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); 3682 3683 /* Get registers */ 3684 phb->regs = of_iomap(np, 0); 3685 if (phb->regs == NULL) 3686 pr_err(" Failed to map registers !\n"); 3687 3688 /* Initialize TCE kill register */ 3689 pnv_pci_ioda_setup_opal_tce_kill(phb); 3690 3691 /* Initialize more IODA stuff */ 3692 phb->ioda.total_pe_num = 1; 3693 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); 3694 if (prop32) 3695 phb->ioda.total_pe_num = be32_to_cpup(prop32); 3696 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); 3697 if (prop32) 3698 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); 3699 3700 /* Invalidate RID to PE# mapping */ 3701 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) 3702 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; 3703 3704 /* Parse 64-bit MMIO range */ 3705 pnv_ioda_parse_m64_window(phb); 3706 3707 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); 3708 /* FW Has already off top 64k of M32 space (MSI space) */ 3709 phb->ioda.m32_size += 0x10000; 3710 3711 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; 3712 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; 3713 phb->ioda.io_size = hose->pci_io_size; 3714 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; 3715 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ 3716 3717 /* Calculate how many 32-bit TCE segments we have */ 3718 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3719 PNV_IODA1_DMA32_SEGSIZE; 3720 3721 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ 3722 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, 3723 sizeof(unsigned long)); 3724 m64map_off = size; 3725 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); 3726 m32map_off = size; 3727 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); 3728 if (phb->type == PNV_PHB_IODA1) { 3729 iomap_off = size; 3730 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); 3731 dma32map_off = size; 3732 size += phb->ioda.dma32_count * 3733 sizeof(phb->ioda.dma32_segmap[0]); 3734 } 3735 pemap_off = size; 3736 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); 3737 aux = memblock_virt_alloc(size, 0); 3738 phb->ioda.pe_alloc = aux; 3739 phb->ioda.m64_segmap = aux + m64map_off; 3740 phb->ioda.m32_segmap = aux + m32map_off; 3741 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { 3742 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; 3743 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; 3744 } 3745 if (phb->type == PNV_PHB_IODA1) { 3746 phb->ioda.io_segmap = aux + iomap_off; 3747 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) 3748 phb->ioda.io_segmap[segno] = IODA_INVALID_PE; 3749 3750 phb->ioda.dma32_segmap = aux + dma32map_off; 3751 for (segno = 0; segno < phb->ioda.dma32_count; segno++) 3752 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; 3753 } 3754 phb->ioda.pe_array = aux + pemap_off; 3755 3756 /* 3757 * Choose PE number for root bus, which shouldn't have 3758 * M64 resources consumed by its child devices. To pick 3759 * the PE number adjacent to the reserved one if possible. 3760 */ 3761 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); 3762 if (phb->ioda.reserved_pe_idx == 0) { 3763 phb->ioda.root_pe_idx = 1; 3764 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3765 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { 3766 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; 3767 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); 3768 } else { 3769 phb->ioda.root_pe_idx = IODA_INVALID_PE; 3770 } 3771 3772 INIT_LIST_HEAD(&phb->ioda.pe_list); 3773 mutex_init(&phb->ioda.pe_list_mutex); 3774 3775 /* Calculate how many 32-bit TCE segments we have */ 3776 phb->ioda.dma32_count = phb->ioda.m32_pci_base / 3777 PNV_IODA1_DMA32_SEGSIZE; 3778 3779 #if 0 /* We should really do that ... */ 3780 rc = opal_pci_set_phb_mem_window(opal->phb_id, 3781 window_type, 3782 window_num, 3783 starting_real_address, 3784 starting_pci_address, 3785 segment_size); 3786 #endif 3787 3788 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", 3789 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, 3790 phb->ioda.m32_size, phb->ioda.m32_segsize); 3791 if (phb->ioda.m64_size) 3792 pr_info(" M64: 0x%lx [segment=0x%lx]\n", 3793 phb->ioda.m64_size, phb->ioda.m64_segsize); 3794 if (phb->ioda.io_size) 3795 pr_info(" IO: 0x%x [segment=0x%x]\n", 3796 phb->ioda.io_size, phb->ioda.io_segsize); 3797 3798 3799 phb->hose->ops = &pnv_pci_ops; 3800 phb->get_pe_state = pnv_ioda_get_pe_state; 3801 phb->freeze_pe = pnv_ioda_freeze_pe; 3802 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 3803 3804 /* Setup MSI support */ 3805 pnv_pci_init_ioda_msis(phb); 3806 3807 /* 3808 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here 3809 * to let the PCI core do resource assignment. It's supposed 3810 * that the PCI core will do correct I/O and MMIO alignment 3811 * for the P2P bridge bars so that each PCI bus (excluding 3812 * the child P2P bridges) can form individual PE. 3813 */ 3814 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 3815 3816 if (phb->type == PNV_PHB_NPU) { 3817 hose->controller_ops = pnv_npu_ioda_controller_ops; 3818 } else { 3819 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; 3820 hose->controller_ops = pnv_pci_ioda_controller_ops; 3821 } 3822 3823 #ifdef CONFIG_PCI_IOV 3824 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; 3825 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; 3826 #endif 3827 3828 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 3829 3830 /* Reset IODA tables to a clean state */ 3831 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); 3832 if (rc) 3833 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); 3834 3835 /* If we're running in kdump kerenl, the previous kerenl never 3836 * shutdown PCI devices correctly. We already got IODA table 3837 * cleaned out. So we have to issue PHB reset to stop all PCI 3838 * transactions from previous kerenl. 3839 */ 3840 if (is_kdump_kernel()) { 3841 pr_info(" Issue PHB reset ...\n"); 3842 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 3843 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 3844 } 3845 3846 /* Remove M64 resource if we can't configure it successfully */ 3847 if (!phb->init_m64 || phb->init_m64(phb)) 3848 hose->mem_resources[1].flags = 0; 3849 } 3850 3851 void __init pnv_pci_init_ioda2_phb(struct device_node *np) 3852 { 3853 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 3854 } 3855 3856 void __init pnv_pci_init_npu_phb(struct device_node *np) 3857 { 3858 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); 3859 } 3860 3861 void __init pnv_pci_init_ioda_hub(struct device_node *np) 3862 { 3863 struct device_node *phbn; 3864 const __be64 *prop64; 3865 u64 hub_id; 3866 3867 pr_info("Probing IODA IO-Hub %s\n", np->full_name); 3868 3869 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 3870 if (!prop64) { 3871 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 3872 return; 3873 } 3874 hub_id = be64_to_cpup(prop64); 3875 pr_devel(" HUB-ID : 0x%016llx\n", hub_id); 3876 3877 /* Count child PHBs */ 3878 for_each_child_of_node(np, phbn) { 3879 /* Look for IODA1 PHBs */ 3880 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) 3881 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); 3882 } 3883 } 3884