1 /* 2 * OPAL IMC interface detection driver 3 * Supported on POWERNV platform 4 * 5 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation. 6 * (C) 2017 Anju T Sudhakar, IBM Corporation. 7 * (C) 2017 Hemant K Shaw, IBM Corporation. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or later version. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/platform_device.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/crash_dump.h> 20 #include <asm/opal.h> 21 #include <asm/io.h> 22 #include <asm/imc-pmu.h> 23 #include <asm/cputhreads.h> 24 #include <asm/debugfs.h> 25 26 static struct dentry *imc_debugfs_parent; 27 28 /* Helpers to export imc command and mode via debugfs */ 29 static int imc_mem_get(void *data, u64 *val) 30 { 31 *val = cpu_to_be64(*(u64 *)data); 32 return 0; 33 } 34 35 static int imc_mem_set(void *data, u64 val) 36 { 37 *(u64 *)data = cpu_to_be64(val); 38 return 0; 39 } 40 DEFINE_DEBUGFS_ATTRIBUTE(fops_imc_x64, imc_mem_get, imc_mem_set, "0x%016llx\n"); 41 42 static struct dentry *imc_debugfs_create_x64(const char *name, umode_t mode, 43 struct dentry *parent, u64 *value) 44 { 45 return debugfs_create_file_unsafe(name, mode, parent, 46 value, &fops_imc_x64); 47 } 48 49 /* 50 * export_imc_mode_and_cmd: Create a debugfs interface 51 * for imc_cmd and imc_mode 52 * for each node in the system. 53 * imc_mode and imc_cmd can be changed by echo into 54 * this interface. 55 */ 56 static void export_imc_mode_and_cmd(struct device_node *node, 57 struct imc_pmu *pmu_ptr) 58 { 59 static u64 loc, *imc_mode_addr, *imc_cmd_addr; 60 int chip = 0, nid; 61 char mode[16], cmd[16]; 62 u32 cb_offset; 63 64 imc_debugfs_parent = debugfs_create_dir("imc", powerpc_debugfs_root); 65 66 /* 67 * Return here, either because 'imc' directory already exists, 68 * Or failed to create a new one. 69 */ 70 if (!imc_debugfs_parent) 71 return; 72 73 if (of_property_read_u32(node, "cb_offset", &cb_offset)) 74 cb_offset = IMC_CNTL_BLK_OFFSET; 75 76 for_each_node(nid) { 77 loc = (u64)(pmu_ptr->mem_info[chip].vbase) + cb_offset; 78 imc_mode_addr = (u64 *)(loc + IMC_CNTL_BLK_MODE_OFFSET); 79 sprintf(mode, "imc_mode_%d", nid); 80 if (!imc_debugfs_create_x64(mode, 0600, imc_debugfs_parent, 81 imc_mode_addr)) 82 goto err; 83 84 imc_cmd_addr = (u64 *)(loc + IMC_CNTL_BLK_CMD_OFFSET); 85 sprintf(cmd, "imc_cmd_%d", nid); 86 if (!imc_debugfs_create_x64(cmd, 0600, imc_debugfs_parent, 87 imc_cmd_addr)) 88 goto err; 89 chip++; 90 } 91 return; 92 93 err: 94 debugfs_remove_recursive(imc_debugfs_parent); 95 } 96 97 /* 98 * imc_get_mem_addr_nest: Function to get nest counter memory region 99 * for each chip 100 */ 101 static int imc_get_mem_addr_nest(struct device_node *node, 102 struct imc_pmu *pmu_ptr, 103 u32 offset) 104 { 105 int nr_chips = 0, i; 106 u64 *base_addr_arr, baddr; 107 u32 *chipid_arr; 108 109 nr_chips = of_property_count_u32_elems(node, "chip-id"); 110 if (nr_chips <= 0) 111 return -ENODEV; 112 113 base_addr_arr = kcalloc(nr_chips, sizeof(*base_addr_arr), GFP_KERNEL); 114 if (!base_addr_arr) 115 return -ENOMEM; 116 117 chipid_arr = kcalloc(nr_chips, sizeof(*chipid_arr), GFP_KERNEL); 118 if (!chipid_arr) { 119 kfree(base_addr_arr); 120 return -ENOMEM; 121 } 122 123 if (of_property_read_u32_array(node, "chip-id", chipid_arr, nr_chips)) 124 goto error; 125 126 if (of_property_read_u64_array(node, "base-addr", base_addr_arr, 127 nr_chips)) 128 goto error; 129 130 pmu_ptr->mem_info = kcalloc(nr_chips, sizeof(*pmu_ptr->mem_info), 131 GFP_KERNEL); 132 if (!pmu_ptr->mem_info) 133 goto error; 134 135 for (i = 0; i < nr_chips; i++) { 136 pmu_ptr->mem_info[i].id = chipid_arr[i]; 137 baddr = base_addr_arr[i] + offset; 138 pmu_ptr->mem_info[i].vbase = phys_to_virt(baddr); 139 } 140 141 pmu_ptr->imc_counter_mmaped = true; 142 export_imc_mode_and_cmd(node, pmu_ptr); 143 kfree(base_addr_arr); 144 kfree(chipid_arr); 145 return 0; 146 147 error: 148 kfree(base_addr_arr); 149 kfree(chipid_arr); 150 return -1; 151 } 152 153 /* 154 * imc_pmu_create : Takes the parent device which is the pmu unit, pmu_index 155 * and domain as the inputs. 156 * Allocates memory for the struct imc_pmu, sets up its domain, size and offsets 157 */ 158 static int imc_pmu_create(struct device_node *parent, int pmu_index, int domain) 159 { 160 int ret = 0; 161 struct imc_pmu *pmu_ptr; 162 u32 offset; 163 164 /* memory for pmu */ 165 pmu_ptr = kzalloc(sizeof(*pmu_ptr), GFP_KERNEL); 166 if (!pmu_ptr) 167 return -ENOMEM; 168 169 /* Set the domain */ 170 pmu_ptr->domain = domain; 171 172 ret = of_property_read_u32(parent, "size", &pmu_ptr->counter_mem_size); 173 if (ret) { 174 ret = -EINVAL; 175 goto free_pmu; 176 } 177 178 if (!of_property_read_u32(parent, "offset", &offset)) { 179 if (imc_get_mem_addr_nest(parent, pmu_ptr, offset)) { 180 ret = -EINVAL; 181 goto free_pmu; 182 } 183 } 184 185 /* Function to register IMC pmu */ 186 ret = init_imc_pmu(parent, pmu_ptr, pmu_index); 187 if (ret) { 188 pr_err("IMC PMU %s Register failed\n", pmu_ptr->pmu.name); 189 kfree(pmu_ptr->pmu.name); 190 if (pmu_ptr->domain == IMC_DOMAIN_NEST) 191 kfree(pmu_ptr->mem_info); 192 kfree(pmu_ptr); 193 return ret; 194 } 195 196 return 0; 197 198 free_pmu: 199 kfree(pmu_ptr); 200 return ret; 201 } 202 203 static void disable_nest_pmu_counters(void) 204 { 205 int nid, cpu; 206 const struct cpumask *l_cpumask; 207 208 get_online_cpus(); 209 for_each_node_with_cpus(nid) { 210 l_cpumask = cpumask_of_node(nid); 211 cpu = cpumask_first_and(l_cpumask, cpu_online_mask); 212 if (cpu >= nr_cpu_ids) 213 continue; 214 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, 215 get_hard_smp_processor_id(cpu)); 216 } 217 put_online_cpus(); 218 } 219 220 static void disable_core_pmu_counters(void) 221 { 222 cpumask_t cores_map; 223 int cpu, rc; 224 225 get_online_cpus(); 226 /* Disable the IMC Core functions */ 227 cores_map = cpu_online_cores_map(); 228 for_each_cpu(cpu, &cores_map) { 229 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, 230 get_hard_smp_processor_id(cpu)); 231 if (rc) 232 pr_err("%s: Failed to stop Core (cpu = %d)\n", 233 __FUNCTION__, cpu); 234 } 235 put_online_cpus(); 236 } 237 238 int get_max_nest_dev(void) 239 { 240 struct device_node *node; 241 u32 pmu_units = 0, type; 242 243 for_each_compatible_node(node, NULL, IMC_DTB_UNIT_COMPAT) { 244 if (of_property_read_u32(node, "type", &type)) 245 continue; 246 247 if (type == IMC_TYPE_CHIP) 248 pmu_units++; 249 } 250 251 return pmu_units; 252 } 253 254 static int opal_imc_counters_probe(struct platform_device *pdev) 255 { 256 struct device_node *imc_dev = pdev->dev.of_node; 257 int pmu_count = 0, domain; 258 bool core_imc_reg = false, thread_imc_reg = false; 259 u32 type; 260 261 /* 262 * Check whether this is kdump kernel. If yes, force the engines to 263 * stop and return. 264 */ 265 if (is_kdump_kernel()) { 266 disable_nest_pmu_counters(); 267 disable_core_pmu_counters(); 268 return -ENODEV; 269 } 270 271 for_each_compatible_node(imc_dev, NULL, IMC_DTB_UNIT_COMPAT) { 272 if (of_property_read_u32(imc_dev, "type", &type)) { 273 pr_warn("IMC Device without type property\n"); 274 continue; 275 } 276 277 switch (type) { 278 case IMC_TYPE_CHIP: 279 domain = IMC_DOMAIN_NEST; 280 break; 281 case IMC_TYPE_CORE: 282 domain =IMC_DOMAIN_CORE; 283 break; 284 case IMC_TYPE_THREAD: 285 domain = IMC_DOMAIN_THREAD; 286 break; 287 default: 288 pr_warn("IMC Unknown Device type \n"); 289 domain = -1; 290 break; 291 } 292 293 if (!imc_pmu_create(imc_dev, pmu_count, domain)) { 294 if (domain == IMC_DOMAIN_NEST) 295 pmu_count++; 296 if (domain == IMC_DOMAIN_CORE) 297 core_imc_reg = true; 298 if (domain == IMC_DOMAIN_THREAD) 299 thread_imc_reg = true; 300 } 301 } 302 303 /* If none of the nest units are registered, remove debugfs interface */ 304 if (pmu_count == 0) 305 debugfs_remove_recursive(imc_debugfs_parent); 306 307 /* If core imc is not registered, unregister thread-imc */ 308 if (!core_imc_reg && thread_imc_reg) 309 unregister_thread_imc(); 310 311 return 0; 312 } 313 314 static void opal_imc_counters_shutdown(struct platform_device *pdev) 315 { 316 /* 317 * Function only stops the engines which is bare minimum. 318 * TODO: Need to handle proper memory cleanup and pmu 319 * unregister. 320 */ 321 disable_nest_pmu_counters(); 322 disable_core_pmu_counters(); 323 } 324 325 static const struct of_device_id opal_imc_match[] = { 326 { .compatible = IMC_DTB_COMPAT }, 327 {}, 328 }; 329 330 static struct platform_driver opal_imc_driver = { 331 .driver = { 332 .name = "opal-imc-counters", 333 .of_match_table = opal_imc_match, 334 }, 335 .probe = opal_imc_counters_probe, 336 .shutdown = opal_imc_counters_shutdown, 337 }; 338 339 builtin_platform_driver(opal_imc_driver); 340