1 /* 2 * SMP support for power macintosh. 3 * 4 * We support both the old "powersurge" SMP architecture 5 * and the current Core99 (G4 PowerMac) machines. 6 * 7 * Note that we don't support the very first rev. of 8 * Apple/DayStar 2 CPUs board, the one with the funky 9 * watchdog. Hopefully, none of these should be there except 10 * maybe internally to Apple. I should probably still add some 11 * code to detect this card though and disable SMP. --BenH. 12 * 13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 14 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 15 * 16 * Support for DayStar quad CPU cards 17 * Copyright (C) XLR8, Inc. 1994-2000 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 #include <linux/config.h> 25 #include <linux/kernel.h> 26 #include <linux/sched.h> 27 #include <linux/smp.h> 28 #include <linux/smp_lock.h> 29 #include <linux/interrupt.h> 30 #include <linux/kernel_stat.h> 31 #include <linux/delay.h> 32 #include <linux/init.h> 33 #include <linux/spinlock.h> 34 #include <linux/errno.h> 35 #include <linux/hardirq.h> 36 #include <linux/cpu.h> 37 #include <linux/compiler.h> 38 39 #include <asm/ptrace.h> 40 #include <asm/atomic.h> 41 #include <asm/irq.h> 42 #include <asm/page.h> 43 #include <asm/pgtable.h> 44 #include <asm/sections.h> 45 #include <asm/io.h> 46 #include <asm/prom.h> 47 #include <asm/smp.h> 48 #include <asm/machdep.h> 49 #include <asm/pmac_feature.h> 50 #include <asm/time.h> 51 #include <asm/mpic.h> 52 #include <asm/cacheflush.h> 53 #include <asm/keylargo.h> 54 #include <asm/pmac_low_i2c.h> 55 #include <asm/pmac_pfunc.h> 56 57 #define DEBUG 58 59 #ifdef DEBUG 60 #define DBG(fmt...) udbg_printf(fmt) 61 #else 62 #define DBG(fmt...) 63 #endif 64 65 extern void __secondary_start_pmac_0(void); 66 extern int pmac_pfunc_base_install(void); 67 68 #ifdef CONFIG_PPC32 69 70 /* Sync flag for HW tb sync */ 71 static volatile int sec_tb_reset = 0; 72 73 /* 74 * Powersurge (old powermac SMP) support. 75 */ 76 77 /* Addresses for powersurge registers */ 78 #define HAMMERHEAD_BASE 0xf8000000 79 #define HHEAD_CONFIG 0x90 80 #define HHEAD_SEC_INTR 0xc0 81 82 /* register for interrupting the primary processor on the powersurge */ 83 /* N.B. this is actually the ethernet ROM! */ 84 #define PSURGE_PRI_INTR 0xf3019000 85 86 /* register for storing the start address for the secondary processor */ 87 /* N.B. this is the PCI config space address register for the 1st bridge */ 88 #define PSURGE_START 0xf2800000 89 90 /* Daystar/XLR8 4-CPU card */ 91 #define PSURGE_QUAD_REG_ADDR 0xf8800000 92 93 #define PSURGE_QUAD_IRQ_SET 0 94 #define PSURGE_QUAD_IRQ_CLR 1 95 #define PSURGE_QUAD_IRQ_PRIMARY 2 96 #define PSURGE_QUAD_CKSTOP_CTL 3 97 #define PSURGE_QUAD_PRIMARY_ARB 4 98 #define PSURGE_QUAD_BOARD_ID 6 99 #define PSURGE_QUAD_WHICH_CPU 7 100 #define PSURGE_QUAD_CKSTOP_RDBK 8 101 #define PSURGE_QUAD_RESET_CTL 11 102 103 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 104 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 105 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 106 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 107 108 /* virtual addresses for the above */ 109 static volatile u8 __iomem *hhead_base; 110 static volatile u8 __iomem *quad_base; 111 static volatile u32 __iomem *psurge_pri_intr; 112 static volatile u8 __iomem *psurge_sec_intr; 113 static volatile u32 __iomem *psurge_start; 114 115 /* values for psurge_type */ 116 #define PSURGE_NONE -1 117 #define PSURGE_DUAL 0 118 #define PSURGE_QUAD_OKEE 1 119 #define PSURGE_QUAD_COTTON 2 120 #define PSURGE_QUAD_ICEGRASS 3 121 122 /* what sort of powersurge board we have */ 123 static int psurge_type = PSURGE_NONE; 124 125 /* 126 * Set and clear IPIs for powersurge. 127 */ 128 static inline void psurge_set_ipi(int cpu) 129 { 130 if (psurge_type == PSURGE_NONE) 131 return; 132 if (cpu == 0) 133 in_be32(psurge_pri_intr); 134 else if (psurge_type == PSURGE_DUAL) 135 out_8(psurge_sec_intr, 0); 136 else 137 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 138 } 139 140 static inline void psurge_clr_ipi(int cpu) 141 { 142 if (cpu > 0) { 143 switch(psurge_type) { 144 case PSURGE_DUAL: 145 out_8(psurge_sec_intr, ~0); 146 case PSURGE_NONE: 147 break; 148 default: 149 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 150 } 151 } 152 } 153 154 /* 155 * On powersurge (old SMP powermac architecture) we don't have 156 * separate IPIs for separate messages like openpic does. Instead 157 * we have a bitmap for each processor, where a 1 bit means that 158 * the corresponding message is pending for that processor. 159 * Ideally each cpu's entry would be in a different cache line. 160 * -- paulus. 161 */ 162 static unsigned long psurge_smp_message[NR_CPUS]; 163 164 void psurge_smp_message_recv(struct pt_regs *regs) 165 { 166 int cpu = smp_processor_id(); 167 int msg; 168 169 /* clear interrupt */ 170 psurge_clr_ipi(cpu); 171 172 if (num_online_cpus() < 2) 173 return; 174 175 /* make sure there is a message there */ 176 for (msg = 0; msg < 4; msg++) 177 if (test_and_clear_bit(msg, &psurge_smp_message[cpu])) 178 smp_message_recv(msg, regs); 179 } 180 181 irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs) 182 { 183 psurge_smp_message_recv(regs); 184 return IRQ_HANDLED; 185 } 186 187 static void smp_psurge_message_pass(int target, int msg) 188 { 189 int i; 190 191 if (num_online_cpus() < 2) 192 return; 193 194 for_each_online_cpu(i) { 195 if (target == MSG_ALL 196 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id()) 197 || target == i) { 198 set_bit(msg, &psurge_smp_message[i]); 199 psurge_set_ipi(i); 200 } 201 } 202 } 203 204 /* 205 * Determine a quad card presence. We read the board ID register, we 206 * force the data bus to change to something else, and we read it again. 207 * It it's stable, then the register probably exist (ugh !) 208 */ 209 static int __init psurge_quad_probe(void) 210 { 211 int type; 212 unsigned int i; 213 214 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 215 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 216 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 217 return PSURGE_DUAL; 218 219 /* looks OK, try a slightly more rigorous test */ 220 /* bogus is not necessarily cacheline-aligned, 221 though I don't suppose that really matters. -- paulus */ 222 for (i = 0; i < 100; i++) { 223 volatile u32 bogus[8]; 224 bogus[(0+i)%8] = 0x00000000; 225 bogus[(1+i)%8] = 0x55555555; 226 bogus[(2+i)%8] = 0xFFFFFFFF; 227 bogus[(3+i)%8] = 0xAAAAAAAA; 228 bogus[(4+i)%8] = 0x33333333; 229 bogus[(5+i)%8] = 0xCCCCCCCC; 230 bogus[(6+i)%8] = 0xCCCCCCCC; 231 bogus[(7+i)%8] = 0x33333333; 232 wmb(); 233 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 234 mb(); 235 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 236 return PSURGE_DUAL; 237 } 238 return type; 239 } 240 241 static void __init psurge_quad_init(void) 242 { 243 int procbits; 244 245 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 246 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 247 if (psurge_type == PSURGE_QUAD_ICEGRASS) 248 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 249 else 250 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 251 mdelay(33); 252 out_8(psurge_sec_intr, ~0); 253 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 254 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 255 if (psurge_type != PSURGE_QUAD_ICEGRASS) 256 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 257 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 258 mdelay(33); 259 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 260 mdelay(33); 261 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 262 mdelay(33); 263 } 264 265 static int __init smp_psurge_probe(void) 266 { 267 int i, ncpus; 268 269 /* We don't do SMP on the PPC601 -- paulus */ 270 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 271 return 1; 272 273 /* 274 * The powersurge cpu board can be used in the generation 275 * of powermacs that have a socket for an upgradeable cpu card, 276 * including the 7500, 8500, 9500, 9600. 277 * The device tree doesn't tell you if you have 2 cpus because 278 * OF doesn't know anything about the 2nd processor. 279 * Instead we look for magic bits in magic registers, 280 * in the hammerhead memory controller in the case of the 281 * dual-cpu powersurge board. -- paulus. 282 */ 283 if (find_devices("hammerhead") == NULL) 284 return 1; 285 286 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 287 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 288 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 289 290 psurge_type = psurge_quad_probe(); 291 if (psurge_type != PSURGE_DUAL) { 292 psurge_quad_init(); 293 /* All released cards using this HW design have 4 CPUs */ 294 ncpus = 4; 295 } else { 296 iounmap(quad_base); 297 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 298 /* not a dual-cpu card */ 299 iounmap(hhead_base); 300 psurge_type = PSURGE_NONE; 301 return 1; 302 } 303 ncpus = 2; 304 } 305 306 psurge_start = ioremap(PSURGE_START, 4); 307 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 308 309 /* 310 * This is necessary because OF doesn't know about the 311 * secondary cpu(s), and thus there aren't nodes in the 312 * device tree for them, and smp_setup_cpu_maps hasn't 313 * set their bits in cpu_possible_map and cpu_present_map. 314 */ 315 if (ncpus > NR_CPUS) 316 ncpus = NR_CPUS; 317 for (i = 1; i < ncpus ; ++i) { 318 cpu_set(i, cpu_present_map); 319 cpu_set(i, cpu_possible_map); 320 set_hard_smp_processor_id(i, i); 321 } 322 323 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 324 325 return ncpus; 326 } 327 328 static void __init smp_psurge_kick_cpu(int nr) 329 { 330 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 331 unsigned long a; 332 333 /* may need to flush here if secondary bats aren't setup */ 334 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 335 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 336 asm volatile("sync"); 337 338 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 339 340 out_be32(psurge_start, start); 341 mb(); 342 343 psurge_set_ipi(nr); 344 udelay(10); 345 psurge_clr_ipi(nr); 346 347 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 348 } 349 350 /* 351 * With the dual-cpu powersurge board, the decrementers and timebases 352 * of both cpus are frozen after the secondary cpu is started up, 353 * until we give the secondary cpu another interrupt. This routine 354 * uses this to get the timebases synchronized. 355 * -- paulus. 356 */ 357 static void __init psurge_dual_sync_tb(int cpu_nr) 358 { 359 int t; 360 361 set_dec(tb_ticks_per_jiffy); 362 /* XXX fixme */ 363 set_tb(0, 0); 364 365 if (cpu_nr > 0) { 366 mb(); 367 sec_tb_reset = 1; 368 return; 369 } 370 371 /* wait for the secondary to have reset its TB before proceeding */ 372 for (t = 10000000; t > 0 && !sec_tb_reset; --t) 373 ; 374 375 /* now interrupt the secondary, starting both TBs */ 376 psurge_set_ipi(1); 377 } 378 379 static struct irqaction psurge_irqaction = { 380 .handler = psurge_primary_intr, 381 .flags = SA_INTERRUPT, 382 .mask = CPU_MASK_NONE, 383 .name = "primary IPI", 384 }; 385 386 static void __init smp_psurge_setup_cpu(int cpu_nr) 387 { 388 389 if (cpu_nr == 0) { 390 /* If we failed to start the second CPU, we should still 391 * send it an IPI to start the timebase & DEC or we might 392 * have them stuck. 393 */ 394 if (num_online_cpus() < 2) { 395 if (psurge_type == PSURGE_DUAL) 396 psurge_set_ipi(1); 397 return; 398 } 399 /* reset the entry point so if we get another intr we won't 400 * try to startup again */ 401 out_be32(psurge_start, 0x100); 402 if (setup_irq(30, &psurge_irqaction)) 403 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 404 } 405 406 if (psurge_type == PSURGE_DUAL) 407 psurge_dual_sync_tb(cpu_nr); 408 } 409 410 void __init smp_psurge_take_timebase(void) 411 { 412 /* Dummy implementation */ 413 } 414 415 void __init smp_psurge_give_timebase(void) 416 { 417 /* Dummy implementation */ 418 } 419 420 /* PowerSurge-style Macs */ 421 struct smp_ops_t psurge_smp_ops = { 422 .message_pass = smp_psurge_message_pass, 423 .probe = smp_psurge_probe, 424 .kick_cpu = smp_psurge_kick_cpu, 425 .setup_cpu = smp_psurge_setup_cpu, 426 .give_timebase = smp_psurge_give_timebase, 427 .take_timebase = smp_psurge_take_timebase, 428 }; 429 #endif /* CONFIG_PPC32 - actually powersurge support */ 430 431 /* 432 * Core 99 and later support 433 */ 434 435 static void (*pmac_tb_freeze)(int freeze); 436 static u64 timebase; 437 static int tb_req; 438 439 static void smp_core99_give_timebase(void) 440 { 441 unsigned long flags; 442 443 local_irq_save(flags); 444 445 while(!tb_req) 446 barrier(); 447 tb_req = 0; 448 (*pmac_tb_freeze)(1); 449 mb(); 450 timebase = get_tb(); 451 mb(); 452 while (timebase) 453 barrier(); 454 mb(); 455 (*pmac_tb_freeze)(0); 456 mb(); 457 458 local_irq_restore(flags); 459 } 460 461 462 static void __devinit smp_core99_take_timebase(void) 463 { 464 unsigned long flags; 465 466 local_irq_save(flags); 467 468 tb_req = 1; 469 mb(); 470 while (!timebase) 471 barrier(); 472 mb(); 473 set_tb(timebase >> 32, timebase & 0xffffffff); 474 timebase = 0; 475 mb(); 476 set_dec(tb_ticks_per_jiffy/2); 477 478 local_irq_restore(flags); 479 } 480 481 #ifdef CONFIG_PPC64 482 /* 483 * G5s enable/disable the timebase via an i2c-connected clock chip. 484 */ 485 static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 486 static u8 pmac_tb_pulsar_addr; 487 488 static void smp_core99_cypress_tb_freeze(int freeze) 489 { 490 u8 data; 491 int rc; 492 493 /* Strangely, the device-tree says address is 0xd2, but darwin 494 * accesses 0xd0 ... 495 */ 496 pmac_i2c_setmode(pmac_tb_clock_chip_host, 497 pmac_i2c_mode_combined); 498 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 499 0xd0 | pmac_i2c_read, 500 1, 0x81, &data, 1); 501 if (rc != 0) 502 goto bail; 503 504 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 505 506 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 507 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 508 0xd0 | pmac_i2c_write, 509 1, 0x81, &data, 1); 510 511 bail: 512 if (rc != 0) { 513 printk("Cypress Timebase %s rc: %d\n", 514 freeze ? "freeze" : "unfreeze", rc); 515 panic("Timebase freeze failed !\n"); 516 } 517 } 518 519 520 static void smp_core99_pulsar_tb_freeze(int freeze) 521 { 522 u8 data; 523 int rc; 524 525 pmac_i2c_setmode(pmac_tb_clock_chip_host, 526 pmac_i2c_mode_combined); 527 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 528 pmac_tb_pulsar_addr | pmac_i2c_read, 529 1, 0x2e, &data, 1); 530 if (rc != 0) 531 goto bail; 532 533 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 534 535 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 536 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 537 pmac_tb_pulsar_addr | pmac_i2c_write, 538 1, 0x2e, &data, 1); 539 bail: 540 if (rc != 0) { 541 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 542 freeze ? "freeze" : "unfreeze", rc); 543 panic("Timebase freeze failed !\n"); 544 } 545 } 546 547 static void __init smp_core99_setup_i2c_hwsync(int ncpus) 548 { 549 struct device_node *cc = NULL; 550 struct device_node *p; 551 const char *name = NULL; 552 u32 *reg; 553 int ok; 554 555 /* Look for the clock chip */ 556 while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) { 557 p = of_get_parent(cc); 558 ok = p && device_is_compatible(p, "uni-n-i2c"); 559 of_node_put(p); 560 if (!ok) 561 continue; 562 563 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 564 if (pmac_tb_clock_chip_host == NULL) 565 continue; 566 reg = (u32 *)get_property(cc, "reg", NULL); 567 if (reg == NULL) 568 continue; 569 switch (*reg) { 570 case 0xd2: 571 if (device_is_compatible(cc,"pulsar-legacy-slewing")) { 572 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 573 pmac_tb_pulsar_addr = 0xd2; 574 name = "Pulsar"; 575 } else if (device_is_compatible(cc, "cy28508")) { 576 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 577 name = "Cypress"; 578 } 579 break; 580 case 0xd4: 581 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 582 pmac_tb_pulsar_addr = 0xd4; 583 name = "Pulsar"; 584 break; 585 } 586 if (pmac_tb_freeze != NULL) 587 break; 588 } 589 if (pmac_tb_freeze != NULL) { 590 /* Open i2c bus for synchronous access */ 591 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 592 printk(KERN_ERR "Failed top open i2c bus for clock" 593 " sync, fallback to software sync !\n"); 594 goto no_i2c_sync; 595 } 596 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 597 name); 598 return; 599 } 600 no_i2c_sync: 601 pmac_tb_freeze = NULL; 602 pmac_tb_clock_chip_host = NULL; 603 } 604 605 606 607 /* 608 * Newer G5s uses a platform function 609 */ 610 611 static void smp_core99_pfunc_tb_freeze(int freeze) 612 { 613 struct device_node *cpus; 614 struct pmf_args args; 615 616 cpus = of_find_node_by_path("/cpus"); 617 BUG_ON(cpus == NULL); 618 args.count = 1; 619 args.u[0].v = !freeze; 620 pmf_call_function(cpus, "cpu-timebase", &args); 621 of_node_put(cpus); 622 } 623 624 #else /* CONFIG_PPC64 */ 625 626 /* 627 * SMP G4 use a GPIO to enable/disable the timebase. 628 */ 629 630 static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 631 632 static void smp_core99_gpio_tb_freeze(int freeze) 633 { 634 if (freeze) 635 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 636 else 637 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 638 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 639 } 640 641 642 #endif /* !CONFIG_PPC64 */ 643 644 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 645 volatile static long int core99_l2_cache; 646 volatile static long int core99_l3_cache; 647 648 static void __devinit core99_init_caches(int cpu) 649 { 650 #ifndef CONFIG_PPC64 651 if (!cpu_has_feature(CPU_FTR_L2CR)) 652 return; 653 654 if (cpu == 0) { 655 core99_l2_cache = _get_L2CR(); 656 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 657 } else { 658 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 659 _set_L2CR(0); 660 _set_L2CR(core99_l2_cache); 661 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 662 } 663 664 if (!cpu_has_feature(CPU_FTR_L3CR)) 665 return; 666 667 if (cpu == 0){ 668 core99_l3_cache = _get_L3CR(); 669 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 670 } else { 671 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 672 _set_L3CR(0); 673 _set_L3CR(core99_l3_cache); 674 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 675 } 676 #endif /* !CONFIG_PPC64 */ 677 } 678 679 static void __init smp_core99_setup(int ncpus) 680 { 681 #ifdef CONFIG_PPC64 682 683 /* i2c based HW sync on some G5s */ 684 if (machine_is_compatible("PowerMac7,2") || 685 machine_is_compatible("PowerMac7,3") || 686 machine_is_compatible("RackMac3,1")) 687 smp_core99_setup_i2c_hwsync(ncpus); 688 689 /* pfunc based HW sync on recent G5s */ 690 if (pmac_tb_freeze == NULL) { 691 struct device_node *cpus = 692 of_find_node_by_path("/cpus"); 693 if (cpus && 694 get_property(cpus, "platform-cpu-timebase", NULL)) { 695 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 696 printk(KERN_INFO "Processor timebase sync using" 697 " platform function\n"); 698 } 699 } 700 701 #else /* CONFIG_PPC64 */ 702 703 /* GPIO based HW sync on ppc32 Core99 */ 704 if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) { 705 struct device_node *cpu; 706 u32 *tbprop = NULL; 707 708 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 709 cpu = of_find_node_by_type(NULL, "cpu"); 710 if (cpu != NULL) { 711 tbprop = (u32 *)get_property(cpu, "timebase-enable", 712 NULL); 713 if (tbprop) 714 core99_tb_gpio = *tbprop; 715 of_node_put(cpu); 716 } 717 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 718 printk(KERN_INFO "Processor timebase sync using" 719 " GPIO 0x%02x\n", core99_tb_gpio); 720 } 721 722 #endif /* CONFIG_PPC64 */ 723 724 /* No timebase sync, fallback to software */ 725 if (pmac_tb_freeze == NULL) { 726 smp_ops->give_timebase = smp_generic_give_timebase; 727 smp_ops->take_timebase = smp_generic_take_timebase; 728 printk(KERN_INFO "Processor timebase sync using software\n"); 729 } 730 731 #ifndef CONFIG_PPC64 732 { 733 int i; 734 735 /* XXX should get this from reg properties */ 736 for (i = 1; i < ncpus; ++i) 737 smp_hw_index[i] = i; 738 } 739 #endif 740 741 /* 32 bits SMP can't NAP */ 742 if (!machine_is_compatible("MacRISC4")) 743 powersave_nap = 0; 744 } 745 746 static int __init smp_core99_probe(void) 747 { 748 struct device_node *cpus; 749 int ncpus = 0; 750 751 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 752 753 /* Count CPUs in the device-tree */ 754 for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;) 755 ++ncpus; 756 757 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 758 759 /* Nothing more to do if less than 2 of them */ 760 if (ncpus <= 1) 761 return 1; 762 763 /* We need to perform some early initialisations before we can start 764 * setting up SMP as we are running before initcalls 765 */ 766 pmac_pfunc_base_install(); 767 pmac_i2c_init(); 768 769 /* Setup various bits like timebase sync method, ability to nap, ... */ 770 smp_core99_setup(ncpus); 771 772 /* Install IPIs */ 773 mpic_request_ipis(); 774 775 /* Collect l2cr and l3cr values from CPU 0 */ 776 core99_init_caches(0); 777 778 return ncpus; 779 } 780 781 static void __devinit smp_core99_kick_cpu(int nr) 782 { 783 unsigned int save_vector; 784 unsigned long target, flags; 785 volatile unsigned int *vector 786 = ((volatile unsigned int *)(KERNELBASE+0x100)); 787 788 if (nr < 0 || nr > 3) 789 return; 790 791 if (ppc_md.progress) 792 ppc_md.progress("smp_core99_kick_cpu", 0x346); 793 794 local_irq_save(flags); 795 local_irq_disable(); 796 797 /* Save reset vector */ 798 save_vector = *vector; 799 800 /* Setup fake reset vector that does 801 * b __secondary_start_pmac_0 + nr*8 - KERNELBASE 802 */ 803 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 804 create_branch((unsigned long)vector, target, BRANCH_SET_LINK); 805 806 /* Put some life in our friend */ 807 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 808 809 /* FIXME: We wait a bit for the CPU to take the exception, I should 810 * instead wait for the entry code to set something for me. Well, 811 * ideally, all that crap will be done in prom.c and the CPU left 812 * in a RAM-based wait loop like CHRP. 813 */ 814 mdelay(1); 815 816 /* Restore our exception vector */ 817 *vector = save_vector; 818 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); 819 820 local_irq_restore(flags); 821 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 822 } 823 824 static void __devinit smp_core99_setup_cpu(int cpu_nr) 825 { 826 /* Setup L2/L3 */ 827 if (cpu_nr != 0) 828 core99_init_caches(cpu_nr); 829 830 /* Setup openpic */ 831 mpic_setup_this_cpu(); 832 833 if (cpu_nr == 0) { 834 #ifdef CONFIG_PPC64 835 extern void g5_phy_disable_cpu1(void); 836 837 /* Close i2c bus if it was used for tb sync */ 838 if (pmac_tb_clock_chip_host) { 839 pmac_i2c_close(pmac_tb_clock_chip_host); 840 pmac_tb_clock_chip_host = NULL; 841 } 842 843 /* If we didn't start the second CPU, we must take 844 * it off the bus 845 */ 846 if (machine_is_compatible("MacRISC4") && 847 num_online_cpus() < 2) 848 g5_phy_disable_cpu1(); 849 #endif /* CONFIG_PPC64 */ 850 851 if (ppc_md.progress) 852 ppc_md.progress("core99_setup_cpu 0 done", 0x349); 853 } 854 } 855 856 857 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) 858 859 int smp_core99_cpu_disable(void) 860 { 861 cpu_clear(smp_processor_id(), cpu_online_map); 862 863 /* XXX reset cpu affinity here */ 864 mpic_cpu_set_priority(0xf); 865 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 866 mb(); 867 udelay(20); 868 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 869 return 0; 870 } 871 872 extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */ 873 static int cpu_dead[NR_CPUS]; 874 875 void cpu_die(void) 876 { 877 local_irq_disable(); 878 cpu_dead[smp_processor_id()] = 1; 879 mb(); 880 low_cpu_die(); 881 } 882 883 void smp_core99_cpu_die(unsigned int cpu) 884 { 885 int timeout; 886 887 timeout = 1000; 888 while (!cpu_dead[cpu]) { 889 if (--timeout == 0) { 890 printk("CPU %u refused to die!\n", cpu); 891 break; 892 } 893 msleep(1); 894 } 895 cpu_dead[cpu] = 0; 896 } 897 898 #endif 899 900 /* Core99 Macs (dual G4s and G5s) */ 901 struct smp_ops_t core99_smp_ops = { 902 .message_pass = smp_mpic_message_pass, 903 .probe = smp_core99_probe, 904 .kick_cpu = smp_core99_kick_cpu, 905 .setup_cpu = smp_core99_setup_cpu, 906 .give_timebase = smp_core99_give_timebase, 907 .take_timebase = smp_core99_take_timebase, 908 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) 909 .cpu_disable = smp_core99_cpu_disable, 910 .cpu_die = smp_core99_cpu_die, 911 #endif 912 }; 913