1 /* 2 * SMP support for power macintosh. 3 * 4 * We support both the old "powersurge" SMP architecture 5 * and the current Core99 (G4 PowerMac) machines. 6 * 7 * Note that we don't support the very first rev. of 8 * Apple/DayStar 2 CPUs board, the one with the funky 9 * watchdog. Hopefully, none of these should be there except 10 * maybe internally to Apple. I should probably still add some 11 * code to detect this card though and disable SMP. --BenH. 12 * 13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 14 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 15 * 16 * Support for DayStar quad CPU cards 17 * Copyright (C) XLR8, Inc. 1994-2000 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 #include <linux/kernel.h> 25 #include <linux/sched.h> 26 #include <linux/smp.h> 27 #include <linux/interrupt.h> 28 #include <linux/kernel_stat.h> 29 #include <linux/delay.h> 30 #include <linux/init.h> 31 #include <linux/spinlock.h> 32 #include <linux/errno.h> 33 #include <linux/hardirq.h> 34 #include <linux/cpu.h> 35 #include <linux/compiler.h> 36 37 #include <asm/ptrace.h> 38 #include <linux/atomic.h> 39 #include <asm/code-patching.h> 40 #include <asm/irq.h> 41 #include <asm/page.h> 42 #include <asm/pgtable.h> 43 #include <asm/sections.h> 44 #include <asm/io.h> 45 #include <asm/prom.h> 46 #include <asm/smp.h> 47 #include <asm/machdep.h> 48 #include <asm/pmac_feature.h> 49 #include <asm/time.h> 50 #include <asm/mpic.h> 51 #include <asm/cacheflush.h> 52 #include <asm/keylargo.h> 53 #include <asm/pmac_low_i2c.h> 54 #include <asm/pmac_pfunc.h> 55 56 #include "pmac.h" 57 58 #undef DEBUG 59 60 #ifdef DEBUG 61 #define DBG(fmt...) udbg_printf(fmt) 62 #else 63 #define DBG(fmt...) 64 #endif 65 66 extern void __secondary_start_pmac_0(void); 67 extern int pmac_pfunc_base_install(void); 68 69 static void (*pmac_tb_freeze)(int freeze); 70 static u64 timebase; 71 static int tb_req; 72 73 #ifdef CONFIG_PPC_PMAC32_PSURGE 74 75 /* 76 * Powersurge (old powermac SMP) support. 77 */ 78 79 /* Addresses for powersurge registers */ 80 #define HAMMERHEAD_BASE 0xf8000000 81 #define HHEAD_CONFIG 0x90 82 #define HHEAD_SEC_INTR 0xc0 83 84 /* register for interrupting the primary processor on the powersurge */ 85 /* N.B. this is actually the ethernet ROM! */ 86 #define PSURGE_PRI_INTR 0xf3019000 87 88 /* register for storing the start address for the secondary processor */ 89 /* N.B. this is the PCI config space address register for the 1st bridge */ 90 #define PSURGE_START 0xf2800000 91 92 /* Daystar/XLR8 4-CPU card */ 93 #define PSURGE_QUAD_REG_ADDR 0xf8800000 94 95 #define PSURGE_QUAD_IRQ_SET 0 96 #define PSURGE_QUAD_IRQ_CLR 1 97 #define PSURGE_QUAD_IRQ_PRIMARY 2 98 #define PSURGE_QUAD_CKSTOP_CTL 3 99 #define PSURGE_QUAD_PRIMARY_ARB 4 100 #define PSURGE_QUAD_BOARD_ID 6 101 #define PSURGE_QUAD_WHICH_CPU 7 102 #define PSURGE_QUAD_CKSTOP_RDBK 8 103 #define PSURGE_QUAD_RESET_CTL 11 104 105 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 106 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 107 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 108 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 109 110 /* virtual addresses for the above */ 111 static volatile u8 __iomem *hhead_base; 112 static volatile u8 __iomem *quad_base; 113 static volatile u32 __iomem *psurge_pri_intr; 114 static volatile u8 __iomem *psurge_sec_intr; 115 static volatile u32 __iomem *psurge_start; 116 117 /* values for psurge_type */ 118 #define PSURGE_NONE -1 119 #define PSURGE_DUAL 0 120 #define PSURGE_QUAD_OKEE 1 121 #define PSURGE_QUAD_COTTON 2 122 #define PSURGE_QUAD_ICEGRASS 3 123 124 /* what sort of powersurge board we have */ 125 static int psurge_type = PSURGE_NONE; 126 127 /* irq for secondary cpus to report */ 128 static struct irq_domain *psurge_host; 129 int psurge_secondary_virq; 130 131 /* 132 * Set and clear IPIs for powersurge. 133 */ 134 static inline void psurge_set_ipi(int cpu) 135 { 136 if (psurge_type == PSURGE_NONE) 137 return; 138 if (cpu == 0) 139 in_be32(psurge_pri_intr); 140 else if (psurge_type == PSURGE_DUAL) 141 out_8(psurge_sec_intr, 0); 142 else 143 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 144 } 145 146 static inline void psurge_clr_ipi(int cpu) 147 { 148 if (cpu > 0) { 149 switch(psurge_type) { 150 case PSURGE_DUAL: 151 out_8(psurge_sec_intr, ~0); 152 case PSURGE_NONE: 153 break; 154 default: 155 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 156 } 157 } 158 } 159 160 /* 161 * On powersurge (old SMP powermac architecture) we don't have 162 * separate IPIs for separate messages like openpic does. Instead 163 * use the generic demux helpers 164 * -- paulus. 165 */ 166 static irqreturn_t psurge_ipi_intr(int irq, void *d) 167 { 168 psurge_clr_ipi(smp_processor_id()); 169 smp_ipi_demux(); 170 171 return IRQ_HANDLED; 172 } 173 174 static void smp_psurge_cause_ipi(int cpu, unsigned long data) 175 { 176 psurge_set_ipi(cpu); 177 } 178 179 static int psurge_host_map(struct irq_domain *h, unsigned int virq, 180 irq_hw_number_t hw) 181 { 182 irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq); 183 184 return 0; 185 } 186 187 static const struct irq_domain_ops psurge_host_ops = { 188 .map = psurge_host_map, 189 }; 190 191 static int psurge_secondary_ipi_init(void) 192 { 193 int rc = -ENOMEM; 194 195 psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL); 196 197 if (psurge_host) 198 psurge_secondary_virq = irq_create_direct_mapping(psurge_host); 199 200 if (psurge_secondary_virq) 201 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr, 202 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL); 203 204 if (rc) 205 pr_err("Failed to setup secondary cpu IPI\n"); 206 207 return rc; 208 } 209 210 /* 211 * Determine a quad card presence. We read the board ID register, we 212 * force the data bus to change to something else, and we read it again. 213 * It it's stable, then the register probably exist (ugh !) 214 */ 215 static int __init psurge_quad_probe(void) 216 { 217 int type; 218 unsigned int i; 219 220 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 221 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 222 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 223 return PSURGE_DUAL; 224 225 /* looks OK, try a slightly more rigorous test */ 226 /* bogus is not necessarily cacheline-aligned, 227 though I don't suppose that really matters. -- paulus */ 228 for (i = 0; i < 100; i++) { 229 volatile u32 bogus[8]; 230 bogus[(0+i)%8] = 0x00000000; 231 bogus[(1+i)%8] = 0x55555555; 232 bogus[(2+i)%8] = 0xFFFFFFFF; 233 bogus[(3+i)%8] = 0xAAAAAAAA; 234 bogus[(4+i)%8] = 0x33333333; 235 bogus[(5+i)%8] = 0xCCCCCCCC; 236 bogus[(6+i)%8] = 0xCCCCCCCC; 237 bogus[(7+i)%8] = 0x33333333; 238 wmb(); 239 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 240 mb(); 241 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 242 return PSURGE_DUAL; 243 } 244 return type; 245 } 246 247 static void __init psurge_quad_init(void) 248 { 249 int procbits; 250 251 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 252 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 253 if (psurge_type == PSURGE_QUAD_ICEGRASS) 254 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 255 else 256 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 257 mdelay(33); 258 out_8(psurge_sec_intr, ~0); 259 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 260 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 261 if (psurge_type != PSURGE_QUAD_ICEGRASS) 262 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 263 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 264 mdelay(33); 265 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 266 mdelay(33); 267 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 268 mdelay(33); 269 } 270 271 static void __init smp_psurge_probe(void) 272 { 273 int i, ncpus; 274 struct device_node *dn; 275 276 /* We don't do SMP on the PPC601 -- paulus */ 277 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 278 return; 279 280 /* 281 * The powersurge cpu board can be used in the generation 282 * of powermacs that have a socket for an upgradeable cpu card, 283 * including the 7500, 8500, 9500, 9600. 284 * The device tree doesn't tell you if you have 2 cpus because 285 * OF doesn't know anything about the 2nd processor. 286 * Instead we look for magic bits in magic registers, 287 * in the hammerhead memory controller in the case of the 288 * dual-cpu powersurge board. -- paulus. 289 */ 290 dn = of_find_node_by_name(NULL, "hammerhead"); 291 if (dn == NULL) 292 return; 293 of_node_put(dn); 294 295 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 296 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 297 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 298 299 psurge_type = psurge_quad_probe(); 300 if (psurge_type != PSURGE_DUAL) { 301 psurge_quad_init(); 302 /* All released cards using this HW design have 4 CPUs */ 303 ncpus = 4; 304 /* No sure how timebase sync works on those, let's use SW */ 305 smp_ops->give_timebase = smp_generic_give_timebase; 306 smp_ops->take_timebase = smp_generic_take_timebase; 307 } else { 308 iounmap(quad_base); 309 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 310 /* not a dual-cpu card */ 311 iounmap(hhead_base); 312 psurge_type = PSURGE_NONE; 313 return; 314 } 315 ncpus = 2; 316 } 317 318 if (psurge_secondary_ipi_init()) 319 return; 320 321 psurge_start = ioremap(PSURGE_START, 4); 322 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 323 324 /* This is necessary because OF doesn't know about the 325 * secondary cpu(s), and thus there aren't nodes in the 326 * device tree for them, and smp_setup_cpu_maps hasn't 327 * set their bits in cpu_present_mask. 328 */ 329 if (ncpus > NR_CPUS) 330 ncpus = NR_CPUS; 331 for (i = 1; i < ncpus ; ++i) 332 set_cpu_present(i, true); 333 334 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 335 } 336 337 static int __init smp_psurge_kick_cpu(int nr) 338 { 339 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 340 unsigned long a, flags; 341 int i, j; 342 343 /* Defining this here is evil ... but I prefer hiding that 344 * crap to avoid giving people ideas that they can do the 345 * same. 346 */ 347 extern volatile unsigned int cpu_callin_map[NR_CPUS]; 348 349 /* may need to flush here if secondary bats aren't setup */ 350 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 351 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 352 asm volatile("sync"); 353 354 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 355 356 /* This is going to freeze the timeebase, we disable interrupts */ 357 local_irq_save(flags); 358 359 out_be32(psurge_start, start); 360 mb(); 361 362 psurge_set_ipi(nr); 363 364 /* 365 * We can't use udelay here because the timebase is now frozen. 366 */ 367 for (i = 0; i < 2000; ++i) 368 asm volatile("nop" : : : "memory"); 369 psurge_clr_ipi(nr); 370 371 /* 372 * Also, because the timebase is frozen, we must not return to the 373 * caller which will try to do udelay's etc... Instead, we wait -here- 374 * for the CPU to callin. 375 */ 376 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { 377 for (j = 1; j < 10000; j++) 378 asm volatile("nop" : : : "memory"); 379 asm volatile("sync" : : : "memory"); 380 } 381 if (!cpu_callin_map[nr]) 382 goto stuck; 383 384 /* And we do the TB sync here too for standard dual CPU cards */ 385 if (psurge_type == PSURGE_DUAL) { 386 while(!tb_req) 387 barrier(); 388 tb_req = 0; 389 mb(); 390 timebase = get_tb(); 391 mb(); 392 while (timebase) 393 barrier(); 394 mb(); 395 } 396 stuck: 397 /* now interrupt the secondary, restarting both TBs */ 398 if (psurge_type == PSURGE_DUAL) 399 psurge_set_ipi(1); 400 401 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 402 403 return 0; 404 } 405 406 static struct irqaction psurge_irqaction = { 407 .handler = psurge_ipi_intr, 408 .flags = IRQF_PERCPU | IRQF_NO_THREAD, 409 .name = "primary IPI", 410 }; 411 412 static void __init smp_psurge_setup_cpu(int cpu_nr) 413 { 414 if (cpu_nr != 0 || !psurge_start) 415 return; 416 417 /* reset the entry point so if we get another intr we won't 418 * try to startup again */ 419 out_be32(psurge_start, 0x100); 420 if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction)) 421 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 422 } 423 424 void __init smp_psurge_take_timebase(void) 425 { 426 if (psurge_type != PSURGE_DUAL) 427 return; 428 429 tb_req = 1; 430 mb(); 431 while (!timebase) 432 barrier(); 433 mb(); 434 set_tb(timebase >> 32, timebase & 0xffffffff); 435 timebase = 0; 436 mb(); 437 set_dec(tb_ticks_per_jiffy/2); 438 } 439 440 void __init smp_psurge_give_timebase(void) 441 { 442 /* Nothing to do here */ 443 } 444 445 /* PowerSurge-style Macs */ 446 struct smp_ops_t psurge_smp_ops = { 447 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */ 448 .cause_ipi = smp_psurge_cause_ipi, 449 .probe = smp_psurge_probe, 450 .kick_cpu = smp_psurge_kick_cpu, 451 .setup_cpu = smp_psurge_setup_cpu, 452 .give_timebase = smp_psurge_give_timebase, 453 .take_timebase = smp_psurge_take_timebase, 454 }; 455 #endif /* CONFIG_PPC_PMAC32_PSURGE */ 456 457 /* 458 * Core 99 and later support 459 */ 460 461 462 static void smp_core99_give_timebase(void) 463 { 464 unsigned long flags; 465 466 local_irq_save(flags); 467 468 while(!tb_req) 469 barrier(); 470 tb_req = 0; 471 (*pmac_tb_freeze)(1); 472 mb(); 473 timebase = get_tb(); 474 mb(); 475 while (timebase) 476 barrier(); 477 mb(); 478 (*pmac_tb_freeze)(0); 479 mb(); 480 481 local_irq_restore(flags); 482 } 483 484 485 static void smp_core99_take_timebase(void) 486 { 487 unsigned long flags; 488 489 local_irq_save(flags); 490 491 tb_req = 1; 492 mb(); 493 while (!timebase) 494 barrier(); 495 mb(); 496 set_tb(timebase >> 32, timebase & 0xffffffff); 497 timebase = 0; 498 mb(); 499 500 local_irq_restore(flags); 501 } 502 503 #ifdef CONFIG_PPC64 504 /* 505 * G5s enable/disable the timebase via an i2c-connected clock chip. 506 */ 507 static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 508 static u8 pmac_tb_pulsar_addr; 509 510 static void smp_core99_cypress_tb_freeze(int freeze) 511 { 512 u8 data; 513 int rc; 514 515 /* Strangely, the device-tree says address is 0xd2, but darwin 516 * accesses 0xd0 ... 517 */ 518 pmac_i2c_setmode(pmac_tb_clock_chip_host, 519 pmac_i2c_mode_combined); 520 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 521 0xd0 | pmac_i2c_read, 522 1, 0x81, &data, 1); 523 if (rc != 0) 524 goto bail; 525 526 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 527 528 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 529 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 530 0xd0 | pmac_i2c_write, 531 1, 0x81, &data, 1); 532 533 bail: 534 if (rc != 0) { 535 printk("Cypress Timebase %s rc: %d\n", 536 freeze ? "freeze" : "unfreeze", rc); 537 panic("Timebase freeze failed !\n"); 538 } 539 } 540 541 542 static void smp_core99_pulsar_tb_freeze(int freeze) 543 { 544 u8 data; 545 int rc; 546 547 pmac_i2c_setmode(pmac_tb_clock_chip_host, 548 pmac_i2c_mode_combined); 549 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 550 pmac_tb_pulsar_addr | pmac_i2c_read, 551 1, 0x2e, &data, 1); 552 if (rc != 0) 553 goto bail; 554 555 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 556 557 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 558 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 559 pmac_tb_pulsar_addr | pmac_i2c_write, 560 1, 0x2e, &data, 1); 561 bail: 562 if (rc != 0) { 563 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 564 freeze ? "freeze" : "unfreeze", rc); 565 panic("Timebase freeze failed !\n"); 566 } 567 } 568 569 static void __init smp_core99_setup_i2c_hwsync(int ncpus) 570 { 571 struct device_node *cc = NULL; 572 struct device_node *p; 573 const char *name = NULL; 574 const u32 *reg; 575 int ok; 576 577 /* Look for the clock chip */ 578 for_each_node_by_name(cc, "i2c-hwclock") { 579 p = of_get_parent(cc); 580 ok = p && of_device_is_compatible(p, "uni-n-i2c"); 581 of_node_put(p); 582 if (!ok) 583 continue; 584 585 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 586 if (pmac_tb_clock_chip_host == NULL) 587 continue; 588 reg = of_get_property(cc, "reg", NULL); 589 if (reg == NULL) 590 continue; 591 switch (*reg) { 592 case 0xd2: 593 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) { 594 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 595 pmac_tb_pulsar_addr = 0xd2; 596 name = "Pulsar"; 597 } else if (of_device_is_compatible(cc, "cy28508")) { 598 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 599 name = "Cypress"; 600 } 601 break; 602 case 0xd4: 603 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 604 pmac_tb_pulsar_addr = 0xd4; 605 name = "Pulsar"; 606 break; 607 } 608 if (pmac_tb_freeze != NULL) 609 break; 610 } 611 if (pmac_tb_freeze != NULL) { 612 /* Open i2c bus for synchronous access */ 613 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 614 printk(KERN_ERR "Failed top open i2c bus for clock" 615 " sync, fallback to software sync !\n"); 616 goto no_i2c_sync; 617 } 618 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 619 name); 620 return; 621 } 622 no_i2c_sync: 623 pmac_tb_freeze = NULL; 624 pmac_tb_clock_chip_host = NULL; 625 } 626 627 628 629 /* 630 * Newer G5s uses a platform function 631 */ 632 633 static void smp_core99_pfunc_tb_freeze(int freeze) 634 { 635 struct device_node *cpus; 636 struct pmf_args args; 637 638 cpus = of_find_node_by_path("/cpus"); 639 BUG_ON(cpus == NULL); 640 args.count = 1; 641 args.u[0].v = !freeze; 642 pmf_call_function(cpus, "cpu-timebase", &args); 643 of_node_put(cpus); 644 } 645 646 #else /* CONFIG_PPC64 */ 647 648 /* 649 * SMP G4 use a GPIO to enable/disable the timebase. 650 */ 651 652 static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 653 654 static void smp_core99_gpio_tb_freeze(int freeze) 655 { 656 if (freeze) 657 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 658 else 659 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 660 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 661 } 662 663 664 #endif /* !CONFIG_PPC64 */ 665 666 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 667 volatile static long int core99_l2_cache; 668 volatile static long int core99_l3_cache; 669 670 static void core99_init_caches(int cpu) 671 { 672 #ifndef CONFIG_PPC64 673 if (!cpu_has_feature(CPU_FTR_L2CR)) 674 return; 675 676 if (cpu == 0) { 677 core99_l2_cache = _get_L2CR(); 678 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 679 } else { 680 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 681 _set_L2CR(0); 682 _set_L2CR(core99_l2_cache); 683 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 684 } 685 686 if (!cpu_has_feature(CPU_FTR_L3CR)) 687 return; 688 689 if (cpu == 0){ 690 core99_l3_cache = _get_L3CR(); 691 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 692 } else { 693 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 694 _set_L3CR(0); 695 _set_L3CR(core99_l3_cache); 696 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 697 } 698 #endif /* !CONFIG_PPC64 */ 699 } 700 701 static void __init smp_core99_setup(int ncpus) 702 { 703 #ifdef CONFIG_PPC64 704 705 /* i2c based HW sync on some G5s */ 706 if (of_machine_is_compatible("PowerMac7,2") || 707 of_machine_is_compatible("PowerMac7,3") || 708 of_machine_is_compatible("RackMac3,1")) 709 smp_core99_setup_i2c_hwsync(ncpus); 710 711 /* pfunc based HW sync on recent G5s */ 712 if (pmac_tb_freeze == NULL) { 713 struct device_node *cpus = 714 of_find_node_by_path("/cpus"); 715 if (cpus && 716 of_get_property(cpus, "platform-cpu-timebase", NULL)) { 717 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 718 printk(KERN_INFO "Processor timebase sync using" 719 " platform function\n"); 720 } 721 } 722 723 #else /* CONFIG_PPC64 */ 724 725 /* GPIO based HW sync on ppc32 Core99 */ 726 if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) { 727 struct device_node *cpu; 728 const u32 *tbprop = NULL; 729 730 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 731 cpu = of_find_node_by_type(NULL, "cpu"); 732 if (cpu != NULL) { 733 tbprop = of_get_property(cpu, "timebase-enable", NULL); 734 if (tbprop) 735 core99_tb_gpio = *tbprop; 736 of_node_put(cpu); 737 } 738 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 739 printk(KERN_INFO "Processor timebase sync using" 740 " GPIO 0x%02x\n", core99_tb_gpio); 741 } 742 743 #endif /* CONFIG_PPC64 */ 744 745 /* No timebase sync, fallback to software */ 746 if (pmac_tb_freeze == NULL) { 747 smp_ops->give_timebase = smp_generic_give_timebase; 748 smp_ops->take_timebase = smp_generic_take_timebase; 749 printk(KERN_INFO "Processor timebase sync using software\n"); 750 } 751 752 #ifndef CONFIG_PPC64 753 { 754 int i; 755 756 /* XXX should get this from reg properties */ 757 for (i = 1; i < ncpus; ++i) 758 set_hard_smp_processor_id(i, i); 759 } 760 #endif 761 762 /* 32 bits SMP can't NAP */ 763 if (!of_machine_is_compatible("MacRISC4")) 764 powersave_nap = 0; 765 } 766 767 static void __init smp_core99_probe(void) 768 { 769 struct device_node *cpus; 770 int ncpus = 0; 771 772 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 773 774 /* Count CPUs in the device-tree */ 775 for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;) 776 ++ncpus; 777 778 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 779 780 /* Nothing more to do if less than 2 of them */ 781 if (ncpus <= 1) 782 return; 783 784 /* We need to perform some early initialisations before we can start 785 * setting up SMP as we are running before initcalls 786 */ 787 pmac_pfunc_base_install(); 788 pmac_i2c_init(); 789 790 /* Setup various bits like timebase sync method, ability to nap, ... */ 791 smp_core99_setup(ncpus); 792 793 /* Install IPIs */ 794 mpic_request_ipis(); 795 796 /* Collect l2cr and l3cr values from CPU 0 */ 797 core99_init_caches(0); 798 } 799 800 static int smp_core99_kick_cpu(int nr) 801 { 802 unsigned int save_vector; 803 unsigned long target, flags; 804 unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100); 805 806 if (nr < 0 || nr > 3) 807 return -ENOENT; 808 809 if (ppc_md.progress) 810 ppc_md.progress("smp_core99_kick_cpu", 0x346); 811 812 local_irq_save(flags); 813 814 /* Save reset vector */ 815 save_vector = *vector; 816 817 /* Setup fake reset vector that does 818 * b __secondary_start_pmac_0 + nr*8 819 */ 820 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 821 patch_branch(vector, target, BRANCH_SET_LINK); 822 823 /* Put some life in our friend */ 824 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 825 826 /* FIXME: We wait a bit for the CPU to take the exception, I should 827 * instead wait for the entry code to set something for me. Well, 828 * ideally, all that crap will be done in prom.c and the CPU left 829 * in a RAM-based wait loop like CHRP. 830 */ 831 mdelay(1); 832 833 /* Restore our exception vector */ 834 *vector = save_vector; 835 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); 836 837 local_irq_restore(flags); 838 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 839 840 return 0; 841 } 842 843 static void smp_core99_setup_cpu(int cpu_nr) 844 { 845 /* Setup L2/L3 */ 846 if (cpu_nr != 0) 847 core99_init_caches(cpu_nr); 848 849 /* Setup openpic */ 850 mpic_setup_this_cpu(); 851 } 852 853 #ifdef CONFIG_PPC64 854 #ifdef CONFIG_HOTPLUG_CPU 855 static int smp_core99_cpu_notify(struct notifier_block *self, 856 unsigned long action, void *hcpu) 857 { 858 int rc; 859 860 switch(action) { 861 case CPU_UP_PREPARE: 862 case CPU_UP_PREPARE_FROZEN: 863 /* Open i2c bus if it was used for tb sync */ 864 if (pmac_tb_clock_chip_host) { 865 rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1); 866 if (rc) { 867 pr_err("Failed to open i2c bus for time sync\n"); 868 return notifier_from_errno(rc); 869 } 870 } 871 break; 872 case CPU_ONLINE: 873 case CPU_UP_CANCELED: 874 /* Close i2c bus if it was used for tb sync */ 875 if (pmac_tb_clock_chip_host) 876 pmac_i2c_close(pmac_tb_clock_chip_host); 877 break; 878 default: 879 break; 880 } 881 return NOTIFY_OK; 882 } 883 884 static struct notifier_block smp_core99_cpu_nb = { 885 .notifier_call = smp_core99_cpu_notify, 886 }; 887 #endif /* CONFIG_HOTPLUG_CPU */ 888 889 static void __init smp_core99_bringup_done(void) 890 { 891 extern void g5_phy_disable_cpu1(void); 892 893 /* Close i2c bus if it was used for tb sync */ 894 if (pmac_tb_clock_chip_host) 895 pmac_i2c_close(pmac_tb_clock_chip_host); 896 897 /* If we didn't start the second CPU, we must take 898 * it off the bus. 899 */ 900 if (of_machine_is_compatible("MacRISC4") && 901 num_online_cpus() < 2) { 902 set_cpu_present(1, false); 903 g5_phy_disable_cpu1(); 904 } 905 #ifdef CONFIG_HOTPLUG_CPU 906 register_cpu_notifier(&smp_core99_cpu_nb); 907 #endif 908 909 if (ppc_md.progress) 910 ppc_md.progress("smp_core99_bringup_done", 0x349); 911 } 912 #endif /* CONFIG_PPC64 */ 913 914 #ifdef CONFIG_HOTPLUG_CPU 915 916 static int smp_core99_cpu_disable(void) 917 { 918 int rc = generic_cpu_disable(); 919 if (rc) 920 return rc; 921 922 mpic_cpu_set_priority(0xf); 923 924 return 0; 925 } 926 927 #ifdef CONFIG_PPC32 928 929 static void pmac_cpu_die(void) 930 { 931 int cpu = smp_processor_id(); 932 933 local_irq_disable(); 934 idle_task_exit(); 935 pr_debug("CPU%d offline\n", cpu); 936 generic_set_cpu_dead(cpu); 937 smp_wmb(); 938 mb(); 939 low_cpu_die(); 940 } 941 942 #else /* CONFIG_PPC32 */ 943 944 static void pmac_cpu_die(void) 945 { 946 int cpu = smp_processor_id(); 947 948 local_irq_disable(); 949 idle_task_exit(); 950 951 /* 952 * turn off as much as possible, we'll be 953 * kicked out as this will only be invoked 954 * on core99 platforms for now ... 955 */ 956 957 printk(KERN_INFO "CPU#%d offline\n", cpu); 958 generic_set_cpu_dead(cpu); 959 smp_wmb(); 960 961 /* 962 * Re-enable interrupts. The NAP code needs to enable them 963 * anyways, do it now so we deal with the case where one already 964 * happened while soft-disabled. 965 * We shouldn't get any external interrupts, only decrementer, and the 966 * decrementer handler is safe for use on offline CPUs 967 */ 968 local_irq_enable(); 969 970 while (1) { 971 /* let's not take timer interrupts too often ... */ 972 set_dec(0x7fffffff); 973 974 /* Enter NAP mode */ 975 power4_idle(); 976 } 977 } 978 979 #endif /* else CONFIG_PPC32 */ 980 #endif /* CONFIG_HOTPLUG_CPU */ 981 982 /* Core99 Macs (dual G4s and G5s) */ 983 struct smp_ops_t core99_smp_ops = { 984 .message_pass = smp_mpic_message_pass, 985 .probe = smp_core99_probe, 986 #ifdef CONFIG_PPC64 987 .bringup_done = smp_core99_bringup_done, 988 #endif 989 .kick_cpu = smp_core99_kick_cpu, 990 .setup_cpu = smp_core99_setup_cpu, 991 .give_timebase = smp_core99_give_timebase, 992 .take_timebase = smp_core99_take_timebase, 993 #if defined(CONFIG_HOTPLUG_CPU) 994 .cpu_disable = smp_core99_cpu_disable, 995 .cpu_die = generic_cpu_die, 996 #endif 997 }; 998 999 void __init pmac_setup_smp(void) 1000 { 1001 struct device_node *np; 1002 1003 /* Check for Core99 */ 1004 np = of_find_node_by_name(NULL, "uni-n"); 1005 if (!np) 1006 np = of_find_node_by_name(NULL, "u3"); 1007 if (!np) 1008 np = of_find_node_by_name(NULL, "u4"); 1009 if (np) { 1010 of_node_put(np); 1011 smp_ops = &core99_smp_ops; 1012 } 1013 #ifdef CONFIG_PPC_PMAC32_PSURGE 1014 else { 1015 /* We have to set bits in cpu_possible_mask here since the 1016 * secondary CPU(s) aren't in the device tree. Various 1017 * things won't be initialized for CPUs not in the possible 1018 * map, so we really need to fix it up here. 1019 */ 1020 int cpu; 1021 1022 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) 1023 set_cpu_possible(cpu, true); 1024 smp_ops = &psurge_smp_ops; 1025 } 1026 #endif /* CONFIG_PPC_PMAC32_PSURGE */ 1027 1028 #ifdef CONFIG_HOTPLUG_CPU 1029 ppc_md.cpu_die = pmac_cpu_die; 1030 #endif 1031 } 1032 1033 1034