1 /* 2 * Support for the interrupt controllers found on Power Macintosh, 3 * currently Apple's "Grand Central" interrupt controller in all 4 * it's incarnations. OpenPIC support used on newer machines is 5 * in a separate file 6 * 7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) 9 * IBM, Corp. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 * 16 */ 17 18 #include <linux/config.h> 19 #include <linux/stddef.h> 20 #include <linux/init.h> 21 #include <linux/sched.h> 22 #include <linux/signal.h> 23 #include <linux/pci.h> 24 #include <linux/interrupt.h> 25 #include <linux/sysdev.h> 26 #include <linux/adb.h> 27 #include <linux/pmu.h> 28 #include <linux/module.h> 29 30 #include <asm/sections.h> 31 #include <asm/io.h> 32 #include <asm/smp.h> 33 #include <asm/prom.h> 34 #include <asm/pci-bridge.h> 35 #include <asm/time.h> 36 #include <asm/pmac_feature.h> 37 #include <asm/mpic.h> 38 39 #include "pmac.h" 40 41 /* 42 * XXX this should be in xmon.h, but putting it there means xmon.h 43 * has to include <linux/interrupt.h> (to get irqreturn_t), which 44 * causes all sorts of problems. -- paulus 45 */ 46 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *); 47 48 #ifdef CONFIG_PPC32 49 struct pmac_irq_hw { 50 unsigned int event; 51 unsigned int enable; 52 unsigned int ack; 53 unsigned int level; 54 }; 55 56 /* Default addresses */ 57 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; 58 59 #define GC_LEVEL_MASK 0x3ff00000 60 #define OHARE_LEVEL_MASK 0x1ff00000 61 #define HEATHROW_LEVEL_MASK 0x1ff00000 62 63 static int max_irqs; 64 static int max_real_irqs; 65 static u32 level_mask[4]; 66 67 static DEFINE_SPINLOCK(pmac_pic_lock); 68 69 #define GATWICK_IRQ_POOL_SIZE 10 70 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE]; 71 72 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) 73 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; 74 75 /* 76 * Mark an irq as "lost". This is only used on the pmac 77 * since it can lose interrupts (see pmac_set_irq_mask). 78 * -- Cort 79 */ 80 void __set_lost(unsigned long irq_nr, int nokick) 81 { 82 if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) { 83 atomic_inc(&ppc_n_lost_interrupts); 84 if (!nokick) 85 set_dec(1); 86 } 87 } 88 89 static void pmac_mask_and_ack_irq(unsigned int irq_nr) 90 { 91 unsigned long bit = 1UL << (irq_nr & 0x1f); 92 int i = irq_nr >> 5; 93 unsigned long flags; 94 95 if ((unsigned)irq_nr >= max_irqs) 96 return; 97 98 clear_bit(irq_nr, ppc_cached_irq_mask); 99 if (test_and_clear_bit(irq_nr, ppc_lost_interrupts)) 100 atomic_dec(&ppc_n_lost_interrupts); 101 spin_lock_irqsave(&pmac_pic_lock, flags); 102 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); 103 out_le32(&pmac_irq_hw[i]->ack, bit); 104 do { 105 /* make sure ack gets to controller before we enable 106 interrupts */ 107 mb(); 108 } while((in_le32(&pmac_irq_hw[i]->enable) & bit) 109 != (ppc_cached_irq_mask[i] & bit)); 110 spin_unlock_irqrestore(&pmac_pic_lock, flags); 111 } 112 113 static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) 114 { 115 unsigned long bit = 1UL << (irq_nr & 0x1f); 116 int i = irq_nr >> 5; 117 unsigned long flags; 118 119 if ((unsigned)irq_nr >= max_irqs) 120 return; 121 122 spin_lock_irqsave(&pmac_pic_lock, flags); 123 /* enable unmasked interrupts */ 124 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); 125 126 do { 127 /* make sure mask gets to controller before we 128 return to user */ 129 mb(); 130 } while((in_le32(&pmac_irq_hw[i]->enable) & bit) 131 != (ppc_cached_irq_mask[i] & bit)); 132 133 /* 134 * Unfortunately, setting the bit in the enable register 135 * when the device interrupt is already on *doesn't* set 136 * the bit in the flag register or request another interrupt. 137 */ 138 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) 139 __set_lost((ulong)irq_nr, nokicklost); 140 spin_unlock_irqrestore(&pmac_pic_lock, flags); 141 } 142 143 /* When an irq gets requested for the first client, if it's an 144 * edge interrupt, we clear any previous one on the controller 145 */ 146 static unsigned int pmac_startup_irq(unsigned int irq_nr) 147 { 148 unsigned long bit = 1UL << (irq_nr & 0x1f); 149 int i = irq_nr >> 5; 150 151 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0) 152 out_le32(&pmac_irq_hw[i]->ack, bit); 153 set_bit(irq_nr, ppc_cached_irq_mask); 154 pmac_set_irq_mask(irq_nr, 0); 155 156 return 0; 157 } 158 159 static void pmac_mask_irq(unsigned int irq_nr) 160 { 161 clear_bit(irq_nr, ppc_cached_irq_mask); 162 pmac_set_irq_mask(irq_nr, 0); 163 mb(); 164 } 165 166 static void pmac_unmask_irq(unsigned int irq_nr) 167 { 168 set_bit(irq_nr, ppc_cached_irq_mask); 169 pmac_set_irq_mask(irq_nr, 0); 170 } 171 172 static void pmac_end_irq(unsigned int irq_nr) 173 { 174 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)) 175 && irq_desc[irq_nr].action) { 176 set_bit(irq_nr, ppc_cached_irq_mask); 177 pmac_set_irq_mask(irq_nr, 1); 178 } 179 } 180 181 182 struct hw_interrupt_type pmac_pic = { 183 .typename = " PMAC-PIC ", 184 .startup = pmac_startup_irq, 185 .enable = pmac_unmask_irq, 186 .disable = pmac_mask_irq, 187 .ack = pmac_mask_and_ack_irq, 188 .end = pmac_end_irq, 189 }; 190 191 struct hw_interrupt_type gatwick_pic = { 192 .typename = " GATWICK ", 193 .startup = pmac_startup_irq, 194 .enable = pmac_unmask_irq, 195 .disable = pmac_mask_irq, 196 .ack = pmac_mask_and_ack_irq, 197 .end = pmac_end_irq, 198 }; 199 200 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs) 201 { 202 int irq, bits; 203 204 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { 205 int i = irq >> 5; 206 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; 207 /* We must read level interrupts from the level register */ 208 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); 209 bits &= ppc_cached_irq_mask[i]; 210 if (bits == 0) 211 continue; 212 irq += __ilog2(bits); 213 __do_IRQ(irq, regs); 214 return IRQ_HANDLED; 215 } 216 printk("gatwick irq not from gatwick pic\n"); 217 return IRQ_NONE; 218 } 219 220 static int pmac_get_irq(struct pt_regs *regs) 221 { 222 int irq; 223 unsigned long bits = 0; 224 225 #ifdef CONFIG_SMP 226 void psurge_smp_message_recv(struct pt_regs *); 227 228 /* IPI's are a hack on the powersurge -- Cort */ 229 if ( smp_processor_id() != 0 ) { 230 psurge_smp_message_recv(regs); 231 return -2; /* ignore, already handled */ 232 } 233 #endif /* CONFIG_SMP */ 234 for (irq = max_real_irqs; (irq -= 32) >= 0; ) { 235 int i = irq >> 5; 236 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; 237 /* We must read level interrupts from the level register */ 238 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); 239 bits &= ppc_cached_irq_mask[i]; 240 if (bits == 0) 241 continue; 242 irq += __ilog2(bits); 243 break; 244 } 245 246 return irq; 247 } 248 249 /* This routine will fix some missing interrupt values in the device tree 250 * on the gatwick mac-io controller used by some PowerBooks 251 * 252 * Walking of OF nodes could use a bit more fixing up here, but it's not 253 * very important as this is all boot time code on static portions of the 254 * device-tree. 255 * 256 * However, the modifications done to "intrs" will have to be removed and 257 * replaced with proper updates of the "interrupts" properties or 258 * AAPL,interrupts, yet to be decided, once the dynamic parsing is there. 259 */ 260 static void __init pmac_fix_gatwick_interrupts(struct device_node *gw, 261 int irq_base) 262 { 263 struct device_node *node; 264 int count; 265 266 memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool)); 267 count = 0; 268 for (node = NULL; (node = of_get_next_child(gw, node)) != NULL;) { 269 /* Fix SCC */ 270 if ((strcasecmp(node->name, "escc") == 0) && node->child) { 271 if (node->child->n_intrs < 3) { 272 node->child->intrs = &gatwick_int_pool[count]; 273 count += 3; 274 } 275 node->child->n_intrs = 3; 276 node->child->intrs[0].line = 15+irq_base; 277 node->child->intrs[1].line = 4+irq_base; 278 node->child->intrs[2].line = 5+irq_base; 279 printk(KERN_INFO "irq: fixed SCC on gatwick" 280 " (%d,%d,%d)\n", 281 node->child->intrs[0].line, 282 node->child->intrs[1].line, 283 node->child->intrs[2].line); 284 } 285 /* Fix media-bay & left SWIM */ 286 if (strcasecmp(node->name, "media-bay") == 0) { 287 struct device_node* ya_node; 288 289 if (node->n_intrs == 0) 290 node->intrs = &gatwick_int_pool[count++]; 291 node->n_intrs = 1; 292 node->intrs[0].line = 29+irq_base; 293 printk(KERN_INFO "irq: fixed media-bay on gatwick" 294 " (%d)\n", node->intrs[0].line); 295 296 ya_node = node->child; 297 while(ya_node) { 298 if (strcasecmp(ya_node->name, "floppy") == 0) { 299 if (ya_node->n_intrs < 2) { 300 ya_node->intrs = &gatwick_int_pool[count]; 301 count += 2; 302 } 303 ya_node->n_intrs = 2; 304 ya_node->intrs[0].line = 19+irq_base; 305 ya_node->intrs[1].line = 1+irq_base; 306 printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n", 307 ya_node->intrs[0].line, ya_node->intrs[1].line); 308 } 309 if (strcasecmp(ya_node->name, "ata4") == 0) { 310 if (ya_node->n_intrs < 2) { 311 ya_node->intrs = &gatwick_int_pool[count]; 312 count += 2; 313 } 314 ya_node->n_intrs = 2; 315 ya_node->intrs[0].line = 14+irq_base; 316 ya_node->intrs[1].line = 3+irq_base; 317 printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n", 318 ya_node->intrs[0].line, ya_node->intrs[1].line); 319 } 320 ya_node = ya_node->sibling; 321 } 322 } 323 } 324 if (count > 10) { 325 printk("WARNING !! Gatwick interrupt pool overflow\n"); 326 printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE); 327 printk(" requested = %d\n", count); 328 } 329 } 330 331 /* 332 * The PowerBook 3400/2400/3500 can have a combo ethernet/modem 333 * card which includes an ohare chip that acts as a second interrupt 334 * controller. If we find this second ohare, set it up and fix the 335 * interrupt value in the device tree for the ethernet chip. 336 */ 337 static void __init enable_second_ohare(struct device_node *np) 338 { 339 unsigned char bus, devfn; 340 unsigned short cmd; 341 struct device_node *ether; 342 343 /* This code doesn't strictly belong here, it could be part of 344 * either the PCI initialisation or the feature code. It's kept 345 * here for historical reasons. 346 */ 347 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { 348 struct pci_controller* hose = 349 pci_find_hose_for_OF_device(np); 350 if (!hose) { 351 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); 352 return; 353 } 354 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); 355 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 356 cmd &= ~PCI_COMMAND_IO; 357 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); 358 } 359 360 /* Fix interrupt for the modem/ethernet combo controller. The number 361 * in the device tree (27) is bogus (correct for the ethernet-only 362 * board but not the combo ethernet/modem board). 363 * The real interrupt is 28 on the second controller -> 28+32 = 60. 364 */ 365 ether = of_find_node_by_name(NULL, "pci1011,14"); 366 if (ether && ether->n_intrs > 0) { 367 ether->intrs[0].line = 60; 368 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n", 369 ether->intrs[0].line); 370 } 371 of_node_put(ether); 372 } 373 374 #ifdef CONFIG_XMON 375 static struct irqaction xmon_action = { 376 .handler = xmon_irq, 377 .flags = 0, 378 .mask = CPU_MASK_NONE, 379 .name = "NMI - XMON" 380 }; 381 #endif 382 383 static struct irqaction gatwick_cascade_action = { 384 .handler = gatwick_action, 385 .flags = SA_INTERRUPT, 386 .mask = CPU_MASK_NONE, 387 .name = "cascade", 388 }; 389 390 static void __init pmac_pic_probe_oldstyle(void) 391 { 392 int i; 393 int irq_cascade = -1; 394 struct device_node *master = NULL; 395 struct device_node *slave = NULL; 396 u8 __iomem *addr; 397 struct resource r; 398 399 /* Set our get_irq function */ 400 ppc_md.get_irq = pmac_get_irq; 401 402 /* 403 * Find the interrupt controller type & node 404 */ 405 406 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { 407 max_irqs = max_real_irqs = 32; 408 level_mask[0] = GC_LEVEL_MASK; 409 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { 410 max_irqs = max_real_irqs = 32; 411 level_mask[0] = OHARE_LEVEL_MASK; 412 413 /* We might have a second cascaded ohare */ 414 slave = of_find_node_by_name(NULL, "pci106b,7"); 415 if (slave) { 416 max_irqs = 64; 417 level_mask[1] = OHARE_LEVEL_MASK; 418 enable_second_ohare(slave); 419 } 420 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { 421 max_irqs = max_real_irqs = 64; 422 level_mask[0] = HEATHROW_LEVEL_MASK; 423 level_mask[1] = 0; 424 425 /* We might have a second cascaded heathrow */ 426 slave = of_find_node_by_name(master, "mac-io"); 427 428 /* Check ordering of master & slave */ 429 if (device_is_compatible(master, "gatwick")) { 430 struct device_node *tmp; 431 BUG_ON(slave == NULL); 432 tmp = master; 433 master = slave; 434 slave = tmp; 435 } 436 437 /* We found a slave */ 438 if (slave) { 439 max_irqs = 128; 440 level_mask[2] = HEATHROW_LEVEL_MASK; 441 level_mask[3] = 0; 442 pmac_fix_gatwick_interrupts(slave, max_real_irqs); 443 } 444 } 445 BUG_ON(master == NULL); 446 447 /* Set the handler for the main PIC */ 448 for ( i = 0; i < max_real_irqs ; i++ ) 449 irq_desc[i].handler = &pmac_pic; 450 451 /* Get addresses of first controller if we have a node for it */ 452 BUG_ON(of_address_to_resource(master, 0, &r)); 453 454 /* Map interrupts of primary controller */ 455 addr = (u8 __iomem *) ioremap(r.start, 0x40); 456 i = 0; 457 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 458 (addr + 0x20); 459 if (max_real_irqs > 32) 460 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 461 (addr + 0x10); 462 of_node_put(master); 463 464 printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n", 465 master->full_name, max_real_irqs); 466 467 /* Map interrupts of cascaded controller */ 468 if (slave && !of_address_to_resource(slave, 0, &r)) { 469 addr = (u8 __iomem *)ioremap(r.start, 0x40); 470 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 471 (addr + 0x20); 472 if (max_irqs > 64) 473 pmac_irq_hw[i++] = 474 (volatile struct pmac_irq_hw __iomem *) 475 (addr + 0x10); 476 irq_cascade = slave->intrs[0].line; 477 478 printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs" 479 " cascade: %d\n", slave->full_name, 480 max_irqs - max_real_irqs, irq_cascade); 481 } 482 of_node_put(slave); 483 484 /* disable all interrupts in all controllers */ 485 for (i = 0; i * 32 < max_irqs; ++i) 486 out_le32(&pmac_irq_hw[i]->enable, 0); 487 488 /* mark level interrupts */ 489 for (i = 0; i < max_irqs; i++) 490 if (level_mask[i >> 5] & (1UL << (i & 0x1f))) 491 irq_desc[i].status = IRQ_LEVEL; 492 493 /* Setup handlers for secondary controller and hook cascade irq*/ 494 if (slave) { 495 for ( i = max_real_irqs ; i < max_irqs ; i++ ) 496 irq_desc[i].handler = &gatwick_pic; 497 setup_irq(irq_cascade, &gatwick_cascade_action); 498 } 499 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); 500 #ifdef CONFIG_XMON 501 setup_irq(20, &xmon_action); 502 #endif 503 } 504 #endif /* CONFIG_PPC32 */ 505 506 static int pmac_u3_cascade(struct pt_regs *regs, void *data) 507 { 508 return mpic_get_one_irq((struct mpic *)data, regs); 509 } 510 511 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) 512 { 513 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32) 514 struct device_node* pswitch; 515 int nmi_irq; 516 517 pswitch = of_find_node_by_name(NULL, "programmer-switch"); 518 if (pswitch && pswitch->n_intrs) { 519 nmi_irq = pswitch->intrs[0].line; 520 mpic_irq_set_priority(nmi_irq, 9); 521 setup_irq(nmi_irq, &xmon_action); 522 } 523 of_node_put(pswitch); 524 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ 525 } 526 527 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, 528 int master) 529 { 530 unsigned char senses[128]; 531 int offset = master ? 0 : 128; 532 int count = master ? 128 : 124; 533 const char *name = master ? " MPIC 1 " : " MPIC 2 "; 534 struct resource r; 535 struct mpic *mpic; 536 unsigned int flags = master ? MPIC_PRIMARY : 0; 537 int rc; 538 539 rc = of_address_to_resource(np, 0, &r); 540 if (rc) 541 return NULL; 542 543 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); 544 545 prom_get_irq_senses(senses, offset, offset + count); 546 547 flags |= MPIC_WANTS_RESET; 548 if (get_property(np, "big-endian", NULL)) 549 flags |= MPIC_BIG_ENDIAN; 550 551 /* Primary Big Endian means HT interrupts. This is quite dodgy 552 * but works until I find a better way 553 */ 554 if (master && (flags & MPIC_BIG_ENDIAN)) 555 flags |= MPIC_BROKEN_U3; 556 557 mpic = mpic_alloc(r.start, flags, 0, offset, count, master ? 252 : 0, 558 senses, count, name); 559 if (mpic == NULL) 560 return NULL; 561 562 mpic_init(mpic); 563 564 return mpic; 565 } 566 567 static int __init pmac_pic_probe_mpic(void) 568 { 569 struct mpic *mpic1, *mpic2; 570 struct device_node *np, *master = NULL, *slave = NULL; 571 572 /* We can have up to 2 MPICs cascaded */ 573 for (np = NULL; (np = of_find_node_by_type(np, "open-pic")) 574 != NULL;) { 575 if (master == NULL && 576 get_property(np, "interrupts", NULL) == NULL) 577 master = of_node_get(np); 578 else if (slave == NULL) 579 slave = of_node_get(np); 580 if (master && slave) 581 break; 582 } 583 584 /* Check for bogus setups */ 585 if (master == NULL && slave != NULL) { 586 master = slave; 587 slave = NULL; 588 } 589 590 /* Not found, default to good old pmac pic */ 591 if (master == NULL) 592 return -ENODEV; 593 594 /* Set master handler */ 595 ppc_md.get_irq = mpic_get_irq; 596 597 /* Setup master */ 598 mpic1 = pmac_setup_one_mpic(master, 1); 599 BUG_ON(mpic1 == NULL); 600 601 /* Install NMI if any */ 602 pmac_pic_setup_mpic_nmi(mpic1); 603 604 of_node_put(master); 605 606 /* No slave, let's go out */ 607 if (slave == NULL || slave->n_intrs < 1) 608 return 0; 609 610 mpic2 = pmac_setup_one_mpic(slave, 0); 611 if (mpic2 == NULL) { 612 printk(KERN_ERR "Failed to setup slave MPIC\n"); 613 of_node_put(slave); 614 return 0; 615 } 616 mpic_setup_cascade(slave->intrs[0].line, pmac_u3_cascade, mpic2); 617 618 of_node_put(slave); 619 return 0; 620 } 621 622 623 void __init pmac_pic_init(void) 624 { 625 /* We first try to detect Apple's new Core99 chipset, since mac-io 626 * is quite different on those machines and contains an IBM MPIC2. 627 */ 628 if (pmac_pic_probe_mpic() == 0) 629 return; 630 631 #ifdef CONFIG_PPC32 632 pmac_pic_probe_oldstyle(); 633 #endif 634 } 635 636 #if defined(CONFIG_PM) && defined(CONFIG_PPC32) 637 /* 638 * These procedures are used in implementing sleep on the powerbooks. 639 * sleep_save_intrs() saves the states of all interrupt enables 640 * and disables all interrupts except for the nominated one. 641 * sleep_restore_intrs() restores the states of all interrupt enables. 642 */ 643 unsigned long sleep_save_mask[2]; 644 645 /* This used to be passed by the PMU driver but that link got 646 * broken with the new driver model. We use this tweak for now... 647 */ 648 static int pmacpic_find_viaint(void) 649 { 650 int viaint = -1; 651 652 #ifdef CONFIG_ADB_PMU 653 struct device_node *np; 654 655 if (pmu_get_model() != PMU_OHARE_BASED) 656 goto not_found; 657 np = of_find_node_by_name(NULL, "via-pmu"); 658 if (np == NULL) 659 goto not_found; 660 viaint = np->intrs[0].line; 661 #endif /* CONFIG_ADB_PMU */ 662 663 not_found: 664 return viaint; 665 } 666 667 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state) 668 { 669 int viaint = pmacpic_find_viaint(); 670 671 sleep_save_mask[0] = ppc_cached_irq_mask[0]; 672 sleep_save_mask[1] = ppc_cached_irq_mask[1]; 673 ppc_cached_irq_mask[0] = 0; 674 ppc_cached_irq_mask[1] = 0; 675 if (viaint > 0) 676 set_bit(viaint, ppc_cached_irq_mask); 677 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); 678 if (max_real_irqs > 32) 679 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); 680 (void)in_le32(&pmac_irq_hw[0]->event); 681 /* make sure mask gets to controller before we return to caller */ 682 mb(); 683 (void)in_le32(&pmac_irq_hw[0]->enable); 684 685 return 0; 686 } 687 688 static int pmacpic_resume(struct sys_device *sysdev) 689 { 690 int i; 691 692 out_le32(&pmac_irq_hw[0]->enable, 0); 693 if (max_real_irqs > 32) 694 out_le32(&pmac_irq_hw[1]->enable, 0); 695 mb(); 696 for (i = 0; i < max_real_irqs; ++i) 697 if (test_bit(i, sleep_save_mask)) 698 pmac_unmask_irq(i); 699 700 return 0; 701 } 702 703 #endif /* CONFIG_PM && CONFIG_PPC32 */ 704 705 static struct sysdev_class pmacpic_sysclass = { 706 set_kset_name("pmac_pic"), 707 }; 708 709 static struct sys_device device_pmacpic = { 710 .id = 0, 711 .cls = &pmacpic_sysclass, 712 }; 713 714 static struct sysdev_driver driver_pmacpic = { 715 #if defined(CONFIG_PM) && defined(CONFIG_PPC32) 716 .suspend = &pmacpic_suspend, 717 .resume = &pmacpic_resume, 718 #endif /* CONFIG_PM && CONFIG_PPC32 */ 719 }; 720 721 static int __init init_pmacpic_sysfs(void) 722 { 723 #ifdef CONFIG_PPC32 724 if (max_irqs == 0) 725 return -ENODEV; 726 #endif 727 printk(KERN_DEBUG "Registering pmac pic with sysfs...\n"); 728 sysdev_class_register(&pmacpic_sysclass); 729 sysdev_register(&device_pmacpic); 730 sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic); 731 return 0; 732 } 733 734 subsys_initcall(init_pmacpic_sysfs); 735 736