1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/types.h> 3 #include <linux/init.h> 4 #include <linux/delay.h> 5 #include <linux/kernel.h> 6 #include <linux/interrupt.h> 7 #include <linux/spinlock.h> 8 #include <linux/of_irq.h> 9 10 #include <asm/pmac_feature.h> 11 #include <asm/pmac_pfunc.h> 12 13 #undef DEBUG 14 #ifdef DEBUG 15 #define DBG(fmt...) printk(fmt) 16 #else 17 #define DBG(fmt...) 18 #endif 19 20 static irqreturn_t macio_gpio_irq(int irq, void *data) 21 { 22 pmf_do_irq(data); 23 24 return IRQ_HANDLED; 25 } 26 27 static int macio_do_gpio_irq_enable(struct pmf_function *func) 28 { 29 unsigned int irq = irq_of_parse_and_map(func->node, 0); 30 if (!irq) 31 return -EINVAL; 32 return request_irq(irq, macio_gpio_irq, 0, func->node->name, func); 33 } 34 35 static int macio_do_gpio_irq_disable(struct pmf_function *func) 36 { 37 unsigned int irq = irq_of_parse_and_map(func->node, 0); 38 if (!irq) 39 return -EINVAL; 40 free_irq(irq, func); 41 return 0; 42 } 43 44 static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask) 45 { 46 u8 __iomem *addr = (u8 __iomem *)func->driver_data; 47 unsigned long flags; 48 u8 tmp; 49 50 /* Check polarity */ 51 if (args && args->count && !args->u[0].v) 52 value = ~value; 53 54 /* Toggle the GPIO */ 55 raw_spin_lock_irqsave(&feature_lock, flags); 56 tmp = readb(addr); 57 tmp = (tmp & ~mask) | (value & mask); 58 DBG("Do write 0x%02x to GPIO %pOF (%p)\n", 59 tmp, func->node, addr); 60 writeb(tmp, addr); 61 raw_spin_unlock_irqrestore(&feature_lock, flags); 62 63 return 0; 64 } 65 66 static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor) 67 { 68 u8 __iomem *addr = (u8 __iomem *)func->driver_data; 69 u32 value; 70 71 /* Check if we have room for reply */ 72 if (args == NULL || args->count == 0 || args->u[0].p == NULL) 73 return -EINVAL; 74 75 value = readb(addr); 76 *args->u[0].p = ((value & mask) >> rshift) ^ xor; 77 78 return 0; 79 } 80 81 static int macio_do_delay(PMF_STD_ARGS, u32 duration) 82 { 83 /* assume we can sleep ! */ 84 msleep((duration + 999) / 1000); 85 return 0; 86 } 87 88 static struct pmf_handlers macio_gpio_handlers = { 89 .irq_enable = macio_do_gpio_irq_enable, 90 .irq_disable = macio_do_gpio_irq_disable, 91 .write_gpio = macio_do_gpio_write, 92 .read_gpio = macio_do_gpio_read, 93 .delay = macio_do_delay, 94 }; 95 96 static void __init macio_gpio_init_one(struct macio_chip *macio) 97 { 98 struct device_node *gparent, *gp; 99 100 /* 101 * Find the "gpio" parent node 102 */ 103 104 for_each_child_of_node(macio->of_node, gparent) 105 if (of_node_name_eq(gparent, "gpio")) 106 break; 107 if (gparent == NULL) 108 return; 109 110 DBG("Installing GPIO functions for macio %pOF\n", 111 macio->of_node); 112 113 /* 114 * Ok, got one, we dont need anything special to track them down, so 115 * we just create them all 116 */ 117 for_each_child_of_node(gparent, gp) { 118 const u32 *reg = of_get_property(gp, "reg", NULL); 119 unsigned long offset; 120 if (reg == NULL) 121 continue; 122 offset = *reg; 123 /* Deal with old style device-tree. We can safely hard code the 124 * offset for now too even if it's a bit gross ... 125 */ 126 if (offset < 0x50) 127 offset += 0x50; 128 offset += (unsigned long)macio->base; 129 pmf_register_driver(gp, &macio_gpio_handlers, (void *)offset); 130 } 131 132 DBG("Calling initial GPIO functions for macio %pOF\n", 133 macio->of_node); 134 135 /* And now we run all the init ones */ 136 for_each_child_of_node(gparent, gp) 137 pmf_do_functions(gp, NULL, 0, PMF_FLAGS_ON_INIT, NULL); 138 139 of_node_put(gparent); 140 141 /* Note: We do not at this point implement the "at sleep" or "at wake" 142 * functions. I yet to find any for GPIOs anyway 143 */ 144 } 145 146 static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) 147 { 148 struct macio_chip *macio = func->driver_data; 149 unsigned long flags; 150 151 raw_spin_lock_irqsave(&feature_lock, flags); 152 MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask)); 153 raw_spin_unlock_irqrestore(&feature_lock, flags); 154 return 0; 155 } 156 157 static int macio_do_read_reg32(PMF_STD_ARGS, u32 offset) 158 { 159 struct macio_chip *macio = func->driver_data; 160 161 /* Check if we have room for reply */ 162 if (args == NULL || args->count == 0 || args->u[0].p == NULL) 163 return -EINVAL; 164 165 *args->u[0].p = MACIO_IN32(offset); 166 return 0; 167 } 168 169 static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask) 170 { 171 struct macio_chip *macio = func->driver_data; 172 unsigned long flags; 173 174 raw_spin_lock_irqsave(&feature_lock, flags); 175 MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (value & mask)); 176 raw_spin_unlock_irqrestore(&feature_lock, flags); 177 return 0; 178 } 179 180 static int macio_do_read_reg8(PMF_STD_ARGS, u32 offset) 181 { 182 struct macio_chip *macio = func->driver_data; 183 184 /* Check if we have room for reply */ 185 if (args == NULL || args->count == 0 || args->u[0].p == NULL) 186 return -EINVAL; 187 188 *((u8 *)(args->u[0].p)) = MACIO_IN8(offset); 189 return 0; 190 } 191 192 static int macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask, 193 u32 shift, u32 xor) 194 { 195 struct macio_chip *macio = func->driver_data; 196 197 /* Check if we have room for reply */ 198 if (args == NULL || args->count == 0 || args->u[0].p == NULL) 199 return -EINVAL; 200 201 *args->u[0].p = ((MACIO_IN32(offset) & mask) >> shift) ^ xor; 202 return 0; 203 } 204 205 static int macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask, 206 u32 shift, u32 xor) 207 { 208 struct macio_chip *macio = func->driver_data; 209 210 /* Check if we have room for reply */ 211 if (args == NULL || args->count == 0 || args->u[0].p == NULL) 212 return -EINVAL; 213 214 *((u8 *)(args->u[0].p)) = ((MACIO_IN8(offset) & mask) >> shift) ^ xor; 215 return 0; 216 } 217 218 static int macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift, 219 u32 mask) 220 { 221 struct macio_chip *macio = func->driver_data; 222 unsigned long flags; 223 u32 tmp, val; 224 225 /* Check args */ 226 if (args == NULL || args->count == 0) 227 return -EINVAL; 228 229 raw_spin_lock_irqsave(&feature_lock, flags); 230 tmp = MACIO_IN32(offset); 231 val = args->u[0].v << shift; 232 tmp = (tmp & ~mask) | (val & mask); 233 MACIO_OUT32(offset, tmp); 234 raw_spin_unlock_irqrestore(&feature_lock, flags); 235 return 0; 236 } 237 238 static int macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift, 239 u32 mask) 240 { 241 struct macio_chip *macio = func->driver_data; 242 unsigned long flags; 243 u32 tmp, val; 244 245 /* Check args */ 246 if (args == NULL || args->count == 0) 247 return -EINVAL; 248 249 raw_spin_lock_irqsave(&feature_lock, flags); 250 tmp = MACIO_IN8(offset); 251 val = args->u[0].v << shift; 252 tmp = (tmp & ~mask) | (val & mask); 253 MACIO_OUT8(offset, tmp); 254 raw_spin_unlock_irqrestore(&feature_lock, flags); 255 return 0; 256 } 257 258 static struct pmf_handlers macio_mmio_handlers = { 259 .write_reg32 = macio_do_write_reg32, 260 .read_reg32 = macio_do_read_reg32, 261 .write_reg8 = macio_do_write_reg8, 262 .read_reg8 = macio_do_read_reg8, 263 .read_reg32_msrx = macio_do_read_reg32_msrx, 264 .read_reg8_msrx = macio_do_read_reg8_msrx, 265 .write_reg32_slm = macio_do_write_reg32_slm, 266 .write_reg8_slm = macio_do_write_reg8_slm, 267 .delay = macio_do_delay, 268 }; 269 270 static void __init macio_mmio_init_one(struct macio_chip *macio) 271 { 272 DBG("Installing MMIO functions for macio %pOF\n", 273 macio->of_node); 274 275 pmf_register_driver(macio->of_node, &macio_mmio_handlers, macio); 276 } 277 278 static struct device_node *unin_hwclock; 279 280 static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) 281 { 282 unsigned long flags; 283 284 raw_spin_lock_irqsave(&feature_lock, flags); 285 /* This is fairly bogus in darwin, but it should work for our needs 286 * implemeted that way: 287 */ 288 UN_OUT(offset, (UN_IN(offset) & ~mask) | (value & mask)); 289 raw_spin_unlock_irqrestore(&feature_lock, flags); 290 return 0; 291 } 292 293 294 static struct pmf_handlers unin_mmio_handlers = { 295 .write_reg32 = unin_do_write_reg32, 296 .delay = macio_do_delay, 297 }; 298 299 static void __init uninorth_install_pfunc(void) 300 { 301 struct device_node *np; 302 303 DBG("Installing functions for UniN %pOF\n", 304 uninorth_node); 305 306 /* 307 * Install handlers for the bridge itself 308 */ 309 pmf_register_driver(uninorth_node, &unin_mmio_handlers, NULL); 310 pmf_do_functions(uninorth_node, NULL, 0, PMF_FLAGS_ON_INIT, NULL); 311 312 313 /* 314 * Install handlers for the hwclock child if any 315 */ 316 for (np = NULL; (np = of_get_next_child(uninorth_node, np)) != NULL;) 317 if (of_node_name_eq(np, "hw-clock")) { 318 unin_hwclock = np; 319 break; 320 } 321 if (unin_hwclock) { 322 DBG("Installing functions for UniN clock %pOF\n", 323 unin_hwclock); 324 pmf_register_driver(unin_hwclock, &unin_mmio_handlers, NULL); 325 pmf_do_functions(unin_hwclock, NULL, 0, PMF_FLAGS_ON_INIT, 326 NULL); 327 } 328 } 329 330 /* We export this as the SMP code might init us early */ 331 int __init pmac_pfunc_base_install(void) 332 { 333 static int pfbase_inited; 334 int i; 335 336 if (pfbase_inited) 337 return 0; 338 pfbase_inited = 1; 339 340 if (!machine_is(powermac)) 341 return 0; 342 343 DBG("Installing base platform functions...\n"); 344 345 /* 346 * Locate mac-io chips and install handlers 347 */ 348 for (i = 0 ; i < MAX_MACIO_CHIPS; i++) { 349 if (macio_chips[i].of_node) { 350 macio_mmio_init_one(&macio_chips[i]); 351 macio_gpio_init_one(&macio_chips[i]); 352 } 353 } 354 355 /* 356 * Install handlers for northbridge and direct mapped hwclock 357 * if any. We do not implement the config space access callback 358 * which is only ever used for functions that we do not call in 359 * the current driver (enabling/disabling cells in U2, mostly used 360 * to restore the PCI settings, we do that differently) 361 */ 362 if (uninorth_node && uninorth_base) 363 uninorth_install_pfunc(); 364 365 DBG("All base functions installed\n"); 366 367 return 0; 368 } 369 machine_arch_initcall(powermac, pmac_pfunc_base_install); 370 371 #ifdef CONFIG_PM 372 373 /* Those can be called by pmac_feature. Ultimately, I should use a sysdev 374 * or a device, but for now, that's good enough until I sort out some 375 * ordering issues. Also, we do not bother with GPIOs, as so far I yet have 376 * to see a case where a GPIO function has the on-suspend or on-resume bit 377 */ 378 void pmac_pfunc_base_suspend(void) 379 { 380 int i; 381 382 for (i = 0 ; i < MAX_MACIO_CHIPS; i++) { 383 if (macio_chips[i].of_node) 384 pmf_do_functions(macio_chips[i].of_node, NULL, 0, 385 PMF_FLAGS_ON_SLEEP, NULL); 386 } 387 if (uninorth_node) 388 pmf_do_functions(uninorth_node, NULL, 0, 389 PMF_FLAGS_ON_SLEEP, NULL); 390 if (unin_hwclock) 391 pmf_do_functions(unin_hwclock, NULL, 0, 392 PMF_FLAGS_ON_SLEEP, NULL); 393 } 394 395 void pmac_pfunc_base_resume(void) 396 { 397 int i; 398 399 if (unin_hwclock) 400 pmf_do_functions(unin_hwclock, NULL, 0, 401 PMF_FLAGS_ON_WAKE, NULL); 402 if (uninorth_node) 403 pmf_do_functions(uninorth_node, NULL, 0, 404 PMF_FLAGS_ON_WAKE, NULL); 405 for (i = 0 ; i < MAX_MACIO_CHIPS; i++) { 406 if (macio_chips[i].of_node) 407 pmf_do_functions(macio_chips[i].of_node, NULL, 0, 408 PMF_FLAGS_ON_WAKE, NULL); 409 } 410 } 411 412 #endif /* CONFIG_PM */ 413