1 /* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/bootmem.h> 19 #include <linux/irq.h> 20 21 #include <asm/sections.h> 22 #include <asm/io.h> 23 #include <asm/prom.h> 24 #include <asm/pci-bridge.h> 25 #include <asm/machdep.h> 26 #include <asm/pmac_feature.h> 27 #include <asm/grackle.h> 28 #include <asm/ppc-pci.h> 29 30 #undef DEBUG 31 32 #ifdef DEBUG 33 #define DBG(x...) printk(x) 34 #else 35 #define DBG(x...) 36 #endif 37 38 static int add_bridge(struct device_node *dev); 39 40 /* XXX Could be per-controller, but I don't think we risk anything by 41 * assuming we won't have both UniNorth and Bandit */ 42 static int has_uninorth; 43 #ifdef CONFIG_PPC64 44 static struct pci_controller *u3_agp; 45 static struct pci_controller *u4_pcie; 46 static struct pci_controller *u3_ht; 47 #else 48 static int has_second_ohare; 49 #endif /* CONFIG_PPC64 */ 50 51 extern int pcibios_assign_bus_offset; 52 53 struct device_node *k2_skiplist[2]; 54 55 /* 56 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 57 */ 58 #define BANDIT_DEVID_2 8 59 #define BANDIT_REVID 3 60 61 #define BANDIT_DEVNUM 11 62 #define BANDIT_MAGIC 0x50 63 #define BANDIT_COHERENT 0x40 64 65 static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 66 { 67 for (; node != 0;node = node->sibling) { 68 const int * bus_range; 69 const unsigned int *class_code; 70 int len; 71 72 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 73 class_code = of_get_property(node, "class-code", NULL); 74 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 75 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 76 continue; 77 bus_range = of_get_property(node, "bus-range", &len); 78 if (bus_range != NULL && len > 2 * sizeof(int)) { 79 if (bus_range[1] > higher) 80 higher = bus_range[1]; 81 } 82 higher = fixup_one_level_bus_range(node->child, higher); 83 } 84 return higher; 85 } 86 87 /* This routine fixes the "bus-range" property of all bridges in the 88 * system since they tend to have their "last" member wrong on macs 89 * 90 * Note that the bus numbers manipulated here are OF bus numbers, they 91 * are not Linux bus numbers. 92 */ 93 static void __init fixup_bus_range(struct device_node *bridge) 94 { 95 int *bus_range, len; 96 struct property *prop; 97 98 /* Lookup the "bus-range" property for the hose */ 99 prop = of_find_property(bridge, "bus-range", &len); 100 if (prop == NULL || prop->length < 2 * sizeof(int)) 101 return; 102 103 bus_range = prop->value; 104 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 105 } 106 107 /* 108 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 109 * 110 * The "Bandit" version is present in all early PCI PowerMacs, 111 * and up to the first ones using Grackle. Some machines may 112 * have 2 bandit controllers (2 PCI busses). 113 * 114 * "Chaos" is used in some "Bandit"-type machines as a bridge 115 * for the separate display bus. It is accessed the same 116 * way as bandit, but cannot be probed for devices. It therefore 117 * has its own config access functions. 118 * 119 * The "UniNorth" version is present in all Core99 machines 120 * (iBook, G4, new IMacs, and all the recent Apple machines). 121 * It contains 3 controllers in one ASIC. 122 * 123 * The U3 is the bridge used on G5 machines. It contains an 124 * AGP bus which is dealt with the old UniNorth access routines 125 * and a HyperTransport bus which uses its own set of access 126 * functions. 127 */ 128 129 #define MACRISC_CFA0(devfn, off) \ 130 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ 131 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 132 | (((unsigned int)(off)) & 0xFCUL)) 133 134 #define MACRISC_CFA1(bus, devfn, off) \ 135 ((((unsigned int)(bus)) << 16) \ 136 |(((unsigned int)(devfn)) << 8) \ 137 |(((unsigned int)(off)) & 0xFCUL) \ 138 |1UL) 139 140 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, 141 u8 bus, u8 dev_fn, u8 offset) 142 { 143 unsigned int caddr; 144 145 if (bus == hose->first_busno) { 146 if (dev_fn < (11 << 3)) 147 return NULL; 148 caddr = MACRISC_CFA0(dev_fn, offset); 149 } else 150 caddr = MACRISC_CFA1(bus, dev_fn, offset); 151 152 /* Uninorth will return garbage if we don't read back the value ! */ 153 do { 154 out_le32(hose->cfg_addr, caddr); 155 } while (in_le32(hose->cfg_addr) != caddr); 156 157 offset &= has_uninorth ? 0x07 : 0x03; 158 return hose->cfg_data + offset; 159 } 160 161 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, 162 int offset, int len, u32 *val) 163 { 164 struct pci_controller *hose; 165 volatile void __iomem *addr; 166 167 hose = pci_bus_to_host(bus); 168 if (hose == NULL) 169 return PCIBIOS_DEVICE_NOT_FOUND; 170 if (offset >= 0x100) 171 return PCIBIOS_BAD_REGISTER_NUMBER; 172 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 173 if (!addr) 174 return PCIBIOS_DEVICE_NOT_FOUND; 175 /* 176 * Note: the caller has already checked that offset is 177 * suitably aligned and that len is 1, 2 or 4. 178 */ 179 switch (len) { 180 case 1: 181 *val = in_8(addr); 182 break; 183 case 2: 184 *val = in_le16(addr); 185 break; 186 default: 187 *val = in_le32(addr); 188 break; 189 } 190 return PCIBIOS_SUCCESSFUL; 191 } 192 193 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, 194 int offset, int len, u32 val) 195 { 196 struct pci_controller *hose; 197 volatile void __iomem *addr; 198 199 hose = pci_bus_to_host(bus); 200 if (hose == NULL) 201 return PCIBIOS_DEVICE_NOT_FOUND; 202 if (offset >= 0x100) 203 return PCIBIOS_BAD_REGISTER_NUMBER; 204 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 205 if (!addr) 206 return PCIBIOS_DEVICE_NOT_FOUND; 207 /* 208 * Note: the caller has already checked that offset is 209 * suitably aligned and that len is 1, 2 or 4. 210 */ 211 switch (len) { 212 case 1: 213 out_8(addr, val); 214 (void) in_8(addr); 215 break; 216 case 2: 217 out_le16(addr, val); 218 (void) in_le16(addr); 219 break; 220 default: 221 out_le32(addr, val); 222 (void) in_le32(addr); 223 break; 224 } 225 return PCIBIOS_SUCCESSFUL; 226 } 227 228 static struct pci_ops macrisc_pci_ops = 229 { 230 macrisc_read_config, 231 macrisc_write_config 232 }; 233 234 #ifdef CONFIG_PPC32 235 /* 236 * Verify that a specific (bus, dev_fn) exists on chaos 237 */ 238 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 239 { 240 struct device_node *np; 241 const u32 *vendor, *device; 242 243 if (offset >= 0x100) 244 return PCIBIOS_BAD_REGISTER_NUMBER; 245 np = pci_busdev_to_OF_node(bus, devfn); 246 if (np == NULL) 247 return PCIBIOS_DEVICE_NOT_FOUND; 248 249 vendor = of_get_property(np, "vendor-id", NULL); 250 device = of_get_property(np, "device-id", NULL); 251 if (vendor == NULL || device == NULL) 252 return PCIBIOS_DEVICE_NOT_FOUND; 253 254 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 255 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 256 return PCIBIOS_BAD_REGISTER_NUMBER; 257 258 return PCIBIOS_SUCCESSFUL; 259 } 260 261 static int 262 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 263 int len, u32 *val) 264 { 265 int result = chaos_validate_dev(bus, devfn, offset); 266 if (result == PCIBIOS_BAD_REGISTER_NUMBER) 267 *val = ~0U; 268 if (result != PCIBIOS_SUCCESSFUL) 269 return result; 270 return macrisc_read_config(bus, devfn, offset, len, val); 271 } 272 273 static int 274 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 275 int len, u32 val) 276 { 277 int result = chaos_validate_dev(bus, devfn, offset); 278 if (result != PCIBIOS_SUCCESSFUL) 279 return result; 280 return macrisc_write_config(bus, devfn, offset, len, val); 281 } 282 283 static struct pci_ops chaos_pci_ops = 284 { 285 chaos_read_config, 286 chaos_write_config 287 }; 288 289 static void __init setup_chaos(struct pci_controller *hose, 290 struct resource *addr) 291 { 292 /* assume a `chaos' bridge */ 293 hose->ops = &chaos_pci_ops; 294 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 295 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 296 } 297 #endif /* CONFIG_PPC32 */ 298 299 #ifdef CONFIG_PPC64 300 /* 301 * These versions of U3 HyperTransport config space access ops do not 302 * implement self-view of the HT host yet 303 */ 304 305 /* 306 * This function deals with some "special cases" devices. 307 * 308 * 0 -> No special case 309 * 1 -> Skip the device but act as if the access was successfull 310 * (return 0xff's on reads, eventually, cache config space 311 * accesses in a later version) 312 * -1 -> Hide the device (unsuccessful acess) 313 */ 314 static int u3_ht_skip_device(struct pci_controller *hose, 315 struct pci_bus *bus, unsigned int devfn) 316 { 317 struct device_node *busdn, *dn; 318 int i; 319 320 /* We only allow config cycles to devices that are in OF device-tree 321 * as we are apparently having some weird things going on with some 322 * revs of K2 on recent G5s 323 */ 324 if (bus->self) 325 busdn = pci_device_to_OF_node(bus->self); 326 else 327 busdn = hose->arch_data; 328 for (dn = busdn->child; dn; dn = dn->sibling) 329 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) 330 break; 331 if (dn == NULL) 332 return -1; 333 334 /* 335 * When a device in K2 is powered down, we die on config 336 * cycle accesses. Fix that here. 337 */ 338 for (i=0; i<2; i++) 339 if (k2_skiplist[i] == dn) 340 return 1; 341 342 return 0; 343 } 344 345 #define U3_HT_CFA0(devfn, off) \ 346 ((((unsigned int)devfn) << 8) | offset) 347 #define U3_HT_CFA1(bus, devfn, off) \ 348 (U3_HT_CFA0(devfn, off) \ 349 + (((unsigned int)bus) << 16) \ 350 + 0x01000000UL) 351 352 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, 353 u8 bus, u8 devfn, u8 offset) 354 { 355 if (bus == hose->first_busno) { 356 /* For now, we don't self probe U3 HT bridge */ 357 if (PCI_SLOT(devfn) == 0) 358 return NULL; 359 return hose->cfg_data + U3_HT_CFA0(devfn, offset); 360 } else 361 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); 362 } 363 364 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 365 int offset, int len, u32 *val) 366 { 367 struct pci_controller *hose; 368 volatile void __iomem *addr; 369 370 hose = pci_bus_to_host(bus); 371 if (hose == NULL) 372 return PCIBIOS_DEVICE_NOT_FOUND; 373 if (offset >= 0x100) 374 return PCIBIOS_BAD_REGISTER_NUMBER; 375 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 376 if (!addr) 377 return PCIBIOS_DEVICE_NOT_FOUND; 378 379 switch (u3_ht_skip_device(hose, bus, devfn)) { 380 case 0: 381 break; 382 case 1: 383 switch (len) { 384 case 1: 385 *val = 0xff; break; 386 case 2: 387 *val = 0xffff; break; 388 default: 389 *val = 0xfffffffful; break; 390 } 391 return PCIBIOS_SUCCESSFUL; 392 default: 393 return PCIBIOS_DEVICE_NOT_FOUND; 394 } 395 396 /* 397 * Note: the caller has already checked that offset is 398 * suitably aligned and that len is 1, 2 or 4. 399 */ 400 switch (len) { 401 case 1: 402 *val = in_8(addr); 403 break; 404 case 2: 405 *val = in_le16(addr); 406 break; 407 default: 408 *val = in_le32(addr); 409 break; 410 } 411 return PCIBIOS_SUCCESSFUL; 412 } 413 414 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 415 int offset, int len, u32 val) 416 { 417 struct pci_controller *hose; 418 volatile void __iomem *addr; 419 420 hose = pci_bus_to_host(bus); 421 if (hose == NULL) 422 return PCIBIOS_DEVICE_NOT_FOUND; 423 if (offset >= 0x100) 424 return PCIBIOS_BAD_REGISTER_NUMBER; 425 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 426 if (!addr) 427 return PCIBIOS_DEVICE_NOT_FOUND; 428 429 switch (u3_ht_skip_device(hose, bus, devfn)) { 430 case 0: 431 break; 432 case 1: 433 return PCIBIOS_SUCCESSFUL; 434 default: 435 return PCIBIOS_DEVICE_NOT_FOUND; 436 } 437 438 /* 439 * Note: the caller has already checked that offset is 440 * suitably aligned and that len is 1, 2 or 4. 441 */ 442 switch (len) { 443 case 1: 444 out_8(addr, val); 445 (void) in_8(addr); 446 break; 447 case 2: 448 out_le16(addr, val); 449 (void) in_le16(addr); 450 break; 451 default: 452 out_le32((u32 __iomem *)addr, val); 453 (void) in_le32(addr); 454 break; 455 } 456 return PCIBIOS_SUCCESSFUL; 457 } 458 459 static struct pci_ops u3_ht_pci_ops = 460 { 461 u3_ht_read_config, 462 u3_ht_write_config 463 }; 464 465 #define U4_PCIE_CFA0(devfn, off) \ 466 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ 467 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 468 | ((((unsigned int)(off)) >> 8) << 28) \ 469 | (((unsigned int)(off)) & 0xfcU)) 470 471 #define U4_PCIE_CFA1(bus, devfn, off) \ 472 ((((unsigned int)(bus)) << 16) \ 473 |(((unsigned int)(devfn)) << 8) \ 474 | ((((unsigned int)(off)) >> 8) << 28) \ 475 |(((unsigned int)(off)) & 0xfcU) \ 476 |1UL) 477 478 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 479 u8 bus, u8 dev_fn, int offset) 480 { 481 unsigned int caddr; 482 483 if (bus == hose->first_busno) { 484 caddr = U4_PCIE_CFA0(dev_fn, offset); 485 } else 486 caddr = U4_PCIE_CFA1(bus, dev_fn, offset); 487 488 /* Uninorth will return garbage if we don't read back the value ! */ 489 do { 490 out_le32(hose->cfg_addr, caddr); 491 } while (in_le32(hose->cfg_addr) != caddr); 492 493 offset &= 0x03; 494 return hose->cfg_data + offset; 495 } 496 497 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 498 int offset, int len, u32 *val) 499 { 500 struct pci_controller *hose; 501 volatile void __iomem *addr; 502 503 hose = pci_bus_to_host(bus); 504 if (hose == NULL) 505 return PCIBIOS_DEVICE_NOT_FOUND; 506 if (offset >= 0x1000) 507 return PCIBIOS_BAD_REGISTER_NUMBER; 508 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 509 if (!addr) 510 return PCIBIOS_DEVICE_NOT_FOUND; 511 /* 512 * Note: the caller has already checked that offset is 513 * suitably aligned and that len is 1, 2 or 4. 514 */ 515 switch (len) { 516 case 1: 517 *val = in_8(addr); 518 break; 519 case 2: 520 *val = in_le16(addr); 521 break; 522 default: 523 *val = in_le32(addr); 524 break; 525 } 526 return PCIBIOS_SUCCESSFUL; 527 } 528 529 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 530 int offset, int len, u32 val) 531 { 532 struct pci_controller *hose; 533 volatile void __iomem *addr; 534 535 hose = pci_bus_to_host(bus); 536 if (hose == NULL) 537 return PCIBIOS_DEVICE_NOT_FOUND; 538 if (offset >= 0x1000) 539 return PCIBIOS_BAD_REGISTER_NUMBER; 540 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 541 if (!addr) 542 return PCIBIOS_DEVICE_NOT_FOUND; 543 /* 544 * Note: the caller has already checked that offset is 545 * suitably aligned and that len is 1, 2 or 4. 546 */ 547 switch (len) { 548 case 1: 549 out_8(addr, val); 550 (void) in_8(addr); 551 break; 552 case 2: 553 out_le16(addr, val); 554 (void) in_le16(addr); 555 break; 556 default: 557 out_le32(addr, val); 558 (void) in_le32(addr); 559 break; 560 } 561 return PCIBIOS_SUCCESSFUL; 562 } 563 564 static struct pci_ops u4_pcie_pci_ops = 565 { 566 u4_pcie_read_config, 567 u4_pcie_write_config 568 }; 569 570 #endif /* CONFIG_PPC64 */ 571 572 #ifdef CONFIG_PPC32 573 /* 574 * For a bandit bridge, turn on cache coherency if necessary. 575 * N.B. we could clean this up using the hose ops directly. 576 */ 577 static void __init init_bandit(struct pci_controller *bp) 578 { 579 unsigned int vendev, magic; 580 int rev; 581 582 /* read the word at offset 0 in config space for device 11 */ 583 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 584 udelay(2); 585 vendev = in_le32(bp->cfg_data); 586 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 587 PCI_VENDOR_ID_APPLE) { 588 /* read the revision id */ 589 out_le32(bp->cfg_addr, 590 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 591 udelay(2); 592 rev = in_8(bp->cfg_data); 593 if (rev != BANDIT_REVID) 594 printk(KERN_WARNING 595 "Unknown revision %d for bandit\n", rev); 596 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 597 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 598 return; 599 } 600 601 /* read the word at offset 0x50 */ 602 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 603 udelay(2); 604 magic = in_le32(bp->cfg_data); 605 if ((magic & BANDIT_COHERENT) != 0) 606 return; 607 magic |= BANDIT_COHERENT; 608 udelay(2); 609 out_le32(bp->cfg_data, magic); 610 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 611 } 612 613 /* 614 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 615 */ 616 static void __init init_p2pbridge(void) 617 { 618 struct device_node *p2pbridge; 619 struct pci_controller* hose; 620 u8 bus, devfn; 621 u16 val; 622 623 /* XXX it would be better here to identify the specific 624 PCI-PCI bridge chip we have. */ 625 if ((p2pbridge = find_devices("pci-bridge")) == 0 626 || p2pbridge->parent == NULL 627 || strcmp(p2pbridge->parent->name, "pci") != 0) 628 return; 629 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 630 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 631 return; 632 } 633 /* Warning: At this point, we have not yet renumbered all busses. 634 * So we must use OF walking to find out hose 635 */ 636 hose = pci_find_hose_for_OF_device(p2pbridge); 637 if (!hose) { 638 DBG("Can't find hose for PCI<->PCI bridge\n"); 639 return; 640 } 641 if (early_read_config_word(hose, bus, devfn, 642 PCI_BRIDGE_CONTROL, &val) < 0) { 643 printk(KERN_ERR "init_p2pbridge: couldn't read bridge" 644 " control\n"); 645 return; 646 } 647 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 648 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 649 } 650 651 static void __init init_second_ohare(void) 652 { 653 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); 654 unsigned char bus, devfn; 655 unsigned short cmd; 656 657 if (np == NULL) 658 return; 659 660 /* This must run before we initialize the PICs since the second 661 * ohare hosts a PIC that will be accessed there. 662 */ 663 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { 664 struct pci_controller* hose = 665 pci_find_hose_for_OF_device(np); 666 if (!hose) { 667 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); 668 return; 669 } 670 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); 671 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 672 cmd &= ~PCI_COMMAND_IO; 673 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); 674 } 675 has_second_ohare = 1; 676 } 677 678 /* 679 * Some Apple desktop machines have a NEC PD720100A USB2 controller 680 * on the motherboard. Open Firmware, on these, will disable the 681 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 682 * code re-enables it ;) 683 */ 684 static void __init fixup_nec_usb2(void) 685 { 686 struct device_node *nec; 687 688 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { 689 struct pci_controller *hose; 690 u32 data; 691 const u32 *prop; 692 u8 bus, devfn; 693 694 prop = of_get_property(nec, "vendor-id", NULL); 695 if (prop == NULL) 696 continue; 697 if (0x1033 != *prop) 698 continue; 699 prop = of_get_property(nec, "device-id", NULL); 700 if (prop == NULL) 701 continue; 702 if (0x0035 != *prop) 703 continue; 704 prop = of_get_property(nec, "reg", NULL); 705 if (prop == NULL) 706 continue; 707 devfn = (prop[0] >> 8) & 0xff; 708 bus = (prop[0] >> 16) & 0xff; 709 if (PCI_FUNC(devfn) != 0) 710 continue; 711 hose = pci_find_hose_for_OF_device(nec); 712 if (!hose) 713 continue; 714 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 715 if (data & 1UL) { 716 printk("Found NEC PD720100A USB2 chip with disabled" 717 " EHCI, fixing up...\n"); 718 data &= ~1UL; 719 early_write_config_dword(hose, bus, devfn, 0xe4, data); 720 } 721 } 722 } 723 724 static void __init setup_bandit(struct pci_controller *hose, 725 struct resource *addr) 726 { 727 hose->ops = ¯isc_pci_ops; 728 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 729 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 730 init_bandit(hose); 731 } 732 733 static int __init setup_uninorth(struct pci_controller *hose, 734 struct resource *addr) 735 { 736 pci_assign_all_buses = 1; 737 has_uninorth = 1; 738 hose->ops = ¯isc_pci_ops; 739 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 740 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 741 /* We "know" that the bridge at f2000000 has the PCI slots. */ 742 return addr->start == 0xf2000000; 743 } 744 #endif /* CONFIG_PPC32 */ 745 746 #ifdef CONFIG_PPC64 747 static void __init setup_u3_agp(struct pci_controller* hose) 748 { 749 /* On G5, we move AGP up to high bus number so we don't need 750 * to reassign bus numbers for HT. If we ever have P2P bridges 751 * on AGP, we'll have to move pci_assign_all_busses to the 752 * pci_controller structure so we enable it for AGP and not for 753 * HT childs. 754 * We hard code the address because of the different size of 755 * the reg address cell, we shall fix that by killing struct 756 * reg_property and using some accessor functions instead 757 */ 758 hose->first_busno = 0xf0; 759 hose->last_busno = 0xff; 760 has_uninorth = 1; 761 hose->ops = ¯isc_pci_ops; 762 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 763 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 764 u3_agp = hose; 765 } 766 767 static void __init setup_u4_pcie(struct pci_controller* hose) 768 { 769 /* We currently only implement the "non-atomic" config space, to 770 * be optimised later. 771 */ 772 hose->ops = &u4_pcie_pci_ops; 773 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 774 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 775 776 /* The bus contains a bridge from root -> device, we need to 777 * make it visible on bus 0 so that we pick the right type 778 * of config cycles. If we didn't, we would have to force all 779 * config cycles to be type 1. So we override the "bus-range" 780 * property here 781 */ 782 hose->first_busno = 0x00; 783 hose->last_busno = 0xff; 784 u4_pcie = hose; 785 } 786 787 static void __init setup_u3_ht(struct pci_controller* hose) 788 { 789 struct device_node *np = (struct device_node *)hose->arch_data; 790 struct pci_controller *other = NULL; 791 int i, cur; 792 793 794 hose->ops = &u3_ht_pci_ops; 795 796 /* We hard code the address because of the different size of 797 * the reg address cell, we shall fix that by killing struct 798 * reg_property and using some accessor functions instead 799 */ 800 hose->cfg_data = ioremap(0xf2000000, 0x02000000); 801 802 /* 803 * /ht node doesn't expose a "ranges" property, so we "remove" 804 * regions that have been allocated to AGP. So far, this version of 805 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions 806 * to /ht. We need to fix that sooner or later by either parsing all 807 * child "ranges" properties or figuring out the U3 address space 808 * decoding logic and then read its configuration register (if any). 809 */ 810 hose->io_base_phys = 0xf4000000; 811 hose->pci_io_size = 0x00400000; 812 hose->io_resource.name = np->full_name; 813 hose->io_resource.start = 0; 814 hose->io_resource.end = 0x003fffff; 815 hose->io_resource.flags = IORESOURCE_IO; 816 hose->pci_mem_offset = 0; 817 hose->first_busno = 0; 818 hose->last_busno = 0xef; 819 hose->mem_resources[0].name = np->full_name; 820 hose->mem_resources[0].start = 0x80000000; 821 hose->mem_resources[0].end = 0xefffffff; 822 hose->mem_resources[0].flags = IORESOURCE_MEM; 823 824 u3_ht = hose; 825 826 if (u3_agp != NULL) 827 other = u3_agp; 828 else if (u4_pcie != NULL) 829 other = u4_pcie; 830 831 if (other == NULL) { 832 DBG("U3/4 has no AGP/PCIE, using full resource range\n"); 833 return; 834 } 835 836 /* Fixup bus range vs. PCIE */ 837 if (u4_pcie) 838 hose->last_busno = u4_pcie->first_busno - 1; 839 840 /* We "remove" the AGP resources from the resources allocated to HT, 841 * that is we create "holes". However, that code does assumptions 842 * that so far happen to be true (cross fingers...), typically that 843 * resources in the AGP node are properly ordered 844 */ 845 cur = 0; 846 for (i=0; i<3; i++) { 847 struct resource *res = &other->mem_resources[i]; 848 if (res->flags != IORESOURCE_MEM) 849 continue; 850 /* We don't care about "fine" resources */ 851 if (res->start >= 0xf0000000) 852 continue; 853 /* Check if it's just a matter of "shrinking" us in one 854 * direction 855 */ 856 if (hose->mem_resources[cur].start == res->start) { 857 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", 858 cur, hose->mem_resources[cur].start, 859 res->end + 1); 860 hose->mem_resources[cur].start = res->end + 1; 861 continue; 862 } 863 if (hose->mem_resources[cur].end == res->end) { 864 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", 865 cur, hose->mem_resources[cur].end, 866 res->start - 1); 867 hose->mem_resources[cur].end = res->start - 1; 868 continue; 869 } 870 /* No, it's not the case, we need a hole */ 871 if (cur == 2) { 872 /* not enough resources for a hole, we drop part 873 * of the range 874 */ 875 printk(KERN_WARNING "Running out of resources" 876 " for /ht host !\n"); 877 hose->mem_resources[cur].end = res->start - 1; 878 continue; 879 } 880 cur++; 881 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", 882 cur-1, res->start - 1, cur, res->end + 1); 883 hose->mem_resources[cur].name = np->full_name; 884 hose->mem_resources[cur].flags = IORESOURCE_MEM; 885 hose->mem_resources[cur].start = res->end + 1; 886 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; 887 hose->mem_resources[cur-1].end = res->start - 1; 888 } 889 } 890 #endif /* CONFIG_PPC64 */ 891 892 /* 893 * We assume that if we have a G3 powermac, we have one bridge called 894 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 895 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 896 */ 897 static int __init add_bridge(struct device_node *dev) 898 { 899 int len; 900 struct pci_controller *hose; 901 struct resource rsrc; 902 char *disp_name; 903 const int *bus_range; 904 int primary = 1, has_address = 0; 905 906 DBG("Adding PCI host bridge %s\n", dev->full_name); 907 908 /* Fetch host bridge registers address */ 909 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 910 911 /* Get bus range if any */ 912 bus_range = of_get_property(dev, "bus-range", &len); 913 if (bus_range == NULL || len < 2 * sizeof(int)) { 914 printk(KERN_WARNING "Can't get bus-range for %s, assume" 915 " bus 0\n", dev->full_name); 916 } 917 918 /* XXX Different prototypes, to be merged */ 919 #ifdef CONFIG_PPC64 920 hose = pcibios_alloc_controller(dev); 921 #else 922 hose = pcibios_alloc_controller(); 923 #endif 924 if (!hose) 925 return -ENOMEM; 926 hose->arch_data = dev; 927 hose->first_busno = bus_range ? bus_range[0] : 0; 928 hose->last_busno = bus_range ? bus_range[1] : 0xff; 929 930 disp_name = NULL; 931 932 /* 64 bits only bridges */ 933 #ifdef CONFIG_PPC64 934 if (device_is_compatible(dev, "u3-agp")) { 935 setup_u3_agp(hose); 936 disp_name = "U3-AGP"; 937 primary = 0; 938 } else if (device_is_compatible(dev, "u3-ht")) { 939 setup_u3_ht(hose); 940 disp_name = "U3-HT"; 941 primary = 1; 942 } else if (device_is_compatible(dev, "u4-pcie")) { 943 setup_u4_pcie(hose); 944 disp_name = "U4-PCIE"; 945 primary = 0; 946 } 947 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" 948 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); 949 #endif /* CONFIG_PPC64 */ 950 951 /* 32 bits only bridges */ 952 #ifdef CONFIG_PPC32 953 if (device_is_compatible(dev, "uni-north")) { 954 primary = setup_uninorth(hose, &rsrc); 955 disp_name = "UniNorth"; 956 } else if (strcmp(dev->name, "pci") == 0) { 957 /* XXX assume this is a mpc106 (grackle) */ 958 setup_grackle(hose); 959 disp_name = "Grackle (MPC106)"; 960 } else if (strcmp(dev->name, "bandit") == 0) { 961 setup_bandit(hose, &rsrc); 962 disp_name = "Bandit"; 963 } else if (strcmp(dev->name, "chaos") == 0) { 964 setup_chaos(hose, &rsrc); 965 disp_name = "Chaos"; 966 primary = 0; 967 } 968 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " 969 "Firmware bus number: %d->%d\n", 970 disp_name, (unsigned long long)rsrc.start, hose->first_busno, 971 hose->last_busno); 972 #endif /* CONFIG_PPC32 */ 973 974 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 975 hose, hose->cfg_addr, hose->cfg_data); 976 977 /* Interpret the "ranges" property */ 978 /* This also maps the I/O region and sets isa_io/mem_base */ 979 pci_process_bridge_OF_ranges(hose, dev, primary); 980 981 /* Fixup "bus-range" OF property */ 982 fixup_bus_range(dev); 983 984 return 0; 985 } 986 987 void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) 988 { 989 #ifdef CONFIG_PPC32 990 /* Fixup interrupt for the modem/ethernet combo controller. 991 * on machines with a second ohare chip. 992 * The number in the device tree (27) is bogus (correct for 993 * the ethernet-only board but not the combo ethernet/modem 994 * board). The real interrupt is 28 on the second controller 995 * -> 28+32 = 60. 996 */ 997 if (has_second_ohare && 998 dev->vendor == PCI_VENDOR_ID_DEC && 999 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { 1000 dev->irq = irq_create_mapping(NULL, 60); 1001 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); 1002 } 1003 #endif /* CONFIG_PPC32 */ 1004 } 1005 1006 #ifdef CONFIG_PPC64 1007 static void __init pmac_fixup_phb_resources(void) 1008 { 1009 struct pci_controller *hose, *tmp; 1010 1011 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1012 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", 1013 hose->global_number, 1014 hose->io_resource.start, hose->io_resource.end); 1015 } 1016 } 1017 #endif 1018 1019 void __init pmac_pci_init(void) 1020 { 1021 struct device_node *np, *root; 1022 struct device_node *ht = NULL; 1023 1024 root = of_find_node_by_path("/"); 1025 if (root == NULL) { 1026 printk(KERN_CRIT "pmac_pci_init: can't find root " 1027 "of device tree\n"); 1028 return; 1029 } 1030 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 1031 if (np->name == NULL) 1032 continue; 1033 if (strcmp(np->name, "bandit") == 0 1034 || strcmp(np->name, "chaos") == 0 1035 || strcmp(np->name, "pci") == 0) { 1036 if (add_bridge(np) == 0) 1037 of_node_get(np); 1038 } 1039 if (strcmp(np->name, "ht") == 0) { 1040 of_node_get(np); 1041 ht = np; 1042 } 1043 } 1044 of_node_put(root); 1045 1046 #ifdef CONFIG_PPC64 1047 /* Probe HT last as it relies on the agp resources to be already 1048 * setup 1049 */ 1050 if (ht && add_bridge(ht) != 0) 1051 of_node_put(ht); 1052 1053 /* 1054 * We need to call pci_setup_phb_io for the HT bridge first 1055 * so it gets the I/O port numbers starting at 0, and we 1056 * need to call it for the AGP bridge after that so it gets 1057 * small positive I/O port numbers. 1058 */ 1059 if (u3_ht) 1060 pci_setup_phb_io(u3_ht, 1); 1061 if (u3_agp) 1062 pci_setup_phb_io(u3_agp, 0); 1063 if (u4_pcie) 1064 pci_setup_phb_io(u4_pcie, 0); 1065 1066 /* 1067 * On ppc64, fixup the IO resources on our host bridges as 1068 * the common code does it only for children of the host bridges 1069 */ 1070 pmac_fixup_phb_resources(); 1071 1072 /* Setup the linkage between OF nodes and PHBs */ 1073 pci_devs_phb_init(); 1074 1075 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 1076 * assume there is no P2P bridge on the AGP bus, which should be a 1077 * safe assumptions for now. We should do something better in the 1078 * future though 1079 */ 1080 if (u3_agp) { 1081 struct device_node *np = u3_agp->arch_data; 1082 PCI_DN(np)->busno = 0xf0; 1083 for (np = np->child; np; np = np->sibling) 1084 PCI_DN(np)->busno = 0xf0; 1085 } 1086 /* pmac_check_ht_link(); */ 1087 1088 /* Tell pci.c to not use the common resource allocation mechanism */ 1089 pci_probe_only = 1; 1090 1091 #else /* CONFIG_PPC64 */ 1092 init_p2pbridge(); 1093 init_second_ohare(); 1094 fixup_nec_usb2(); 1095 1096 /* We are still having some issues with the Xserve G4, enabling 1097 * some offset between bus number and domains for now when we 1098 * assign all busses should help for now 1099 */ 1100 if (pci_assign_all_buses) 1101 pcibios_assign_bus_offset = 0x10; 1102 #endif 1103 } 1104 1105 int 1106 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) 1107 { 1108 struct device_node* node; 1109 int updatecfg = 0; 1110 int uninorth_child; 1111 1112 node = pci_device_to_OF_node(dev); 1113 1114 /* We don't want to enable USB controllers absent from the OF tree 1115 * (iBook second controller) 1116 */ 1117 if (dev->vendor == PCI_VENDOR_ID_APPLE 1118 && dev->class == PCI_CLASS_SERIAL_USB_OHCI 1119 && !node) { 1120 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 1121 pci_name(dev)); 1122 return -EINVAL; 1123 } 1124 1125 if (!node) 1126 return 0; 1127 1128 uninorth_child = node->parent && 1129 device_is_compatible(node->parent, "uni-north"); 1130 1131 /* Firewire & GMAC were disabled after PCI probe, the driver is 1132 * claiming them, we must re-enable them now. 1133 */ 1134 if (uninorth_child && !strcmp(node->name, "firewire") && 1135 (device_is_compatible(node, "pci106b,18") || 1136 device_is_compatible(node, "pci106b,30") || 1137 device_is_compatible(node, "pci11c1,5811"))) { 1138 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 1139 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 1140 updatecfg = 1; 1141 } 1142 if (uninorth_child && !strcmp(node->name, "ethernet") && 1143 device_is_compatible(node, "gmac")) { 1144 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 1145 updatecfg = 1; 1146 } 1147 1148 if (updatecfg) { 1149 u16 cmd; 1150 1151 /* 1152 * Make sure PCI is correctly configured 1153 * 1154 * We use old pci_bios versions of the function since, by 1155 * default, gmac is not powered up, and so will be absent 1156 * from the kernel initial PCI lookup. 1157 * 1158 * Should be replaced by 2.4 new PCI mechanisms and really 1159 * register the device. 1160 */ 1161 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1162 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 1163 | PCI_COMMAND_INVALIDATE; 1164 pci_write_config_word(dev, PCI_COMMAND, cmd); 1165 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1166 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1167 L1_CACHE_BYTES >> 2); 1168 } 1169 1170 return 0; 1171 } 1172 1173 /* We power down some devices after they have been probed. They'll 1174 * be powered back on later on 1175 */ 1176 void __init pmac_pcibios_after_init(void) 1177 { 1178 struct device_node* nd; 1179 1180 #ifdef CONFIG_BLK_DEV_IDE 1181 struct pci_dev *dev = NULL; 1182 1183 /* OF fails to initialize IDE controllers on macs 1184 * (and maybe other machines) 1185 * 1186 * Ideally, this should be moved to the IDE layer, but we need 1187 * to check specifically with Andre Hedrick how to do it cleanly 1188 * since the common IDE code seem to care about the fact that the 1189 * BIOS may have disabled a controller. 1190 * 1191 * -- BenH 1192 */ 1193 for_each_pci_dev(dev) { 1194 if ((dev->class >> 16) != PCI_BASE_CLASS_STORAGE) 1195 continue; 1196 if (pci_enable_device(dev)) 1197 printk(KERN_WARNING 1198 "pci: Failed to enable %s\n", pci_name(dev)); 1199 } 1200 #endif /* CONFIG_BLK_DEV_IDE */ 1201 1202 nd = find_devices("firewire"); 1203 while (nd) { 1204 if (nd->parent && (device_is_compatible(nd, "pci106b,18") || 1205 device_is_compatible(nd, "pci106b,30") || 1206 device_is_compatible(nd, "pci11c1,5811")) 1207 && device_is_compatible(nd->parent, "uni-north")) { 1208 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1209 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1210 } 1211 nd = nd->next; 1212 } 1213 nd = find_devices("ethernet"); 1214 while (nd) { 1215 if (nd->parent && device_is_compatible(nd, "gmac") 1216 && device_is_compatible(nd->parent, "uni-north")) 1217 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1218 nd = nd->next; 1219 } 1220 } 1221 1222 #ifdef CONFIG_PPC32 1223 void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1224 { 1225 if (!machine_is(powermac)) 1226 return; 1227 /* 1228 * Fix the interrupt routing on the various cardbus bridges 1229 * used on powerbooks 1230 */ 1231 if (dev->vendor != PCI_VENDOR_ID_TI) 1232 return; 1233 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1234 dev->device == PCI_DEVICE_ID_TI_1131) { 1235 u8 val; 1236 /* Enable PCI interrupt */ 1237 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1238 pci_write_config_byte(dev, 0x91, val | 0x30); 1239 /* Disable ISA interrupt mode */ 1240 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1241 pci_write_config_byte(dev, 0x92, val & ~0x06); 1242 } 1243 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1244 dev->device == PCI_DEVICE_ID_TI_1211 || 1245 dev->device == PCI_DEVICE_ID_TI_1410 || 1246 dev->device == PCI_DEVICE_ID_TI_1510) { 1247 u8 val; 1248 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1249 signal out the MFUNC0 pin */ 1250 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1251 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1252 /* Disable ISA interrupt mode */ 1253 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1254 pci_write_config_byte(dev, 0x92, val & ~0x06); 1255 } 1256 } 1257 1258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1259 1260 void pmac_pci_fixup_pciata(struct pci_dev* dev) 1261 { 1262 u8 progif = 0; 1263 1264 /* 1265 * On PowerMacs, we try to switch any PCI ATA controller to 1266 * fully native mode 1267 */ 1268 if (!machine_is(powermac)) 1269 return; 1270 1271 /* Some controllers don't have the class IDE */ 1272 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1273 switch(dev->device) { 1274 case PCI_DEVICE_ID_PROMISE_20246: 1275 case PCI_DEVICE_ID_PROMISE_20262: 1276 case PCI_DEVICE_ID_PROMISE_20263: 1277 case PCI_DEVICE_ID_PROMISE_20265: 1278 case PCI_DEVICE_ID_PROMISE_20267: 1279 case PCI_DEVICE_ID_PROMISE_20268: 1280 case PCI_DEVICE_ID_PROMISE_20269: 1281 case PCI_DEVICE_ID_PROMISE_20270: 1282 case PCI_DEVICE_ID_PROMISE_20271: 1283 case PCI_DEVICE_ID_PROMISE_20275: 1284 case PCI_DEVICE_ID_PROMISE_20276: 1285 case PCI_DEVICE_ID_PROMISE_20277: 1286 goto good; 1287 } 1288 /* Others, check PCI class */ 1289 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1290 return; 1291 good: 1292 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1293 if ((progif & 5) != 5) { 1294 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", 1295 pci_name(dev)); 1296 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1297 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1298 (progif & 5) != 5) 1299 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1300 } 1301 } 1302 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1303 #endif 1304 1305 /* 1306 * Disable second function on K2-SATA, it's broken 1307 * and disable IO BARs on first one 1308 */ 1309 static void fixup_k2_sata(struct pci_dev* dev) 1310 { 1311 int i; 1312 u16 cmd; 1313 1314 if (PCI_FUNC(dev->devfn) > 0) { 1315 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1316 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1317 pci_write_config_word(dev, PCI_COMMAND, cmd); 1318 for (i = 0; i < 6; i++) { 1319 dev->resource[i].start = dev->resource[i].end = 0; 1320 dev->resource[i].flags = 0; 1321 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1322 0); 1323 } 1324 } else { 1325 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1326 cmd &= ~PCI_COMMAND_IO; 1327 pci_write_config_word(dev, PCI_COMMAND, cmd); 1328 for (i = 0; i < 5; i++) { 1329 dev->resource[i].start = dev->resource[i].end = 0; 1330 dev->resource[i].flags = 0; 1331 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1332 0); 1333 } 1334 } 1335 } 1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1337 1338