1 /* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/bootmem.h> 19 20 #include <asm/sections.h> 21 #include <asm/io.h> 22 #include <asm/prom.h> 23 #include <asm/pci-bridge.h> 24 #include <asm/machdep.h> 25 #include <asm/pmac_feature.h> 26 #include <asm/grackle.h> 27 #ifdef CONFIG_PPC64 28 #include <asm/iommu.h> 29 #include <asm/ppc-pci.h> 30 #endif 31 32 #undef DEBUG 33 34 #ifdef DEBUG 35 #define DBG(x...) printk(x) 36 #else 37 #define DBG(x...) 38 #endif 39 40 static int add_bridge(struct device_node *dev); 41 42 /* XXX Could be per-controller, but I don't think we risk anything by 43 * assuming we won't have both UniNorth and Bandit */ 44 static int has_uninorth; 45 #ifdef CONFIG_PPC64 46 static struct pci_controller *u3_agp; 47 static struct pci_controller *u3_ht; 48 #endif /* CONFIG_PPC64 */ 49 50 extern u8 pci_cache_line_size; 51 extern int pcibios_assign_bus_offset; 52 53 struct device_node *k2_skiplist[2]; 54 55 /* 56 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 57 */ 58 #define BANDIT_DEVID_2 8 59 #define BANDIT_REVID 3 60 61 #define BANDIT_DEVNUM 11 62 #define BANDIT_MAGIC 0x50 63 #define BANDIT_COHERENT 0x40 64 65 static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 66 { 67 for (; node != 0;node = node->sibling) { 68 int * bus_range; 69 unsigned int *class_code; 70 int len; 71 72 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 73 class_code = (unsigned int *) get_property(node, "class-code", NULL); 74 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 75 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 76 continue; 77 bus_range = (int *) get_property(node, "bus-range", &len); 78 if (bus_range != NULL && len > 2 * sizeof(int)) { 79 if (bus_range[1] > higher) 80 higher = bus_range[1]; 81 } 82 higher = fixup_one_level_bus_range(node->child, higher); 83 } 84 return higher; 85 } 86 87 /* This routine fixes the "bus-range" property of all bridges in the 88 * system since they tend to have their "last" member wrong on macs 89 * 90 * Note that the bus numbers manipulated here are OF bus numbers, they 91 * are not Linux bus numbers. 92 */ 93 static void __init fixup_bus_range(struct device_node *bridge) 94 { 95 int * bus_range; 96 int len; 97 98 /* Lookup the "bus-range" property for the hose */ 99 bus_range = (int *) get_property(bridge, "bus-range", &len); 100 if (bus_range == NULL || len < 2 * sizeof(int)) { 101 printk(KERN_WARNING "Can't get bus-range for %s\n", 102 bridge->full_name); 103 return; 104 } 105 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 106 } 107 108 /* 109 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 110 * 111 * The "Bandit" version is present in all early PCI PowerMacs, 112 * and up to the first ones using Grackle. Some machines may 113 * have 2 bandit controllers (2 PCI busses). 114 * 115 * "Chaos" is used in some "Bandit"-type machines as a bridge 116 * for the separate display bus. It is accessed the same 117 * way as bandit, but cannot be probed for devices. It therefore 118 * has its own config access functions. 119 * 120 * The "UniNorth" version is present in all Core99 machines 121 * (iBook, G4, new IMacs, and all the recent Apple machines). 122 * It contains 3 controllers in one ASIC. 123 * 124 * The U3 is the bridge used on G5 machines. It contains an 125 * AGP bus which is dealt with the old UniNorth access routines 126 * and a HyperTransport bus which uses its own set of access 127 * functions. 128 */ 129 130 #define MACRISC_CFA0(devfn, off) \ 131 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \ 132 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \ 133 | (((unsigned long)(off)) & 0xFCUL)) 134 135 #define MACRISC_CFA1(bus, devfn, off) \ 136 ((((unsigned long)(bus)) << 16) \ 137 |(((unsigned long)(devfn)) << 8) \ 138 |(((unsigned long)(off)) & 0xFCUL) \ 139 |1UL) 140 141 static unsigned long macrisc_cfg_access(struct pci_controller* hose, 142 u8 bus, u8 dev_fn, u8 offset) 143 { 144 unsigned int caddr; 145 146 if (bus == hose->first_busno) { 147 if (dev_fn < (11 << 3)) 148 return 0; 149 caddr = MACRISC_CFA0(dev_fn, offset); 150 } else 151 caddr = MACRISC_CFA1(bus, dev_fn, offset); 152 153 /* Uninorth will return garbage if we don't read back the value ! */ 154 do { 155 out_le32(hose->cfg_addr, caddr); 156 } while (in_le32(hose->cfg_addr) != caddr); 157 158 offset &= has_uninorth ? 0x07 : 0x03; 159 return ((unsigned long)hose->cfg_data) + offset; 160 } 161 162 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, 163 int offset, int len, u32 *val) 164 { 165 struct pci_controller *hose; 166 unsigned long addr; 167 168 hose = pci_bus_to_host(bus); 169 if (hose == NULL) 170 return PCIBIOS_DEVICE_NOT_FOUND; 171 172 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 173 if (!addr) 174 return PCIBIOS_DEVICE_NOT_FOUND; 175 /* 176 * Note: the caller has already checked that offset is 177 * suitably aligned and that len is 1, 2 or 4. 178 */ 179 switch (len) { 180 case 1: 181 *val = in_8((u8 *)addr); 182 break; 183 case 2: 184 *val = in_le16((u16 *)addr); 185 break; 186 default: 187 *val = in_le32((u32 *)addr); 188 break; 189 } 190 return PCIBIOS_SUCCESSFUL; 191 } 192 193 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, 194 int offset, int len, u32 val) 195 { 196 struct pci_controller *hose; 197 unsigned long addr; 198 199 hose = pci_bus_to_host(bus); 200 if (hose == NULL) 201 return PCIBIOS_DEVICE_NOT_FOUND; 202 203 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 204 if (!addr) 205 return PCIBIOS_DEVICE_NOT_FOUND; 206 /* 207 * Note: the caller has already checked that offset is 208 * suitably aligned and that len is 1, 2 or 4. 209 */ 210 switch (len) { 211 case 1: 212 out_8((u8 *)addr, val); 213 (void) in_8((u8 *)addr); 214 break; 215 case 2: 216 out_le16((u16 *)addr, val); 217 (void) in_le16((u16 *)addr); 218 break; 219 default: 220 out_le32((u32 *)addr, val); 221 (void) in_le32((u32 *)addr); 222 break; 223 } 224 return PCIBIOS_SUCCESSFUL; 225 } 226 227 static struct pci_ops macrisc_pci_ops = 228 { 229 macrisc_read_config, 230 macrisc_write_config 231 }; 232 233 #ifdef CONFIG_PPC32 234 /* 235 * Verify that a specific (bus, dev_fn) exists on chaos 236 */ 237 static int 238 chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 239 { 240 struct device_node *np; 241 u32 *vendor, *device; 242 243 np = pci_busdev_to_OF_node(bus, devfn); 244 if (np == NULL) 245 return PCIBIOS_DEVICE_NOT_FOUND; 246 247 vendor = (u32 *)get_property(np, "vendor-id", NULL); 248 device = (u32 *)get_property(np, "device-id", NULL); 249 if (vendor == NULL || device == NULL) 250 return PCIBIOS_DEVICE_NOT_FOUND; 251 252 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 253 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 254 return PCIBIOS_BAD_REGISTER_NUMBER; 255 256 return PCIBIOS_SUCCESSFUL; 257 } 258 259 static int 260 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 261 int len, u32 *val) 262 { 263 int result = chaos_validate_dev(bus, devfn, offset); 264 if (result == PCIBIOS_BAD_REGISTER_NUMBER) 265 *val = ~0U; 266 if (result != PCIBIOS_SUCCESSFUL) 267 return result; 268 return macrisc_read_config(bus, devfn, offset, len, val); 269 } 270 271 static int 272 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 273 int len, u32 val) 274 { 275 int result = chaos_validate_dev(bus, devfn, offset); 276 if (result != PCIBIOS_SUCCESSFUL) 277 return result; 278 return macrisc_write_config(bus, devfn, offset, len, val); 279 } 280 281 static struct pci_ops chaos_pci_ops = 282 { 283 chaos_read_config, 284 chaos_write_config 285 }; 286 287 static void __init setup_chaos(struct pci_controller *hose, 288 struct reg_property *addr) 289 { 290 /* assume a `chaos' bridge */ 291 hose->ops = &chaos_pci_ops; 292 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); 293 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); 294 } 295 #else 296 #define setup_chaos(hose, addr) 297 #endif /* CONFIG_PPC32 */ 298 299 #ifdef CONFIG_PPC64 300 /* 301 * These versions of U3 HyperTransport config space access ops do not 302 * implement self-view of the HT host yet 303 */ 304 305 /* 306 * This function deals with some "special cases" devices. 307 * 308 * 0 -> No special case 309 * 1 -> Skip the device but act as if the access was successfull 310 * (return 0xff's on reads, eventually, cache config space 311 * accesses in a later version) 312 * -1 -> Hide the device (unsuccessful acess) 313 */ 314 static int u3_ht_skip_device(struct pci_controller *hose, 315 struct pci_bus *bus, unsigned int devfn) 316 { 317 struct device_node *busdn, *dn; 318 int i; 319 320 /* We only allow config cycles to devices that are in OF device-tree 321 * as we are apparently having some weird things going on with some 322 * revs of K2 on recent G5s 323 */ 324 if (bus->self) 325 busdn = pci_device_to_OF_node(bus->self); 326 else 327 busdn = hose->arch_data; 328 for (dn = busdn->child; dn; dn = dn->sibling) 329 if (dn->data && PCI_DN(dn)->devfn == devfn) 330 break; 331 if (dn == NULL) 332 return -1; 333 334 /* 335 * When a device in K2 is powered down, we die on config 336 * cycle accesses. Fix that here. 337 */ 338 for (i=0; i<2; i++) 339 if (k2_skiplist[i] == dn) 340 return 1; 341 342 return 0; 343 } 344 345 #define U3_HT_CFA0(devfn, off) \ 346 ((((unsigned long)devfn) << 8) | offset) 347 #define U3_HT_CFA1(bus, devfn, off) \ 348 (U3_HT_CFA0(devfn, off) \ 349 + (((unsigned long)bus) << 16) \ 350 + 0x01000000UL) 351 352 static unsigned long u3_ht_cfg_access(struct pci_controller* hose, 353 u8 bus, u8 devfn, u8 offset) 354 { 355 if (bus == hose->first_busno) { 356 /* For now, we don't self probe U3 HT bridge */ 357 if (PCI_SLOT(devfn) == 0) 358 return 0; 359 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset); 360 } else 361 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); 362 } 363 364 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 365 int offset, int len, u32 *val) 366 { 367 struct pci_controller *hose; 368 unsigned long addr; 369 370 hose = pci_bus_to_host(bus); 371 if (hose == NULL) 372 return PCIBIOS_DEVICE_NOT_FOUND; 373 374 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 375 if (!addr) 376 return PCIBIOS_DEVICE_NOT_FOUND; 377 378 switch (u3_ht_skip_device(hose, bus, devfn)) { 379 case 0: 380 break; 381 case 1: 382 switch (len) { 383 case 1: 384 *val = 0xff; break; 385 case 2: 386 *val = 0xffff; break; 387 default: 388 *val = 0xfffffffful; break; 389 } 390 return PCIBIOS_SUCCESSFUL; 391 default: 392 return PCIBIOS_DEVICE_NOT_FOUND; 393 } 394 395 /* 396 * Note: the caller has already checked that offset is 397 * suitably aligned and that len is 1, 2 or 4. 398 */ 399 switch (len) { 400 case 1: 401 *val = in_8((u8 *)addr); 402 break; 403 case 2: 404 *val = in_le16((u16 *)addr); 405 break; 406 default: 407 *val = in_le32((u32 *)addr); 408 break; 409 } 410 return PCIBIOS_SUCCESSFUL; 411 } 412 413 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 414 int offset, int len, u32 val) 415 { 416 struct pci_controller *hose; 417 unsigned long addr; 418 419 hose = pci_bus_to_host(bus); 420 if (hose == NULL) 421 return PCIBIOS_DEVICE_NOT_FOUND; 422 423 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 424 if (!addr) 425 return PCIBIOS_DEVICE_NOT_FOUND; 426 427 switch (u3_ht_skip_device(hose, bus, devfn)) { 428 case 0: 429 break; 430 case 1: 431 return PCIBIOS_SUCCESSFUL; 432 default: 433 return PCIBIOS_DEVICE_NOT_FOUND; 434 } 435 436 /* 437 * Note: the caller has already checked that offset is 438 * suitably aligned and that len is 1, 2 or 4. 439 */ 440 switch (len) { 441 case 1: 442 out_8((u8 *)addr, val); 443 (void) in_8((u8 *)addr); 444 break; 445 case 2: 446 out_le16((u16 *)addr, val); 447 (void) in_le16((u16 *)addr); 448 break; 449 default: 450 out_le32((u32 *)addr, val); 451 (void) in_le32((u32 *)addr); 452 break; 453 } 454 return PCIBIOS_SUCCESSFUL; 455 } 456 457 static struct pci_ops u3_ht_pci_ops = 458 { 459 u3_ht_read_config, 460 u3_ht_write_config 461 }; 462 #endif /* CONFIG_PPC64 */ 463 464 #ifdef CONFIG_PPC32 465 /* 466 * For a bandit bridge, turn on cache coherency if necessary. 467 * N.B. we could clean this up using the hose ops directly. 468 */ 469 static void __init init_bandit(struct pci_controller *bp) 470 { 471 unsigned int vendev, magic; 472 int rev; 473 474 /* read the word at offset 0 in config space for device 11 */ 475 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 476 udelay(2); 477 vendev = in_le32(bp->cfg_data); 478 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 479 PCI_VENDOR_ID_APPLE) { 480 /* read the revision id */ 481 out_le32(bp->cfg_addr, 482 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 483 udelay(2); 484 rev = in_8(bp->cfg_data); 485 if (rev != BANDIT_REVID) 486 printk(KERN_WARNING 487 "Unknown revision %d for bandit\n", rev); 488 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 489 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 490 return; 491 } 492 493 /* read the word at offset 0x50 */ 494 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 495 udelay(2); 496 magic = in_le32(bp->cfg_data); 497 if ((magic & BANDIT_COHERENT) != 0) 498 return; 499 magic |= BANDIT_COHERENT; 500 udelay(2); 501 out_le32(bp->cfg_data, magic); 502 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 503 } 504 505 /* 506 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 507 */ 508 static void __init init_p2pbridge(void) 509 { 510 struct device_node *p2pbridge; 511 struct pci_controller* hose; 512 u8 bus, devfn; 513 u16 val; 514 515 /* XXX it would be better here to identify the specific 516 PCI-PCI bridge chip we have. */ 517 if ((p2pbridge = find_devices("pci-bridge")) == 0 518 || p2pbridge->parent == NULL 519 || strcmp(p2pbridge->parent->name, "pci") != 0) 520 return; 521 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 522 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 523 return; 524 } 525 /* Warning: At this point, we have not yet renumbered all busses. 526 * So we must use OF walking to find out hose 527 */ 528 hose = pci_find_hose_for_OF_device(p2pbridge); 529 if (!hose) { 530 DBG("Can't find hose for PCI<->PCI bridge\n"); 531 return; 532 } 533 if (early_read_config_word(hose, bus, devfn, 534 PCI_BRIDGE_CONTROL, &val) < 0) { 535 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n"); 536 return; 537 } 538 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 539 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 540 } 541 542 /* 543 * Some Apple desktop machines have a NEC PD720100A USB2 controller 544 * on the motherboard. Open Firmware, on these, will disable the 545 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 546 * code re-enables it ;) 547 */ 548 static void __init fixup_nec_usb2(void) 549 { 550 struct device_node *nec; 551 552 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { 553 struct pci_controller *hose; 554 u32 data, *prop; 555 u8 bus, devfn; 556 557 prop = (u32 *)get_property(nec, "vendor-id", NULL); 558 if (prop == NULL) 559 continue; 560 if (0x1033 != *prop) 561 continue; 562 prop = (u32 *)get_property(nec, "device-id", NULL); 563 if (prop == NULL) 564 continue; 565 if (0x0035 != *prop) 566 continue; 567 prop = (u32 *)get_property(nec, "reg", NULL); 568 if (prop == NULL) 569 continue; 570 devfn = (prop[0] >> 8) & 0xff; 571 bus = (prop[0] >> 16) & 0xff; 572 if (PCI_FUNC(devfn) != 0) 573 continue; 574 hose = pci_find_hose_for_OF_device(nec); 575 if (!hose) 576 continue; 577 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 578 if (data & 1UL) { 579 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n"); 580 data &= ~1UL; 581 early_write_config_dword(hose, bus, devfn, 0xe4, data); 582 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE, 583 nec->intrs[0].line); 584 } 585 } 586 } 587 588 static void __init setup_bandit(struct pci_controller *hose, 589 struct reg_property *addr) 590 { 591 hose->ops = ¯isc_pci_ops; 592 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); 593 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); 594 init_bandit(hose); 595 } 596 597 static int __init setup_uninorth(struct pci_controller *hose, 598 struct reg_property *addr) 599 { 600 pci_assign_all_buses = 1; 601 has_uninorth = 1; 602 hose->ops = ¯isc_pci_ops; 603 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); 604 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); 605 /* We "know" that the bridge at f2000000 has the PCI slots. */ 606 return addr->address == 0xf2000000; 607 } 608 #endif 609 610 #ifdef CONFIG_PPC64 611 static void __init setup_u3_agp(struct pci_controller* hose) 612 { 613 /* On G5, we move AGP up to high bus number so we don't need 614 * to reassign bus numbers for HT. If we ever have P2P bridges 615 * on AGP, we'll have to move pci_assign_all_busses to the 616 * pci_controller structure so we enable it for AGP and not for 617 * HT childs. 618 * We hard code the address because of the different size of 619 * the reg address cell, we shall fix that by killing struct 620 * reg_property and using some accessor functions instead 621 */ 622 hose->first_busno = 0xf0; 623 hose->last_busno = 0xff; 624 has_uninorth = 1; 625 hose->ops = ¯isc_pci_ops; 626 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 627 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 628 629 u3_agp = hose; 630 } 631 632 static void __init setup_u3_ht(struct pci_controller* hose) 633 { 634 struct device_node *np = (struct device_node *)hose->arch_data; 635 int i, cur; 636 637 hose->ops = &u3_ht_pci_ops; 638 639 /* We hard code the address because of the different size of 640 * the reg address cell, we shall fix that by killing struct 641 * reg_property and using some accessor functions instead 642 */ 643 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); 644 645 /* 646 * /ht node doesn't expose a "ranges" property, so we "remove" regions that 647 * have been allocated to AGP. So far, this version of the code doesn't assign 648 * any of the 0xfxxxxxxx "fine" memory regions to /ht. 649 * We need to fix that sooner or later by either parsing all child "ranges" 650 * properties or figuring out the U3 address space decoding logic and 651 * then read its configuration register (if any). 652 */ 653 hose->io_base_phys = 0xf4000000; 654 hose->pci_io_size = 0x00400000; 655 hose->io_resource.name = np->full_name; 656 hose->io_resource.start = 0; 657 hose->io_resource.end = 0x003fffff; 658 hose->io_resource.flags = IORESOURCE_IO; 659 hose->pci_mem_offset = 0; 660 hose->first_busno = 0; 661 hose->last_busno = 0xef; 662 hose->mem_resources[0].name = np->full_name; 663 hose->mem_resources[0].start = 0x80000000; 664 hose->mem_resources[0].end = 0xefffffff; 665 hose->mem_resources[0].flags = IORESOURCE_MEM; 666 667 u3_ht = hose; 668 669 if (u3_agp == NULL) { 670 DBG("U3 has no AGP, using full resource range\n"); 671 return; 672 } 673 674 /* We "remove" the AGP resources from the resources allocated to HT, that 675 * is we create "holes". However, that code does assumptions that so far 676 * happen to be true (cross fingers...), typically that resources in the 677 * AGP node are properly ordered 678 */ 679 cur = 0; 680 for (i=0; i<3; i++) { 681 struct resource *res = &u3_agp->mem_resources[i]; 682 if (res->flags != IORESOURCE_MEM) 683 continue; 684 /* We don't care about "fine" resources */ 685 if (res->start >= 0xf0000000) 686 continue; 687 /* Check if it's just a matter of "shrinking" us in one direction */ 688 if (hose->mem_resources[cur].start == res->start) { 689 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", 690 cur, hose->mem_resources[cur].start, res->end + 1); 691 hose->mem_resources[cur].start = res->end + 1; 692 continue; 693 } 694 if (hose->mem_resources[cur].end == res->end) { 695 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", 696 cur, hose->mem_resources[cur].end, res->start - 1); 697 hose->mem_resources[cur].end = res->start - 1; 698 continue; 699 } 700 /* No, it's not the case, we need a hole */ 701 if (cur == 2) { 702 /* not enough resources for a hole, we drop part of the range */ 703 printk(KERN_WARNING "Running out of resources for /ht host !\n"); 704 hose->mem_resources[cur].end = res->start - 1; 705 continue; 706 } 707 cur++; 708 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", 709 cur-1, res->start - 1, cur, res->end + 1); 710 hose->mem_resources[cur].name = np->full_name; 711 hose->mem_resources[cur].flags = IORESOURCE_MEM; 712 hose->mem_resources[cur].start = res->end + 1; 713 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; 714 hose->mem_resources[cur-1].end = res->start - 1; 715 } 716 } 717 718 /* XXX this needs to be converged between ppc32 and ppc64... */ 719 static struct pci_controller * __init pcibios_alloc_controller(void) 720 { 721 struct pci_controller *hose; 722 723 hose = alloc_bootmem(sizeof(struct pci_controller)); 724 if (hose) 725 pci_setup_pci_controller(hose); 726 return hose; 727 } 728 #endif 729 730 /* 731 * We assume that if we have a G3 powermac, we have one bridge called 732 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 733 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 734 */ 735 static int __init add_bridge(struct device_node *dev) 736 { 737 int len; 738 struct pci_controller *hose; 739 #ifdef CONFIG_PPC32 740 struct reg_property *addr; 741 #endif 742 char *disp_name; 743 int *bus_range; 744 int primary = 1; 745 746 DBG("Adding PCI host bridge %s\n", dev->full_name); 747 748 #ifdef CONFIG_PPC32 749 /* XXX fix this */ 750 addr = (struct reg_property *) get_property(dev, "reg", &len); 751 if (addr == NULL || len < sizeof(*addr)) { 752 printk(KERN_WARNING "Can't use %s: no address\n", 753 dev->full_name); 754 return -ENODEV; 755 } 756 #endif 757 bus_range = (int *) get_property(dev, "bus-range", &len); 758 if (bus_range == NULL || len < 2 * sizeof(int)) { 759 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n", 760 dev->full_name); 761 } 762 763 hose = pcibios_alloc_controller(); 764 if (!hose) 765 return -ENOMEM; 766 hose->arch_data = dev; 767 hose->first_busno = bus_range ? bus_range[0] : 0; 768 hose->last_busno = bus_range ? bus_range[1] : 0xff; 769 770 disp_name = NULL; 771 #ifdef CONFIG_POWER4 772 if (device_is_compatible(dev, "u3-agp")) { 773 setup_u3_agp(hose); 774 disp_name = "U3-AGP"; 775 primary = 0; 776 } else if (device_is_compatible(dev, "u3-ht")) { 777 setup_u3_ht(hose); 778 disp_name = "U3-HT"; 779 primary = 1; 780 } 781 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n", 782 disp_name, hose->first_busno, hose->last_busno); 783 #else 784 if (device_is_compatible(dev, "uni-north")) { 785 primary = setup_uninorth(hose, addr); 786 disp_name = "UniNorth"; 787 } else if (strcmp(dev->name, "pci") == 0) { 788 /* XXX assume this is a mpc106 (grackle) */ 789 setup_grackle(hose); 790 disp_name = "Grackle (MPC106)"; 791 } else if (strcmp(dev->name, "bandit") == 0) { 792 setup_bandit(hose, addr); 793 disp_name = "Bandit"; 794 } else if (strcmp(dev->name, "chaos") == 0) { 795 setup_chaos(hose, addr); 796 disp_name = "Chaos"; 797 primary = 0; 798 } 799 printk(KERN_INFO "Found %s PCI host bridge at 0x%08lx. Firmware bus number: %d->%d\n", 800 disp_name, addr->address, hose->first_busno, hose->last_busno); 801 #endif 802 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 803 hose, hose->cfg_addr, hose->cfg_data); 804 805 /* Interpret the "ranges" property */ 806 /* This also maps the I/O region and sets isa_io/mem_base */ 807 pci_process_bridge_OF_ranges(hose, dev, primary); 808 809 /* Fixup "bus-range" OF property */ 810 fixup_bus_range(dev); 811 812 return 0; 813 } 814 815 static void __init 816 pcibios_fixup_OF_interrupts(void) 817 { 818 struct pci_dev* dev = NULL; 819 820 /* 821 * Open Firmware often doesn't initialize the 822 * PCI_INTERRUPT_LINE config register properly, so we 823 * should find the device node and apply the interrupt 824 * obtained from the OF device-tree 825 */ 826 for_each_pci_dev(dev) { 827 struct device_node *node; 828 node = pci_device_to_OF_node(dev); 829 /* this is the node, see if it has interrupts */ 830 if (node && node->n_intrs > 0) 831 dev->irq = node->intrs[0].line; 832 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 833 } 834 } 835 836 void __init 837 pmac_pcibios_fixup(void) 838 { 839 /* Fixup interrupts according to OF tree */ 840 pcibios_fixup_OF_interrupts(); 841 } 842 843 #ifdef CONFIG_PPC64 844 static void __init pmac_fixup_phb_resources(void) 845 { 846 struct pci_controller *hose, *tmp; 847 848 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 849 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", 850 hose->global_number, 851 hose->io_resource.start, hose->io_resource.end); 852 } 853 } 854 #endif 855 856 void __init pmac_pci_init(void) 857 { 858 struct device_node *np, *root; 859 struct device_node *ht = NULL; 860 861 root = of_find_node_by_path("/"); 862 if (root == NULL) { 863 printk(KERN_CRIT "pmac_pci_init: can't find root " 864 "of device tree\n"); 865 return; 866 } 867 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 868 if (np->name == NULL) 869 continue; 870 if (strcmp(np->name, "bandit") == 0 871 || strcmp(np->name, "chaos") == 0 872 || strcmp(np->name, "pci") == 0) { 873 if (add_bridge(np) == 0) 874 of_node_get(np); 875 } 876 if (strcmp(np->name, "ht") == 0) { 877 of_node_get(np); 878 ht = np; 879 } 880 } 881 of_node_put(root); 882 883 #ifdef CONFIG_PPC64 884 /* Probe HT last as it relies on the agp resources to be already 885 * setup 886 */ 887 if (ht && add_bridge(ht) != 0) 888 of_node_put(ht); 889 890 /* 891 * We need to call pci_setup_phb_io for the HT bridge first 892 * so it gets the I/O port numbers starting at 0, and we 893 * need to call it for the AGP bridge after that so it gets 894 * small positive I/O port numbers. 895 */ 896 if (u3_ht) 897 pci_setup_phb_io(u3_ht, 1); 898 if (u3_agp) 899 pci_setup_phb_io(u3_agp, 0); 900 901 /* 902 * On ppc64, fixup the IO resources on our host bridges as 903 * the common code does it only for children of the host bridges 904 */ 905 pmac_fixup_phb_resources(); 906 907 /* Setup the linkage between OF nodes and PHBs */ 908 pci_devs_phb_init(); 909 910 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 911 * assume there is no P2P bridge on the AGP bus, which should be a 912 * safe assumptions hopefully. 913 */ 914 if (u3_agp) { 915 struct device_node *np = u3_agp->arch_data; 916 PCI_DN(np)->busno = 0xf0; 917 for (np = np->child; np; np = np->sibling) 918 PCI_DN(np)->busno = 0xf0; 919 } 920 921 /* map in PCI I/O space */ 922 phbs_remap_io(); 923 924 /* pmac_check_ht_link(); */ 925 926 /* Tell pci.c to not use the common resource allocation mechanism */ 927 pci_probe_only = 1; 928 929 /* Allow all IO */ 930 io_page_mask = -1; 931 932 #else /* CONFIG_PPC64 */ 933 init_p2pbridge(); 934 fixup_nec_usb2(); 935 936 /* We are still having some issues with the Xserve G4, enabling 937 * some offset between bus number and domains for now when we 938 * assign all busses should help for now 939 */ 940 if (pci_assign_all_buses) 941 pcibios_assign_bus_offset = 0x10; 942 #endif 943 } 944 945 int 946 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) 947 { 948 struct device_node* node; 949 int updatecfg = 0; 950 int uninorth_child; 951 952 node = pci_device_to_OF_node(dev); 953 954 /* We don't want to enable USB controllers absent from the OF tree 955 * (iBook second controller) 956 */ 957 if (dev->vendor == PCI_VENDOR_ID_APPLE 958 && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) 959 && !node) { 960 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 961 pci_name(dev)); 962 return -EINVAL; 963 } 964 965 if (!node) 966 return 0; 967 968 uninorth_child = node->parent && 969 device_is_compatible(node->parent, "uni-north"); 970 971 /* Firewire & GMAC were disabled after PCI probe, the driver is 972 * claiming them, we must re-enable them now. 973 */ 974 if (uninorth_child && !strcmp(node->name, "firewire") && 975 (device_is_compatible(node, "pci106b,18") || 976 device_is_compatible(node, "pci106b,30") || 977 device_is_compatible(node, "pci11c1,5811"))) { 978 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 979 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 980 updatecfg = 1; 981 } 982 if (uninorth_child && !strcmp(node->name, "ethernet") && 983 device_is_compatible(node, "gmac")) { 984 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 985 updatecfg = 1; 986 } 987 988 if (updatecfg) { 989 u16 cmd; 990 991 /* 992 * Make sure PCI is correctly configured 993 * 994 * We use old pci_bios versions of the function since, by 995 * default, gmac is not powered up, and so will be absent 996 * from the kernel initial PCI lookup. 997 * 998 * Should be replaced by 2.4 new PCI mechanisms and really 999 * register the device. 1000 */ 1001 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1002 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 1003 | PCI_COMMAND_INVALIDATE; 1004 pci_write_config_word(dev, PCI_COMMAND, cmd); 1005 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1006 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1007 L1_CACHE_BYTES >> 2); 1008 } 1009 1010 return 0; 1011 } 1012 1013 /* We power down some devices after they have been probed. They'll 1014 * be powered back on later on 1015 */ 1016 void __init pmac_pcibios_after_init(void) 1017 { 1018 struct device_node* nd; 1019 1020 #ifdef CONFIG_BLK_DEV_IDE 1021 struct pci_dev *dev = NULL; 1022 1023 /* OF fails to initialize IDE controllers on macs 1024 * (and maybe other machines) 1025 * 1026 * Ideally, this should be moved to the IDE layer, but we need 1027 * to check specifically with Andre Hedrick how to do it cleanly 1028 * since the common IDE code seem to care about the fact that the 1029 * BIOS may have disabled a controller. 1030 * 1031 * -- BenH 1032 */ 1033 for_each_pci_dev(dev) { 1034 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) 1035 pci_enable_device(dev); 1036 } 1037 #endif /* CONFIG_BLK_DEV_IDE */ 1038 1039 nd = find_devices("firewire"); 1040 while (nd) { 1041 if (nd->parent && (device_is_compatible(nd, "pci106b,18") || 1042 device_is_compatible(nd, "pci106b,30") || 1043 device_is_compatible(nd, "pci11c1,5811")) 1044 && device_is_compatible(nd->parent, "uni-north")) { 1045 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1046 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1047 } 1048 nd = nd->next; 1049 } 1050 nd = find_devices("ethernet"); 1051 while (nd) { 1052 if (nd->parent && device_is_compatible(nd, "gmac") 1053 && device_is_compatible(nd->parent, "uni-north")) 1054 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1055 nd = nd->next; 1056 } 1057 } 1058 1059 #ifdef CONFIG_PPC32 1060 void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1061 { 1062 if (_machine != _MACH_Pmac) 1063 return; 1064 /* 1065 * Fix the interrupt routing on the various cardbus bridges 1066 * used on powerbooks 1067 */ 1068 if (dev->vendor != PCI_VENDOR_ID_TI) 1069 return; 1070 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1071 dev->device == PCI_DEVICE_ID_TI_1131) { 1072 u8 val; 1073 /* Enable PCI interrupt */ 1074 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1075 pci_write_config_byte(dev, 0x91, val | 0x30); 1076 /* Disable ISA interrupt mode */ 1077 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1078 pci_write_config_byte(dev, 0x92, val & ~0x06); 1079 } 1080 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1081 dev->device == PCI_DEVICE_ID_TI_1211 || 1082 dev->device == PCI_DEVICE_ID_TI_1410 || 1083 dev->device == PCI_DEVICE_ID_TI_1510) { 1084 u8 val; 1085 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1086 signal out the MFUNC0 pin */ 1087 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1088 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1089 /* Disable ISA interrupt mode */ 1090 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1091 pci_write_config_byte(dev, 0x92, val & ~0x06); 1092 } 1093 } 1094 1095 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1096 1097 void pmac_pci_fixup_pciata(struct pci_dev* dev) 1098 { 1099 u8 progif = 0; 1100 1101 /* 1102 * On PowerMacs, we try to switch any PCI ATA controller to 1103 * fully native mode 1104 */ 1105 if (_machine != _MACH_Pmac) 1106 return; 1107 /* Some controllers don't have the class IDE */ 1108 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1109 switch(dev->device) { 1110 case PCI_DEVICE_ID_PROMISE_20246: 1111 case PCI_DEVICE_ID_PROMISE_20262: 1112 case PCI_DEVICE_ID_PROMISE_20263: 1113 case PCI_DEVICE_ID_PROMISE_20265: 1114 case PCI_DEVICE_ID_PROMISE_20267: 1115 case PCI_DEVICE_ID_PROMISE_20268: 1116 case PCI_DEVICE_ID_PROMISE_20269: 1117 case PCI_DEVICE_ID_PROMISE_20270: 1118 case PCI_DEVICE_ID_PROMISE_20271: 1119 case PCI_DEVICE_ID_PROMISE_20275: 1120 case PCI_DEVICE_ID_PROMISE_20276: 1121 case PCI_DEVICE_ID_PROMISE_20277: 1122 goto good; 1123 } 1124 /* Others, check PCI class */ 1125 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1126 return; 1127 good: 1128 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1129 if ((progif & 5) != 5) { 1130 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev)); 1131 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1132 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1133 (progif & 5) != 5) 1134 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1135 } 1136 } 1137 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1138 #endif 1139 1140 /* 1141 * Disable second function on K2-SATA, it's broken 1142 * and disable IO BARs on first one 1143 */ 1144 static void fixup_k2_sata(struct pci_dev* dev) 1145 { 1146 int i; 1147 u16 cmd; 1148 1149 if (PCI_FUNC(dev->devfn) > 0) { 1150 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1151 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1152 pci_write_config_word(dev, PCI_COMMAND, cmd); 1153 for (i = 0; i < 6; i++) { 1154 dev->resource[i].start = dev->resource[i].end = 0; 1155 dev->resource[i].flags = 0; 1156 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0); 1157 } 1158 } else { 1159 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1160 cmd &= ~PCI_COMMAND_IO; 1161 pci_write_config_word(dev, PCI_COMMAND, cmd); 1162 for (i = 0; i < 5; i++) { 1163 dev->resource[i].start = dev->resource[i].end = 0; 1164 dev->resource[i].flags = 0; 1165 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0); 1166 } 1167 } 1168 } 1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1170 1171