1 /* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/bootmem.h> 19 20 #include <asm/sections.h> 21 #include <asm/io.h> 22 #include <asm/prom.h> 23 #include <asm/pci-bridge.h> 24 #include <asm/machdep.h> 25 #include <asm/pmac_feature.h> 26 #include <asm/grackle.h> 27 #ifdef CONFIG_PPC64 28 //#include <asm/iommu.h> 29 #include <asm/ppc-pci.h> 30 #endif 31 32 #undef DEBUG 33 34 #ifdef DEBUG 35 #define DBG(x...) printk(x) 36 #else 37 #define DBG(x...) 38 #endif 39 40 static int add_bridge(struct device_node *dev); 41 42 /* XXX Could be per-controller, but I don't think we risk anything by 43 * assuming we won't have both UniNorth and Bandit */ 44 static int has_uninorth; 45 #ifdef CONFIG_PPC64 46 static struct pci_controller *u3_agp; 47 static struct pci_controller *u4_pcie; 48 static struct pci_controller *u3_ht; 49 #endif /* CONFIG_PPC64 */ 50 51 extern u8 pci_cache_line_size; 52 extern int pcibios_assign_bus_offset; 53 54 struct device_node *k2_skiplist[2]; 55 56 /* 57 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 58 */ 59 #define BANDIT_DEVID_2 8 60 #define BANDIT_REVID 3 61 62 #define BANDIT_DEVNUM 11 63 #define BANDIT_MAGIC 0x50 64 #define BANDIT_COHERENT 0x40 65 66 static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 67 { 68 for (; node != 0;node = node->sibling) { 69 int * bus_range; 70 unsigned int *class_code; 71 int len; 72 73 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 74 class_code = (unsigned int *) get_property(node, "class-code", NULL); 75 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 76 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 77 continue; 78 bus_range = (int *) get_property(node, "bus-range", &len); 79 if (bus_range != NULL && len > 2 * sizeof(int)) { 80 if (bus_range[1] > higher) 81 higher = bus_range[1]; 82 } 83 higher = fixup_one_level_bus_range(node->child, higher); 84 } 85 return higher; 86 } 87 88 /* This routine fixes the "bus-range" property of all bridges in the 89 * system since they tend to have their "last" member wrong on macs 90 * 91 * Note that the bus numbers manipulated here are OF bus numbers, they 92 * are not Linux bus numbers. 93 */ 94 static void __init fixup_bus_range(struct device_node *bridge) 95 { 96 int * bus_range; 97 int len; 98 99 /* Lookup the "bus-range" property for the hose */ 100 bus_range = (int *) get_property(bridge, "bus-range", &len); 101 if (bus_range == NULL || len < 2 * sizeof(int)) 102 return; 103 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 104 } 105 106 /* 107 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 108 * 109 * The "Bandit" version is present in all early PCI PowerMacs, 110 * and up to the first ones using Grackle. Some machines may 111 * have 2 bandit controllers (2 PCI busses). 112 * 113 * "Chaos" is used in some "Bandit"-type machines as a bridge 114 * for the separate display bus. It is accessed the same 115 * way as bandit, but cannot be probed for devices. It therefore 116 * has its own config access functions. 117 * 118 * The "UniNorth" version is present in all Core99 machines 119 * (iBook, G4, new IMacs, and all the recent Apple machines). 120 * It contains 3 controllers in one ASIC. 121 * 122 * The U3 is the bridge used on G5 machines. It contains an 123 * AGP bus which is dealt with the old UniNorth access routines 124 * and a HyperTransport bus which uses its own set of access 125 * functions. 126 */ 127 128 #define MACRISC_CFA0(devfn, off) \ 129 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ 130 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 131 | (((unsigned int)(off)) & 0xFCUL)) 132 133 #define MACRISC_CFA1(bus, devfn, off) \ 134 ((((unsigned int)(bus)) << 16) \ 135 |(((unsigned int)(devfn)) << 8) \ 136 |(((unsigned int)(off)) & 0xFCUL) \ 137 |1UL) 138 139 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, 140 u8 bus, u8 dev_fn, u8 offset) 141 { 142 unsigned int caddr; 143 144 if (bus == hose->first_busno) { 145 if (dev_fn < (11 << 3)) 146 return NULL; 147 caddr = MACRISC_CFA0(dev_fn, offset); 148 } else 149 caddr = MACRISC_CFA1(bus, dev_fn, offset); 150 151 /* Uninorth will return garbage if we don't read back the value ! */ 152 do { 153 out_le32(hose->cfg_addr, caddr); 154 } while (in_le32(hose->cfg_addr) != caddr); 155 156 offset &= has_uninorth ? 0x07 : 0x03; 157 return hose->cfg_data + offset; 158 } 159 160 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, 161 int offset, int len, u32 *val) 162 { 163 struct pci_controller *hose; 164 volatile void __iomem *addr; 165 166 hose = pci_bus_to_host(bus); 167 if (hose == NULL) 168 return PCIBIOS_DEVICE_NOT_FOUND; 169 if (offset >= 0x100) 170 return PCIBIOS_BAD_REGISTER_NUMBER; 171 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 172 if (!addr) 173 return PCIBIOS_DEVICE_NOT_FOUND; 174 /* 175 * Note: the caller has already checked that offset is 176 * suitably aligned and that len is 1, 2 or 4. 177 */ 178 switch (len) { 179 case 1: 180 *val = in_8(addr); 181 break; 182 case 2: 183 *val = in_le16(addr); 184 break; 185 default: 186 *val = in_le32(addr); 187 break; 188 } 189 return PCIBIOS_SUCCESSFUL; 190 } 191 192 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, 193 int offset, int len, u32 val) 194 { 195 struct pci_controller *hose; 196 volatile void __iomem *addr; 197 198 hose = pci_bus_to_host(bus); 199 if (hose == NULL) 200 return PCIBIOS_DEVICE_NOT_FOUND; 201 if (offset >= 0x100) 202 return PCIBIOS_BAD_REGISTER_NUMBER; 203 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 204 if (!addr) 205 return PCIBIOS_DEVICE_NOT_FOUND; 206 /* 207 * Note: the caller has already checked that offset is 208 * suitably aligned and that len is 1, 2 or 4. 209 */ 210 switch (len) { 211 case 1: 212 out_8(addr, val); 213 (void) in_8(addr); 214 break; 215 case 2: 216 out_le16(addr, val); 217 (void) in_le16(addr); 218 break; 219 default: 220 out_le32(addr, val); 221 (void) in_le32(addr); 222 break; 223 } 224 return PCIBIOS_SUCCESSFUL; 225 } 226 227 static struct pci_ops macrisc_pci_ops = 228 { 229 macrisc_read_config, 230 macrisc_write_config 231 }; 232 233 #ifdef CONFIG_PPC32 234 /* 235 * Verify that a specific (bus, dev_fn) exists on chaos 236 */ 237 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 238 { 239 struct device_node *np; 240 u32 *vendor, *device; 241 242 if (offset >= 0x100) 243 return PCIBIOS_BAD_REGISTER_NUMBER; 244 np = pci_busdev_to_OF_node(bus, devfn); 245 if (np == NULL) 246 return PCIBIOS_DEVICE_NOT_FOUND; 247 248 vendor = (u32 *)get_property(np, "vendor-id", NULL); 249 device = (u32 *)get_property(np, "device-id", NULL); 250 if (vendor == NULL || device == NULL) 251 return PCIBIOS_DEVICE_NOT_FOUND; 252 253 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 254 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 255 return PCIBIOS_BAD_REGISTER_NUMBER; 256 257 return PCIBIOS_SUCCESSFUL; 258 } 259 260 static int 261 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 262 int len, u32 *val) 263 { 264 int result = chaos_validate_dev(bus, devfn, offset); 265 if (result == PCIBIOS_BAD_REGISTER_NUMBER) 266 *val = ~0U; 267 if (result != PCIBIOS_SUCCESSFUL) 268 return result; 269 return macrisc_read_config(bus, devfn, offset, len, val); 270 } 271 272 static int 273 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 274 int len, u32 val) 275 { 276 int result = chaos_validate_dev(bus, devfn, offset); 277 if (result != PCIBIOS_SUCCESSFUL) 278 return result; 279 return macrisc_write_config(bus, devfn, offset, len, val); 280 } 281 282 static struct pci_ops chaos_pci_ops = 283 { 284 chaos_read_config, 285 chaos_write_config 286 }; 287 288 static void __init setup_chaos(struct pci_controller *hose, 289 struct resource *addr) 290 { 291 /* assume a `chaos' bridge */ 292 hose->ops = &chaos_pci_ops; 293 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 294 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 295 } 296 #endif /* CONFIG_PPC32 */ 297 298 #ifdef CONFIG_PPC64 299 /* 300 * These versions of U3 HyperTransport config space access ops do not 301 * implement self-view of the HT host yet 302 */ 303 304 /* 305 * This function deals with some "special cases" devices. 306 * 307 * 0 -> No special case 308 * 1 -> Skip the device but act as if the access was successfull 309 * (return 0xff's on reads, eventually, cache config space 310 * accesses in a later version) 311 * -1 -> Hide the device (unsuccessful acess) 312 */ 313 static int u3_ht_skip_device(struct pci_controller *hose, 314 struct pci_bus *bus, unsigned int devfn) 315 { 316 struct device_node *busdn, *dn; 317 int i; 318 319 /* We only allow config cycles to devices that are in OF device-tree 320 * as we are apparently having some weird things going on with some 321 * revs of K2 on recent G5s 322 */ 323 if (bus->self) 324 busdn = pci_device_to_OF_node(bus->self); 325 else 326 busdn = hose->arch_data; 327 for (dn = busdn->child; dn; dn = dn->sibling) 328 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) 329 break; 330 if (dn == NULL) 331 return -1; 332 333 /* 334 * When a device in K2 is powered down, we die on config 335 * cycle accesses. Fix that here. 336 */ 337 for (i=0; i<2; i++) 338 if (k2_skiplist[i] == dn) 339 return 1; 340 341 return 0; 342 } 343 344 #define U3_HT_CFA0(devfn, off) \ 345 ((((unsigned int)devfn) << 8) | offset) 346 #define U3_HT_CFA1(bus, devfn, off) \ 347 (U3_HT_CFA0(devfn, off) \ 348 + (((unsigned int)bus) << 16) \ 349 + 0x01000000UL) 350 351 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, 352 u8 bus, u8 devfn, u8 offset) 353 { 354 if (bus == hose->first_busno) { 355 /* For now, we don't self probe U3 HT bridge */ 356 if (PCI_SLOT(devfn) == 0) 357 return NULL; 358 return hose->cfg_data + U3_HT_CFA0(devfn, offset); 359 } else 360 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); 361 } 362 363 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 364 int offset, int len, u32 *val) 365 { 366 struct pci_controller *hose; 367 volatile void __iomem *addr; 368 369 hose = pci_bus_to_host(bus); 370 if (hose == NULL) 371 return PCIBIOS_DEVICE_NOT_FOUND; 372 if (offset >= 0x100) 373 return PCIBIOS_BAD_REGISTER_NUMBER; 374 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 375 if (!addr) 376 return PCIBIOS_DEVICE_NOT_FOUND; 377 378 switch (u3_ht_skip_device(hose, bus, devfn)) { 379 case 0: 380 break; 381 case 1: 382 switch (len) { 383 case 1: 384 *val = 0xff; break; 385 case 2: 386 *val = 0xffff; break; 387 default: 388 *val = 0xfffffffful; break; 389 } 390 return PCIBIOS_SUCCESSFUL; 391 default: 392 return PCIBIOS_DEVICE_NOT_FOUND; 393 } 394 395 /* 396 * Note: the caller has already checked that offset is 397 * suitably aligned and that len is 1, 2 or 4. 398 */ 399 switch (len) { 400 case 1: 401 *val = in_8(addr); 402 break; 403 case 2: 404 *val = in_le16(addr); 405 break; 406 default: 407 *val = in_le32(addr); 408 break; 409 } 410 return PCIBIOS_SUCCESSFUL; 411 } 412 413 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 414 int offset, int len, u32 val) 415 { 416 struct pci_controller *hose; 417 volatile void __iomem *addr; 418 419 hose = pci_bus_to_host(bus); 420 if (hose == NULL) 421 return PCIBIOS_DEVICE_NOT_FOUND; 422 if (offset >= 0x100) 423 return PCIBIOS_BAD_REGISTER_NUMBER; 424 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 425 if (!addr) 426 return PCIBIOS_DEVICE_NOT_FOUND; 427 428 switch (u3_ht_skip_device(hose, bus, devfn)) { 429 case 0: 430 break; 431 case 1: 432 return PCIBIOS_SUCCESSFUL; 433 default: 434 return PCIBIOS_DEVICE_NOT_FOUND; 435 } 436 437 /* 438 * Note: the caller has already checked that offset is 439 * suitably aligned and that len is 1, 2 or 4. 440 */ 441 switch (len) { 442 case 1: 443 out_8(addr, val); 444 (void) in_8(addr); 445 break; 446 case 2: 447 out_le16(addr, val); 448 (void) in_le16(addr); 449 break; 450 default: 451 out_le32((u32 __iomem *)addr, val); 452 (void) in_le32(addr); 453 break; 454 } 455 return PCIBIOS_SUCCESSFUL; 456 } 457 458 static struct pci_ops u3_ht_pci_ops = 459 { 460 u3_ht_read_config, 461 u3_ht_write_config 462 }; 463 464 #define U4_PCIE_CFA0(devfn, off) \ 465 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ 466 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 467 | ((((unsigned int)(off)) >> 8) << 28) \ 468 | (((unsigned int)(off)) & 0xfcU)) 469 470 #define U4_PCIE_CFA1(bus, devfn, off) \ 471 ((((unsigned int)(bus)) << 16) \ 472 |(((unsigned int)(devfn)) << 8) \ 473 | ((((unsigned int)(off)) >> 8) << 28) \ 474 |(((unsigned int)(off)) & 0xfcU) \ 475 |1UL) 476 477 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 478 u8 bus, u8 dev_fn, int offset) 479 { 480 unsigned int caddr; 481 482 if (bus == hose->first_busno) { 483 caddr = U4_PCIE_CFA0(dev_fn, offset); 484 } else 485 caddr = U4_PCIE_CFA1(bus, dev_fn, offset); 486 487 /* Uninorth will return garbage if we don't read back the value ! */ 488 do { 489 out_le32(hose->cfg_addr, caddr); 490 } while (in_le32(hose->cfg_addr) != caddr); 491 492 offset &= 0x03; 493 return hose->cfg_data + offset; 494 } 495 496 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 497 int offset, int len, u32 *val) 498 { 499 struct pci_controller *hose; 500 volatile void __iomem *addr; 501 502 hose = pci_bus_to_host(bus); 503 if (hose == NULL) 504 return PCIBIOS_DEVICE_NOT_FOUND; 505 if (offset >= 0x1000) 506 return PCIBIOS_BAD_REGISTER_NUMBER; 507 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 508 if (!addr) 509 return PCIBIOS_DEVICE_NOT_FOUND; 510 /* 511 * Note: the caller has already checked that offset is 512 * suitably aligned and that len is 1, 2 or 4. 513 */ 514 switch (len) { 515 case 1: 516 *val = in_8(addr); 517 break; 518 case 2: 519 *val = in_le16(addr); 520 break; 521 default: 522 *val = in_le32(addr); 523 break; 524 } 525 return PCIBIOS_SUCCESSFUL; 526 } 527 528 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 529 int offset, int len, u32 val) 530 { 531 struct pci_controller *hose; 532 volatile void __iomem *addr; 533 534 hose = pci_bus_to_host(bus); 535 if (hose == NULL) 536 return PCIBIOS_DEVICE_NOT_FOUND; 537 if (offset >= 0x1000) 538 return PCIBIOS_BAD_REGISTER_NUMBER; 539 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 540 if (!addr) 541 return PCIBIOS_DEVICE_NOT_FOUND; 542 /* 543 * Note: the caller has already checked that offset is 544 * suitably aligned and that len is 1, 2 or 4. 545 */ 546 switch (len) { 547 case 1: 548 out_8(addr, val); 549 (void) in_8(addr); 550 break; 551 case 2: 552 out_le16(addr, val); 553 (void) in_le16(addr); 554 break; 555 default: 556 out_le32(addr, val); 557 (void) in_le32(addr); 558 break; 559 } 560 return PCIBIOS_SUCCESSFUL; 561 } 562 563 static struct pci_ops u4_pcie_pci_ops = 564 { 565 u4_pcie_read_config, 566 u4_pcie_write_config 567 }; 568 569 #endif /* CONFIG_PPC64 */ 570 571 #ifdef CONFIG_PPC32 572 /* 573 * For a bandit bridge, turn on cache coherency if necessary. 574 * N.B. we could clean this up using the hose ops directly. 575 */ 576 static void __init init_bandit(struct pci_controller *bp) 577 { 578 unsigned int vendev, magic; 579 int rev; 580 581 /* read the word at offset 0 in config space for device 11 */ 582 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 583 udelay(2); 584 vendev = in_le32(bp->cfg_data); 585 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 586 PCI_VENDOR_ID_APPLE) { 587 /* read the revision id */ 588 out_le32(bp->cfg_addr, 589 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 590 udelay(2); 591 rev = in_8(bp->cfg_data); 592 if (rev != BANDIT_REVID) 593 printk(KERN_WARNING 594 "Unknown revision %d for bandit\n", rev); 595 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 596 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 597 return; 598 } 599 600 /* read the word at offset 0x50 */ 601 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 602 udelay(2); 603 magic = in_le32(bp->cfg_data); 604 if ((magic & BANDIT_COHERENT) != 0) 605 return; 606 magic |= BANDIT_COHERENT; 607 udelay(2); 608 out_le32(bp->cfg_data, magic); 609 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 610 } 611 612 /* 613 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 614 */ 615 static void __init init_p2pbridge(void) 616 { 617 struct device_node *p2pbridge; 618 struct pci_controller* hose; 619 u8 bus, devfn; 620 u16 val; 621 622 /* XXX it would be better here to identify the specific 623 PCI-PCI bridge chip we have. */ 624 if ((p2pbridge = find_devices("pci-bridge")) == 0 625 || p2pbridge->parent == NULL 626 || strcmp(p2pbridge->parent->name, "pci") != 0) 627 return; 628 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 629 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 630 return; 631 } 632 /* Warning: At this point, we have not yet renumbered all busses. 633 * So we must use OF walking to find out hose 634 */ 635 hose = pci_find_hose_for_OF_device(p2pbridge); 636 if (!hose) { 637 DBG("Can't find hose for PCI<->PCI bridge\n"); 638 return; 639 } 640 if (early_read_config_word(hose, bus, devfn, 641 PCI_BRIDGE_CONTROL, &val) < 0) { 642 printk(KERN_ERR "init_p2pbridge: couldn't read bridge" 643 " control\n"); 644 return; 645 } 646 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 647 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 648 } 649 650 /* 651 * Some Apple desktop machines have a NEC PD720100A USB2 controller 652 * on the motherboard. Open Firmware, on these, will disable the 653 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 654 * code re-enables it ;) 655 */ 656 static void __init fixup_nec_usb2(void) 657 { 658 struct device_node *nec; 659 660 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { 661 struct pci_controller *hose; 662 u32 data, *prop; 663 u8 bus, devfn; 664 665 prop = (u32 *)get_property(nec, "vendor-id", NULL); 666 if (prop == NULL) 667 continue; 668 if (0x1033 != *prop) 669 continue; 670 prop = (u32 *)get_property(nec, "device-id", NULL); 671 if (prop == NULL) 672 continue; 673 if (0x0035 != *prop) 674 continue; 675 prop = (u32 *)get_property(nec, "reg", NULL); 676 if (prop == NULL) 677 continue; 678 devfn = (prop[0] >> 8) & 0xff; 679 bus = (prop[0] >> 16) & 0xff; 680 if (PCI_FUNC(devfn) != 0) 681 continue; 682 hose = pci_find_hose_for_OF_device(nec); 683 if (!hose) 684 continue; 685 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 686 if (data & 1UL) { 687 printk("Found NEC PD720100A USB2 chip with disabled" 688 " EHCI, fixing up...\n"); 689 data &= ~1UL; 690 early_write_config_dword(hose, bus, devfn, 0xe4, data); 691 early_write_config_byte(hose, bus, 692 devfn | 2, PCI_INTERRUPT_LINE, 693 nec->intrs[0].line); 694 } 695 } 696 } 697 698 static void __init setup_bandit(struct pci_controller *hose, 699 struct resource *addr) 700 { 701 hose->ops = ¯isc_pci_ops; 702 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 703 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 704 init_bandit(hose); 705 } 706 707 static int __init setup_uninorth(struct pci_controller *hose, 708 struct resource *addr) 709 { 710 pci_assign_all_buses = 1; 711 has_uninorth = 1; 712 hose->ops = ¯isc_pci_ops; 713 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 714 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 715 /* We "know" that the bridge at f2000000 has the PCI slots. */ 716 return addr->start == 0xf2000000; 717 } 718 #endif /* CONFIG_PPC32 */ 719 720 #ifdef CONFIG_PPC64 721 static void __init setup_u3_agp(struct pci_controller* hose) 722 { 723 /* On G5, we move AGP up to high bus number so we don't need 724 * to reassign bus numbers for HT. If we ever have P2P bridges 725 * on AGP, we'll have to move pci_assign_all_busses to the 726 * pci_controller structure so we enable it for AGP and not for 727 * HT childs. 728 * We hard code the address because of the different size of 729 * the reg address cell, we shall fix that by killing struct 730 * reg_property and using some accessor functions instead 731 */ 732 hose->first_busno = 0xf0; 733 hose->last_busno = 0xff; 734 has_uninorth = 1; 735 hose->ops = ¯isc_pci_ops; 736 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 737 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 738 u3_agp = hose; 739 } 740 741 static void __init setup_u4_pcie(struct pci_controller* hose) 742 { 743 /* We currently only implement the "non-atomic" config space, to 744 * be optimised later. 745 */ 746 hose->ops = &u4_pcie_pci_ops; 747 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 748 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 749 750 /* The bus contains a bridge from root -> device, we need to 751 * make it visible on bus 0 so that we pick the right type 752 * of config cycles. If we didn't, we would have to force all 753 * config cycles to be type 1. So we override the "bus-range" 754 * property here 755 */ 756 hose->first_busno = 0x00; 757 hose->last_busno = 0xff; 758 u4_pcie = hose; 759 } 760 761 static void __init setup_u3_ht(struct pci_controller* hose) 762 { 763 struct device_node *np = (struct device_node *)hose->arch_data; 764 struct pci_controller *other = NULL; 765 int i, cur; 766 767 768 hose->ops = &u3_ht_pci_ops; 769 770 /* We hard code the address because of the different size of 771 * the reg address cell, we shall fix that by killing struct 772 * reg_property and using some accessor functions instead 773 */ 774 hose->cfg_data = ioremap(0xf2000000, 0x02000000); 775 776 /* 777 * /ht node doesn't expose a "ranges" property, so we "remove" 778 * regions that have been allocated to AGP. So far, this version of 779 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions 780 * to /ht. We need to fix that sooner or later by either parsing all 781 * child "ranges" properties or figuring out the U3 address space 782 * decoding logic and then read its configuration register (if any). 783 */ 784 hose->io_base_phys = 0xf4000000; 785 hose->pci_io_size = 0x00400000; 786 hose->io_resource.name = np->full_name; 787 hose->io_resource.start = 0; 788 hose->io_resource.end = 0x003fffff; 789 hose->io_resource.flags = IORESOURCE_IO; 790 hose->pci_mem_offset = 0; 791 hose->first_busno = 0; 792 hose->last_busno = 0xef; 793 hose->mem_resources[0].name = np->full_name; 794 hose->mem_resources[0].start = 0x80000000; 795 hose->mem_resources[0].end = 0xefffffff; 796 hose->mem_resources[0].flags = IORESOURCE_MEM; 797 798 u3_ht = hose; 799 800 if (u3_agp != NULL) 801 other = u3_agp; 802 else if (u4_pcie != NULL) 803 other = u4_pcie; 804 805 if (other == NULL) { 806 DBG("U3/4 has no AGP/PCIE, using full resource range\n"); 807 return; 808 } 809 810 /* Fixup bus range vs. PCIE */ 811 if (u4_pcie) 812 hose->last_busno = u4_pcie->first_busno - 1; 813 814 /* We "remove" the AGP resources from the resources allocated to HT, 815 * that is we create "holes". However, that code does assumptions 816 * that so far happen to be true (cross fingers...), typically that 817 * resources in the AGP node are properly ordered 818 */ 819 cur = 0; 820 for (i=0; i<3; i++) { 821 struct resource *res = &other->mem_resources[i]; 822 if (res->flags != IORESOURCE_MEM) 823 continue; 824 /* We don't care about "fine" resources */ 825 if (res->start >= 0xf0000000) 826 continue; 827 /* Check if it's just a matter of "shrinking" us in one 828 * direction 829 */ 830 if (hose->mem_resources[cur].start == res->start) { 831 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", 832 cur, hose->mem_resources[cur].start, 833 res->end + 1); 834 hose->mem_resources[cur].start = res->end + 1; 835 continue; 836 } 837 if (hose->mem_resources[cur].end == res->end) { 838 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", 839 cur, hose->mem_resources[cur].end, 840 res->start - 1); 841 hose->mem_resources[cur].end = res->start - 1; 842 continue; 843 } 844 /* No, it's not the case, we need a hole */ 845 if (cur == 2) { 846 /* not enough resources for a hole, we drop part 847 * of the range 848 */ 849 printk(KERN_WARNING "Running out of resources" 850 " for /ht host !\n"); 851 hose->mem_resources[cur].end = res->start - 1; 852 continue; 853 } 854 cur++; 855 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", 856 cur-1, res->start - 1, cur, res->end + 1); 857 hose->mem_resources[cur].name = np->full_name; 858 hose->mem_resources[cur].flags = IORESOURCE_MEM; 859 hose->mem_resources[cur].start = res->end + 1; 860 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; 861 hose->mem_resources[cur-1].end = res->start - 1; 862 } 863 } 864 #endif /* CONFIG_PPC64 */ 865 866 /* 867 * We assume that if we have a G3 powermac, we have one bridge called 868 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 869 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 870 */ 871 static int __init add_bridge(struct device_node *dev) 872 { 873 int len; 874 struct pci_controller *hose; 875 struct resource rsrc; 876 char *disp_name; 877 int *bus_range; 878 int primary = 1, has_address = 0; 879 880 DBG("Adding PCI host bridge %s\n", dev->full_name); 881 882 /* Fetch host bridge registers address */ 883 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 884 885 /* Get bus range if any */ 886 bus_range = (int *) get_property(dev, "bus-range", &len); 887 if (bus_range == NULL || len < 2 * sizeof(int)) { 888 printk(KERN_WARNING "Can't get bus-range for %s, assume" 889 " bus 0\n", dev->full_name); 890 } 891 892 /* XXX Different prototypes, to be merged */ 893 #ifdef CONFIG_PPC64 894 hose = pcibios_alloc_controller(dev); 895 #else 896 hose = pcibios_alloc_controller(); 897 #endif 898 if (!hose) 899 return -ENOMEM; 900 hose->arch_data = dev; 901 hose->first_busno = bus_range ? bus_range[0] : 0; 902 hose->last_busno = bus_range ? bus_range[1] : 0xff; 903 904 disp_name = NULL; 905 906 /* 64 bits only bridges */ 907 #ifdef CONFIG_PPC64 908 if (device_is_compatible(dev, "u3-agp")) { 909 setup_u3_agp(hose); 910 disp_name = "U3-AGP"; 911 primary = 0; 912 } else if (device_is_compatible(dev, "u3-ht")) { 913 setup_u3_ht(hose); 914 disp_name = "U3-HT"; 915 primary = 1; 916 } else if (device_is_compatible(dev, "u4-pcie")) { 917 setup_u4_pcie(hose); 918 disp_name = "U4-PCIE"; 919 primary = 0; 920 } 921 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" 922 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); 923 #endif /* CONFIG_PPC64 */ 924 925 /* 32 bits only bridges */ 926 #ifdef CONFIG_PPC32 927 if (device_is_compatible(dev, "uni-north")) { 928 primary = setup_uninorth(hose, &rsrc); 929 disp_name = "UniNorth"; 930 } else if (strcmp(dev->name, "pci") == 0) { 931 /* XXX assume this is a mpc106 (grackle) */ 932 setup_grackle(hose); 933 disp_name = "Grackle (MPC106)"; 934 } else if (strcmp(dev->name, "bandit") == 0) { 935 setup_bandit(hose, &rsrc); 936 disp_name = "Bandit"; 937 } else if (strcmp(dev->name, "chaos") == 0) { 938 setup_chaos(hose, &rsrc); 939 disp_name = "Chaos"; 940 primary = 0; 941 } 942 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " 943 "Firmware bus number: %d->%d\n", 944 disp_name, (unsigned long long)rsrc.start, hose->first_busno, 945 hose->last_busno); 946 #endif /* CONFIG_PPC32 */ 947 948 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 949 hose, hose->cfg_addr, hose->cfg_data); 950 951 /* Interpret the "ranges" property */ 952 /* This also maps the I/O region and sets isa_io/mem_base */ 953 pci_process_bridge_OF_ranges(hose, dev, primary); 954 955 /* Fixup "bus-range" OF property */ 956 fixup_bus_range(dev); 957 958 return 0; 959 } 960 961 static void __init pcibios_fixup_OF_interrupts(void) 962 { 963 struct pci_dev* dev = NULL; 964 965 /* 966 * Open Firmware often doesn't initialize the 967 * PCI_INTERRUPT_LINE config register properly, so we 968 * should find the device node and apply the interrupt 969 * obtained from the OF device-tree 970 */ 971 for_each_pci_dev(dev) { 972 struct device_node *node; 973 node = pci_device_to_OF_node(dev); 974 /* this is the node, see if it has interrupts */ 975 if (node && node->n_intrs > 0) 976 dev->irq = node->intrs[0].line; 977 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 978 } 979 } 980 981 void __init pmac_pcibios_fixup(void) 982 { 983 /* Fixup interrupts according to OF tree */ 984 pcibios_fixup_OF_interrupts(); 985 } 986 987 #ifdef CONFIG_PPC64 988 static void __init pmac_fixup_phb_resources(void) 989 { 990 struct pci_controller *hose, *tmp; 991 992 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 993 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", 994 hose->global_number, 995 hose->io_resource.start, hose->io_resource.end); 996 } 997 } 998 #endif 999 1000 void __init pmac_pci_init(void) 1001 { 1002 struct device_node *np, *root; 1003 struct device_node *ht = NULL; 1004 1005 root = of_find_node_by_path("/"); 1006 if (root == NULL) { 1007 printk(KERN_CRIT "pmac_pci_init: can't find root " 1008 "of device tree\n"); 1009 return; 1010 } 1011 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 1012 if (np->name == NULL) 1013 continue; 1014 if (strcmp(np->name, "bandit") == 0 1015 || strcmp(np->name, "chaos") == 0 1016 || strcmp(np->name, "pci") == 0) { 1017 if (add_bridge(np) == 0) 1018 of_node_get(np); 1019 } 1020 if (strcmp(np->name, "ht") == 0) { 1021 of_node_get(np); 1022 ht = np; 1023 } 1024 } 1025 of_node_put(root); 1026 1027 #ifdef CONFIG_PPC64 1028 /* Probe HT last as it relies on the agp resources to be already 1029 * setup 1030 */ 1031 if (ht && add_bridge(ht) != 0) 1032 of_node_put(ht); 1033 1034 /* 1035 * We need to call pci_setup_phb_io for the HT bridge first 1036 * so it gets the I/O port numbers starting at 0, and we 1037 * need to call it for the AGP bridge after that so it gets 1038 * small positive I/O port numbers. 1039 */ 1040 if (u3_ht) 1041 pci_setup_phb_io(u3_ht, 1); 1042 if (u3_agp) 1043 pci_setup_phb_io(u3_agp, 0); 1044 if (u4_pcie) 1045 pci_setup_phb_io(u4_pcie, 0); 1046 1047 /* 1048 * On ppc64, fixup the IO resources on our host bridges as 1049 * the common code does it only for children of the host bridges 1050 */ 1051 pmac_fixup_phb_resources(); 1052 1053 /* Setup the linkage between OF nodes and PHBs */ 1054 pci_devs_phb_init(); 1055 1056 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 1057 * assume there is no P2P bridge on the AGP bus, which should be a 1058 * safe assumptions for now. We should do something better in the 1059 * future though 1060 */ 1061 if (u3_agp) { 1062 struct device_node *np = u3_agp->arch_data; 1063 PCI_DN(np)->busno = 0xf0; 1064 for (np = np->child; np; np = np->sibling) 1065 PCI_DN(np)->busno = 0xf0; 1066 } 1067 /* pmac_check_ht_link(); */ 1068 1069 /* Tell pci.c to not use the common resource allocation mechanism */ 1070 pci_probe_only = 1; 1071 1072 #else /* CONFIG_PPC64 */ 1073 init_p2pbridge(); 1074 fixup_nec_usb2(); 1075 1076 /* We are still having some issues with the Xserve G4, enabling 1077 * some offset between bus number and domains for now when we 1078 * assign all busses should help for now 1079 */ 1080 if (pci_assign_all_buses) 1081 pcibios_assign_bus_offset = 0x10; 1082 #endif 1083 } 1084 1085 int 1086 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) 1087 { 1088 struct device_node* node; 1089 int updatecfg = 0; 1090 int uninorth_child; 1091 1092 node = pci_device_to_OF_node(dev); 1093 1094 /* We don't want to enable USB controllers absent from the OF tree 1095 * (iBook second controller) 1096 */ 1097 if (dev->vendor == PCI_VENDOR_ID_APPLE 1098 && dev->class == PCI_CLASS_SERIAL_USB_OHCI 1099 && !node) { 1100 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 1101 pci_name(dev)); 1102 return -EINVAL; 1103 } 1104 1105 if (!node) 1106 return 0; 1107 1108 uninorth_child = node->parent && 1109 device_is_compatible(node->parent, "uni-north"); 1110 1111 /* Firewire & GMAC were disabled after PCI probe, the driver is 1112 * claiming them, we must re-enable them now. 1113 */ 1114 if (uninorth_child && !strcmp(node->name, "firewire") && 1115 (device_is_compatible(node, "pci106b,18") || 1116 device_is_compatible(node, "pci106b,30") || 1117 device_is_compatible(node, "pci11c1,5811"))) { 1118 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 1119 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 1120 updatecfg = 1; 1121 } 1122 if (uninorth_child && !strcmp(node->name, "ethernet") && 1123 device_is_compatible(node, "gmac")) { 1124 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 1125 updatecfg = 1; 1126 } 1127 1128 if (updatecfg) { 1129 u16 cmd; 1130 1131 /* 1132 * Make sure PCI is correctly configured 1133 * 1134 * We use old pci_bios versions of the function since, by 1135 * default, gmac is not powered up, and so will be absent 1136 * from the kernel initial PCI lookup. 1137 * 1138 * Should be replaced by 2.4 new PCI mechanisms and really 1139 * register the device. 1140 */ 1141 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1142 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 1143 | PCI_COMMAND_INVALIDATE; 1144 pci_write_config_word(dev, PCI_COMMAND, cmd); 1145 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1146 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1147 L1_CACHE_BYTES >> 2); 1148 } 1149 1150 return 0; 1151 } 1152 1153 /* We power down some devices after they have been probed. They'll 1154 * be powered back on later on 1155 */ 1156 void __init pmac_pcibios_after_init(void) 1157 { 1158 struct device_node* nd; 1159 1160 #ifdef CONFIG_BLK_DEV_IDE 1161 struct pci_dev *dev = NULL; 1162 1163 /* OF fails to initialize IDE controllers on macs 1164 * (and maybe other machines) 1165 * 1166 * Ideally, this should be moved to the IDE layer, but we need 1167 * to check specifically with Andre Hedrick how to do it cleanly 1168 * since the common IDE code seem to care about the fact that the 1169 * BIOS may have disabled a controller. 1170 * 1171 * -- BenH 1172 */ 1173 for_each_pci_dev(dev) { 1174 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) 1175 pci_enable_device(dev); 1176 } 1177 #endif /* CONFIG_BLK_DEV_IDE */ 1178 1179 nd = find_devices("firewire"); 1180 while (nd) { 1181 if (nd->parent && (device_is_compatible(nd, "pci106b,18") || 1182 device_is_compatible(nd, "pci106b,30") || 1183 device_is_compatible(nd, "pci11c1,5811")) 1184 && device_is_compatible(nd->parent, "uni-north")) { 1185 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1186 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1187 } 1188 nd = nd->next; 1189 } 1190 nd = find_devices("ethernet"); 1191 while (nd) { 1192 if (nd->parent && device_is_compatible(nd, "gmac") 1193 && device_is_compatible(nd->parent, "uni-north")) 1194 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1195 nd = nd->next; 1196 } 1197 } 1198 1199 #ifdef CONFIG_PPC32 1200 void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1201 { 1202 if (!machine_is(powermac)) 1203 return; 1204 /* 1205 * Fix the interrupt routing on the various cardbus bridges 1206 * used on powerbooks 1207 */ 1208 if (dev->vendor != PCI_VENDOR_ID_TI) 1209 return; 1210 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1211 dev->device == PCI_DEVICE_ID_TI_1131) { 1212 u8 val; 1213 /* Enable PCI interrupt */ 1214 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1215 pci_write_config_byte(dev, 0x91, val | 0x30); 1216 /* Disable ISA interrupt mode */ 1217 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1218 pci_write_config_byte(dev, 0x92, val & ~0x06); 1219 } 1220 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1221 dev->device == PCI_DEVICE_ID_TI_1211 || 1222 dev->device == PCI_DEVICE_ID_TI_1410 || 1223 dev->device == PCI_DEVICE_ID_TI_1510) { 1224 u8 val; 1225 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1226 signal out the MFUNC0 pin */ 1227 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1228 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1229 /* Disable ISA interrupt mode */ 1230 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1231 pci_write_config_byte(dev, 0x92, val & ~0x06); 1232 } 1233 } 1234 1235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1236 1237 void pmac_pci_fixup_pciata(struct pci_dev* dev) 1238 { 1239 u8 progif = 0; 1240 1241 /* 1242 * On PowerMacs, we try to switch any PCI ATA controller to 1243 * fully native mode 1244 */ 1245 if (!machine_is(powermac)) 1246 return; 1247 1248 /* Some controllers don't have the class IDE */ 1249 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1250 switch(dev->device) { 1251 case PCI_DEVICE_ID_PROMISE_20246: 1252 case PCI_DEVICE_ID_PROMISE_20262: 1253 case PCI_DEVICE_ID_PROMISE_20263: 1254 case PCI_DEVICE_ID_PROMISE_20265: 1255 case PCI_DEVICE_ID_PROMISE_20267: 1256 case PCI_DEVICE_ID_PROMISE_20268: 1257 case PCI_DEVICE_ID_PROMISE_20269: 1258 case PCI_DEVICE_ID_PROMISE_20270: 1259 case PCI_DEVICE_ID_PROMISE_20271: 1260 case PCI_DEVICE_ID_PROMISE_20275: 1261 case PCI_DEVICE_ID_PROMISE_20276: 1262 case PCI_DEVICE_ID_PROMISE_20277: 1263 goto good; 1264 } 1265 /* Others, check PCI class */ 1266 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1267 return; 1268 good: 1269 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1270 if ((progif & 5) != 5) { 1271 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", 1272 pci_name(dev)); 1273 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1274 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1275 (progif & 5) != 5) 1276 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1277 } 1278 } 1279 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1280 #endif 1281 1282 /* 1283 * Disable second function on K2-SATA, it's broken 1284 * and disable IO BARs on first one 1285 */ 1286 static void fixup_k2_sata(struct pci_dev* dev) 1287 { 1288 int i; 1289 u16 cmd; 1290 1291 if (PCI_FUNC(dev->devfn) > 0) { 1292 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1293 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1294 pci_write_config_word(dev, PCI_COMMAND, cmd); 1295 for (i = 0; i < 6; i++) { 1296 dev->resource[i].start = dev->resource[i].end = 0; 1297 dev->resource[i].flags = 0; 1298 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1299 0); 1300 } 1301 } else { 1302 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1303 cmd &= ~PCI_COMMAND_IO; 1304 pci_write_config_word(dev, PCI_COMMAND, cmd); 1305 for (i = 0; i < 5; i++) { 1306 dev->resource[i].start = dev->resource[i].end = 0; 1307 dev->resource[i].flags = 0; 1308 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1309 0); 1310 } 1311 } 1312 } 1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1314 1315