1 /* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/bootmem.h> 19 #include <linux/irq.h> 20 21 #include <asm/sections.h> 22 #include <asm/io.h> 23 #include <asm/prom.h> 24 #include <asm/pci-bridge.h> 25 #include <asm/machdep.h> 26 #include <asm/pmac_feature.h> 27 #include <asm/grackle.h> 28 #include <asm/ppc-pci.h> 29 30 #undef DEBUG 31 32 #ifdef DEBUG 33 #define DBG(x...) printk(x) 34 #else 35 #define DBG(x...) 36 #endif 37 38 /* XXX Could be per-controller, but I don't think we risk anything by 39 * assuming we won't have both UniNorth and Bandit */ 40 static int has_uninorth; 41 #ifdef CONFIG_PPC64 42 static struct pci_controller *u3_agp; 43 static struct pci_controller *u4_pcie; 44 static struct pci_controller *u3_ht; 45 #else 46 static int has_second_ohare; 47 #endif /* CONFIG_PPC64 */ 48 49 extern int pcibios_assign_bus_offset; 50 51 struct device_node *k2_skiplist[2]; 52 53 /* 54 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 55 */ 56 #define BANDIT_DEVID_2 8 57 #define BANDIT_REVID 3 58 59 #define BANDIT_DEVNUM 11 60 #define BANDIT_MAGIC 0x50 61 #define BANDIT_COHERENT 0x40 62 63 static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 64 { 65 for (; node != 0;node = node->sibling) { 66 const int * bus_range; 67 const unsigned int *class_code; 68 int len; 69 70 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 71 class_code = of_get_property(node, "class-code", NULL); 72 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 73 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 74 continue; 75 bus_range = of_get_property(node, "bus-range", &len); 76 if (bus_range != NULL && len > 2 * sizeof(int)) { 77 if (bus_range[1] > higher) 78 higher = bus_range[1]; 79 } 80 higher = fixup_one_level_bus_range(node->child, higher); 81 } 82 return higher; 83 } 84 85 /* This routine fixes the "bus-range" property of all bridges in the 86 * system since they tend to have their "last" member wrong on macs 87 * 88 * Note that the bus numbers manipulated here are OF bus numbers, they 89 * are not Linux bus numbers. 90 */ 91 static void __init fixup_bus_range(struct device_node *bridge) 92 { 93 int *bus_range, len; 94 struct property *prop; 95 96 /* Lookup the "bus-range" property for the hose */ 97 prop = of_find_property(bridge, "bus-range", &len); 98 if (prop == NULL || prop->length < 2 * sizeof(int)) 99 return; 100 101 bus_range = prop->value; 102 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 103 } 104 105 /* 106 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 107 * 108 * The "Bandit" version is present in all early PCI PowerMacs, 109 * and up to the first ones using Grackle. Some machines may 110 * have 2 bandit controllers (2 PCI busses). 111 * 112 * "Chaos" is used in some "Bandit"-type machines as a bridge 113 * for the separate display bus. It is accessed the same 114 * way as bandit, but cannot be probed for devices. It therefore 115 * has its own config access functions. 116 * 117 * The "UniNorth" version is present in all Core99 machines 118 * (iBook, G4, new IMacs, and all the recent Apple machines). 119 * It contains 3 controllers in one ASIC. 120 * 121 * The U3 is the bridge used on G5 machines. It contains an 122 * AGP bus which is dealt with the old UniNorth access routines 123 * and a HyperTransport bus which uses its own set of access 124 * functions. 125 */ 126 127 #define MACRISC_CFA0(devfn, off) \ 128 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ 129 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 130 | (((unsigned int)(off)) & 0xFCUL)) 131 132 #define MACRISC_CFA1(bus, devfn, off) \ 133 ((((unsigned int)(bus)) << 16) \ 134 |(((unsigned int)(devfn)) << 8) \ 135 |(((unsigned int)(off)) & 0xFCUL) \ 136 |1UL) 137 138 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, 139 u8 bus, u8 dev_fn, u8 offset) 140 { 141 unsigned int caddr; 142 143 if (bus == hose->first_busno) { 144 if (dev_fn < (11 << 3)) 145 return NULL; 146 caddr = MACRISC_CFA0(dev_fn, offset); 147 } else 148 caddr = MACRISC_CFA1(bus, dev_fn, offset); 149 150 /* Uninorth will return garbage if we don't read back the value ! */ 151 do { 152 out_le32(hose->cfg_addr, caddr); 153 } while (in_le32(hose->cfg_addr) != caddr); 154 155 offset &= has_uninorth ? 0x07 : 0x03; 156 return hose->cfg_data + offset; 157 } 158 159 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, 160 int offset, int len, u32 *val) 161 { 162 struct pci_controller *hose; 163 volatile void __iomem *addr; 164 165 hose = pci_bus_to_host(bus); 166 if (hose == NULL) 167 return PCIBIOS_DEVICE_NOT_FOUND; 168 if (offset >= 0x100) 169 return PCIBIOS_BAD_REGISTER_NUMBER; 170 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 171 if (!addr) 172 return PCIBIOS_DEVICE_NOT_FOUND; 173 /* 174 * Note: the caller has already checked that offset is 175 * suitably aligned and that len is 1, 2 or 4. 176 */ 177 switch (len) { 178 case 1: 179 *val = in_8(addr); 180 break; 181 case 2: 182 *val = in_le16(addr); 183 break; 184 default: 185 *val = in_le32(addr); 186 break; 187 } 188 return PCIBIOS_SUCCESSFUL; 189 } 190 191 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, 192 int offset, int len, u32 val) 193 { 194 struct pci_controller *hose; 195 volatile void __iomem *addr; 196 197 hose = pci_bus_to_host(bus); 198 if (hose == NULL) 199 return PCIBIOS_DEVICE_NOT_FOUND; 200 if (offset >= 0x100) 201 return PCIBIOS_BAD_REGISTER_NUMBER; 202 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 203 if (!addr) 204 return PCIBIOS_DEVICE_NOT_FOUND; 205 /* 206 * Note: the caller has already checked that offset is 207 * suitably aligned and that len is 1, 2 or 4. 208 */ 209 switch (len) { 210 case 1: 211 out_8(addr, val); 212 break; 213 case 2: 214 out_le16(addr, val); 215 break; 216 default: 217 out_le32(addr, val); 218 break; 219 } 220 return PCIBIOS_SUCCESSFUL; 221 } 222 223 static struct pci_ops macrisc_pci_ops = 224 { 225 .read = macrisc_read_config, 226 .write = macrisc_write_config, 227 }; 228 229 #ifdef CONFIG_PPC32 230 /* 231 * Verify that a specific (bus, dev_fn) exists on chaos 232 */ 233 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 234 { 235 struct device_node *np; 236 const u32 *vendor, *device; 237 238 if (offset >= 0x100) 239 return PCIBIOS_BAD_REGISTER_NUMBER; 240 np = pci_busdev_to_OF_node(bus, devfn); 241 if (np == NULL) 242 return PCIBIOS_DEVICE_NOT_FOUND; 243 244 vendor = of_get_property(np, "vendor-id", NULL); 245 device = of_get_property(np, "device-id", NULL); 246 if (vendor == NULL || device == NULL) 247 return PCIBIOS_DEVICE_NOT_FOUND; 248 249 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 250 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 251 return PCIBIOS_BAD_REGISTER_NUMBER; 252 253 return PCIBIOS_SUCCESSFUL; 254 } 255 256 static int 257 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 258 int len, u32 *val) 259 { 260 int result = chaos_validate_dev(bus, devfn, offset); 261 if (result == PCIBIOS_BAD_REGISTER_NUMBER) 262 *val = ~0U; 263 if (result != PCIBIOS_SUCCESSFUL) 264 return result; 265 return macrisc_read_config(bus, devfn, offset, len, val); 266 } 267 268 static int 269 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 270 int len, u32 val) 271 { 272 int result = chaos_validate_dev(bus, devfn, offset); 273 if (result != PCIBIOS_SUCCESSFUL) 274 return result; 275 return macrisc_write_config(bus, devfn, offset, len, val); 276 } 277 278 static struct pci_ops chaos_pci_ops = 279 { 280 .read = chaos_read_config, 281 .write = chaos_write_config, 282 }; 283 284 static void __init setup_chaos(struct pci_controller *hose, 285 struct resource *addr) 286 { 287 /* assume a `chaos' bridge */ 288 hose->ops = &chaos_pci_ops; 289 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 290 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 291 } 292 #endif /* CONFIG_PPC32 */ 293 294 #ifdef CONFIG_PPC64 295 /* 296 * These versions of U3 HyperTransport config space access ops do not 297 * implement self-view of the HT host yet 298 */ 299 300 /* 301 * This function deals with some "special cases" devices. 302 * 303 * 0 -> No special case 304 * 1 -> Skip the device but act as if the access was successfull 305 * (return 0xff's on reads, eventually, cache config space 306 * accesses in a later version) 307 * -1 -> Hide the device (unsuccessful acess) 308 */ 309 static int u3_ht_skip_device(struct pci_controller *hose, 310 struct pci_bus *bus, unsigned int devfn) 311 { 312 struct device_node *busdn, *dn; 313 int i; 314 315 /* We only allow config cycles to devices that are in OF device-tree 316 * as we are apparently having some weird things going on with some 317 * revs of K2 on recent G5s 318 */ 319 if (bus->self) 320 busdn = pci_device_to_OF_node(bus->self); 321 else 322 busdn = hose->arch_data; 323 for (dn = busdn->child; dn; dn = dn->sibling) 324 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) 325 break; 326 if (dn == NULL) 327 return -1; 328 329 /* 330 * When a device in K2 is powered down, we die on config 331 * cycle accesses. Fix that here. 332 */ 333 for (i=0; i<2; i++) 334 if (k2_skiplist[i] == dn) 335 return 1; 336 337 return 0; 338 } 339 340 #define U3_HT_CFA0(devfn, off) \ 341 ((((unsigned int)devfn) << 8) | offset) 342 #define U3_HT_CFA1(bus, devfn, off) \ 343 (U3_HT_CFA0(devfn, off) \ 344 + (((unsigned int)bus) << 16) \ 345 + 0x01000000UL) 346 347 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, 348 u8 bus, u8 devfn, u8 offset) 349 { 350 if (bus == hose->first_busno) { 351 /* For now, we don't self probe U3 HT bridge */ 352 if (PCI_SLOT(devfn) == 0) 353 return NULL; 354 return hose->cfg_data + U3_HT_CFA0(devfn, offset); 355 } else 356 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); 357 } 358 359 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 360 int offset, int len, u32 *val) 361 { 362 struct pci_controller *hose; 363 volatile void __iomem *addr; 364 365 hose = pci_bus_to_host(bus); 366 if (hose == NULL) 367 return PCIBIOS_DEVICE_NOT_FOUND; 368 if (offset >= 0x100) 369 return PCIBIOS_BAD_REGISTER_NUMBER; 370 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 371 if (!addr) 372 return PCIBIOS_DEVICE_NOT_FOUND; 373 374 switch (u3_ht_skip_device(hose, bus, devfn)) { 375 case 0: 376 break; 377 case 1: 378 switch (len) { 379 case 1: 380 *val = 0xff; break; 381 case 2: 382 *val = 0xffff; break; 383 default: 384 *val = 0xfffffffful; break; 385 } 386 return PCIBIOS_SUCCESSFUL; 387 default: 388 return PCIBIOS_DEVICE_NOT_FOUND; 389 } 390 391 /* 392 * Note: the caller has already checked that offset is 393 * suitably aligned and that len is 1, 2 or 4. 394 */ 395 switch (len) { 396 case 1: 397 *val = in_8(addr); 398 break; 399 case 2: 400 *val = in_le16(addr); 401 break; 402 default: 403 *val = in_le32(addr); 404 break; 405 } 406 return PCIBIOS_SUCCESSFUL; 407 } 408 409 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 410 int offset, int len, u32 val) 411 { 412 struct pci_controller *hose; 413 volatile void __iomem *addr; 414 415 hose = pci_bus_to_host(bus); 416 if (hose == NULL) 417 return PCIBIOS_DEVICE_NOT_FOUND; 418 if (offset >= 0x100) 419 return PCIBIOS_BAD_REGISTER_NUMBER; 420 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 421 if (!addr) 422 return PCIBIOS_DEVICE_NOT_FOUND; 423 424 switch (u3_ht_skip_device(hose, bus, devfn)) { 425 case 0: 426 break; 427 case 1: 428 return PCIBIOS_SUCCESSFUL; 429 default: 430 return PCIBIOS_DEVICE_NOT_FOUND; 431 } 432 433 /* 434 * Note: the caller has already checked that offset is 435 * suitably aligned and that len is 1, 2 or 4. 436 */ 437 switch (len) { 438 case 1: 439 out_8(addr, val); 440 break; 441 case 2: 442 out_le16(addr, val); 443 break; 444 default: 445 out_le32((u32 __iomem *)addr, val); 446 break; 447 } 448 return PCIBIOS_SUCCESSFUL; 449 } 450 451 static struct pci_ops u3_ht_pci_ops = 452 { 453 .read = u3_ht_read_config, 454 .write = u3_ht_write_config, 455 }; 456 457 #define U4_PCIE_CFA0(devfn, off) \ 458 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ 459 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 460 | ((((unsigned int)(off)) >> 8) << 28) \ 461 | (((unsigned int)(off)) & 0xfcU)) 462 463 #define U4_PCIE_CFA1(bus, devfn, off) \ 464 ((((unsigned int)(bus)) << 16) \ 465 |(((unsigned int)(devfn)) << 8) \ 466 | ((((unsigned int)(off)) >> 8) << 28) \ 467 |(((unsigned int)(off)) & 0xfcU) \ 468 |1UL) 469 470 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 471 u8 bus, u8 dev_fn, int offset) 472 { 473 unsigned int caddr; 474 475 if (bus == hose->first_busno) { 476 caddr = U4_PCIE_CFA0(dev_fn, offset); 477 } else 478 caddr = U4_PCIE_CFA1(bus, dev_fn, offset); 479 480 /* Uninorth will return garbage if we don't read back the value ! */ 481 do { 482 out_le32(hose->cfg_addr, caddr); 483 } while (in_le32(hose->cfg_addr) != caddr); 484 485 offset &= 0x03; 486 return hose->cfg_data + offset; 487 } 488 489 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 490 int offset, int len, u32 *val) 491 { 492 struct pci_controller *hose; 493 volatile void __iomem *addr; 494 495 hose = pci_bus_to_host(bus); 496 if (hose == NULL) 497 return PCIBIOS_DEVICE_NOT_FOUND; 498 if (offset >= 0x1000) 499 return PCIBIOS_BAD_REGISTER_NUMBER; 500 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 501 if (!addr) 502 return PCIBIOS_DEVICE_NOT_FOUND; 503 /* 504 * Note: the caller has already checked that offset is 505 * suitably aligned and that len is 1, 2 or 4. 506 */ 507 switch (len) { 508 case 1: 509 *val = in_8(addr); 510 break; 511 case 2: 512 *val = in_le16(addr); 513 break; 514 default: 515 *val = in_le32(addr); 516 break; 517 } 518 return PCIBIOS_SUCCESSFUL; 519 } 520 521 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 522 int offset, int len, u32 val) 523 { 524 struct pci_controller *hose; 525 volatile void __iomem *addr; 526 527 hose = pci_bus_to_host(bus); 528 if (hose == NULL) 529 return PCIBIOS_DEVICE_NOT_FOUND; 530 if (offset >= 0x1000) 531 return PCIBIOS_BAD_REGISTER_NUMBER; 532 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 533 if (!addr) 534 return PCIBIOS_DEVICE_NOT_FOUND; 535 /* 536 * Note: the caller has already checked that offset is 537 * suitably aligned and that len is 1, 2 or 4. 538 */ 539 switch (len) { 540 case 1: 541 out_8(addr, val); 542 break; 543 case 2: 544 out_le16(addr, val); 545 break; 546 default: 547 out_le32(addr, val); 548 break; 549 } 550 return PCIBIOS_SUCCESSFUL; 551 } 552 553 static struct pci_ops u4_pcie_pci_ops = 554 { 555 .read = u4_pcie_read_config, 556 .write = u4_pcie_write_config, 557 }; 558 559 #endif /* CONFIG_PPC64 */ 560 561 #ifdef CONFIG_PPC32 562 /* 563 * For a bandit bridge, turn on cache coherency if necessary. 564 * N.B. we could clean this up using the hose ops directly. 565 */ 566 static void __init init_bandit(struct pci_controller *bp) 567 { 568 unsigned int vendev, magic; 569 int rev; 570 571 /* read the word at offset 0 in config space for device 11 */ 572 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 573 udelay(2); 574 vendev = in_le32(bp->cfg_data); 575 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 576 PCI_VENDOR_ID_APPLE) { 577 /* read the revision id */ 578 out_le32(bp->cfg_addr, 579 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 580 udelay(2); 581 rev = in_8(bp->cfg_data); 582 if (rev != BANDIT_REVID) 583 printk(KERN_WARNING 584 "Unknown revision %d for bandit\n", rev); 585 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 586 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 587 return; 588 } 589 590 /* read the word at offset 0x50 */ 591 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 592 udelay(2); 593 magic = in_le32(bp->cfg_data); 594 if ((magic & BANDIT_COHERENT) != 0) 595 return; 596 magic |= BANDIT_COHERENT; 597 udelay(2); 598 out_le32(bp->cfg_data, magic); 599 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 600 } 601 602 /* 603 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 604 */ 605 static void __init init_p2pbridge(void) 606 { 607 struct device_node *p2pbridge; 608 struct pci_controller* hose; 609 u8 bus, devfn; 610 u16 val; 611 612 /* XXX it would be better here to identify the specific 613 PCI-PCI bridge chip we have. */ 614 p2pbridge = of_find_node_by_name(NULL, "pci-bridge"); 615 if (p2pbridge == NULL 616 || p2pbridge->parent == NULL 617 || strcmp(p2pbridge->parent->name, "pci") != 0) 618 goto done; 619 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 620 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 621 goto done; 622 } 623 /* Warning: At this point, we have not yet renumbered all busses. 624 * So we must use OF walking to find out hose 625 */ 626 hose = pci_find_hose_for_OF_device(p2pbridge); 627 if (!hose) { 628 DBG("Can't find hose for PCI<->PCI bridge\n"); 629 goto done; 630 } 631 if (early_read_config_word(hose, bus, devfn, 632 PCI_BRIDGE_CONTROL, &val) < 0) { 633 printk(KERN_ERR "init_p2pbridge: couldn't read bridge" 634 " control\n"); 635 goto done; 636 } 637 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 638 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 639 done: 640 of_node_put(p2pbridge); 641 } 642 643 static void __init init_second_ohare(void) 644 { 645 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); 646 unsigned char bus, devfn; 647 unsigned short cmd; 648 649 if (np == NULL) 650 return; 651 652 /* This must run before we initialize the PICs since the second 653 * ohare hosts a PIC that will be accessed there. 654 */ 655 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { 656 struct pci_controller* hose = 657 pci_find_hose_for_OF_device(np); 658 if (!hose) { 659 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); 660 return; 661 } 662 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); 663 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 664 cmd &= ~PCI_COMMAND_IO; 665 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); 666 } 667 has_second_ohare = 1; 668 } 669 670 /* 671 * Some Apple desktop machines have a NEC PD720100A USB2 controller 672 * on the motherboard. Open Firmware, on these, will disable the 673 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 674 * code re-enables it ;) 675 */ 676 static void __init fixup_nec_usb2(void) 677 { 678 struct device_node *nec; 679 680 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { 681 struct pci_controller *hose; 682 u32 data; 683 const u32 *prop; 684 u8 bus, devfn; 685 686 prop = of_get_property(nec, "vendor-id", NULL); 687 if (prop == NULL) 688 continue; 689 if (0x1033 != *prop) 690 continue; 691 prop = of_get_property(nec, "device-id", NULL); 692 if (prop == NULL) 693 continue; 694 if (0x0035 != *prop) 695 continue; 696 prop = of_get_property(nec, "reg", NULL); 697 if (prop == NULL) 698 continue; 699 devfn = (prop[0] >> 8) & 0xff; 700 bus = (prop[0] >> 16) & 0xff; 701 if (PCI_FUNC(devfn) != 0) 702 continue; 703 hose = pci_find_hose_for_OF_device(nec); 704 if (!hose) 705 continue; 706 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 707 if (data & 1UL) { 708 printk("Found NEC PD720100A USB2 chip with disabled" 709 " EHCI, fixing up...\n"); 710 data &= ~1UL; 711 early_write_config_dword(hose, bus, devfn, 0xe4, data); 712 } 713 } 714 } 715 716 static void __init setup_bandit(struct pci_controller *hose, 717 struct resource *addr) 718 { 719 hose->ops = ¯isc_pci_ops; 720 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 721 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 722 init_bandit(hose); 723 } 724 725 static int __init setup_uninorth(struct pci_controller *hose, 726 struct resource *addr) 727 { 728 pci_assign_all_buses = 1; 729 has_uninorth = 1; 730 hose->ops = ¯isc_pci_ops; 731 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 732 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 733 /* We "know" that the bridge at f2000000 has the PCI slots. */ 734 return addr->start == 0xf2000000; 735 } 736 #endif /* CONFIG_PPC32 */ 737 738 #ifdef CONFIG_PPC64 739 static void __init setup_u3_agp(struct pci_controller* hose) 740 { 741 /* On G5, we move AGP up to high bus number so we don't need 742 * to reassign bus numbers for HT. If we ever have P2P bridges 743 * on AGP, we'll have to move pci_assign_all_busses to the 744 * pci_controller structure so we enable it for AGP and not for 745 * HT childs. 746 * We hard code the address because of the different size of 747 * the reg address cell, we shall fix that by killing struct 748 * reg_property and using some accessor functions instead 749 */ 750 hose->first_busno = 0xf0; 751 hose->last_busno = 0xff; 752 has_uninorth = 1; 753 hose->ops = ¯isc_pci_ops; 754 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 755 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 756 u3_agp = hose; 757 } 758 759 static void __init setup_u4_pcie(struct pci_controller* hose) 760 { 761 /* We currently only implement the "non-atomic" config space, to 762 * be optimised later. 763 */ 764 hose->ops = &u4_pcie_pci_ops; 765 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 766 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 767 768 /* The bus contains a bridge from root -> device, we need to 769 * make it visible on bus 0 so that we pick the right type 770 * of config cycles. If we didn't, we would have to force all 771 * config cycles to be type 1. So we override the "bus-range" 772 * property here 773 */ 774 hose->first_busno = 0x00; 775 hose->last_busno = 0xff; 776 u4_pcie = hose; 777 } 778 779 static void __init setup_u3_ht(struct pci_controller* hose) 780 { 781 struct device_node *np = (struct device_node *)hose->arch_data; 782 struct pci_controller *other = NULL; 783 int i, cur; 784 785 786 hose->ops = &u3_ht_pci_ops; 787 788 /* We hard code the address because of the different size of 789 * the reg address cell, we shall fix that by killing struct 790 * reg_property and using some accessor functions instead 791 */ 792 hose->cfg_data = ioremap(0xf2000000, 0x02000000); 793 794 /* 795 * /ht node doesn't expose a "ranges" property, so we "remove" 796 * regions that have been allocated to AGP. So far, this version of 797 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions 798 * to /ht. We need to fix that sooner or later by either parsing all 799 * child "ranges" properties or figuring out the U3 address space 800 * decoding logic and then read its configuration register (if any). 801 */ 802 hose->io_base_phys = 0xf4000000; 803 hose->pci_io_size = 0x00400000; 804 hose->io_resource.name = np->full_name; 805 hose->io_resource.start = 0; 806 hose->io_resource.end = 0x003fffff; 807 hose->io_resource.flags = IORESOURCE_IO; 808 hose->pci_mem_offset = 0; 809 hose->first_busno = 0; 810 hose->last_busno = 0xef; 811 hose->mem_resources[0].name = np->full_name; 812 hose->mem_resources[0].start = 0x80000000; 813 hose->mem_resources[0].end = 0xefffffff; 814 hose->mem_resources[0].flags = IORESOURCE_MEM; 815 816 u3_ht = hose; 817 818 if (u3_agp != NULL) 819 other = u3_agp; 820 else if (u4_pcie != NULL) 821 other = u4_pcie; 822 823 if (other == NULL) { 824 DBG("U3/4 has no AGP/PCIE, using full resource range\n"); 825 return; 826 } 827 828 /* Fixup bus range vs. PCIE */ 829 if (u4_pcie) 830 hose->last_busno = u4_pcie->first_busno - 1; 831 832 /* We "remove" the AGP resources from the resources allocated to HT, 833 * that is we create "holes". However, that code does assumptions 834 * that so far happen to be true (cross fingers...), typically that 835 * resources in the AGP node are properly ordered 836 */ 837 cur = 0; 838 for (i=0; i<3; i++) { 839 struct resource *res = &other->mem_resources[i]; 840 if (res->flags != IORESOURCE_MEM) 841 continue; 842 /* We don't care about "fine" resources */ 843 if (res->start >= 0xf0000000) 844 continue; 845 /* Check if it's just a matter of "shrinking" us in one 846 * direction 847 */ 848 if (hose->mem_resources[cur].start == res->start) { 849 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", 850 cur, hose->mem_resources[cur].start, 851 res->end + 1); 852 hose->mem_resources[cur].start = res->end + 1; 853 continue; 854 } 855 if (hose->mem_resources[cur].end == res->end) { 856 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", 857 cur, hose->mem_resources[cur].end, 858 res->start - 1); 859 hose->mem_resources[cur].end = res->start - 1; 860 continue; 861 } 862 /* No, it's not the case, we need a hole */ 863 if (cur == 2) { 864 /* not enough resources for a hole, we drop part 865 * of the range 866 */ 867 printk(KERN_WARNING "Running out of resources" 868 " for /ht host !\n"); 869 hose->mem_resources[cur].end = res->start - 1; 870 continue; 871 } 872 cur++; 873 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", 874 cur-1, res->start - 1, cur, res->end + 1); 875 hose->mem_resources[cur].name = np->full_name; 876 hose->mem_resources[cur].flags = IORESOURCE_MEM; 877 hose->mem_resources[cur].start = res->end + 1; 878 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; 879 hose->mem_resources[cur-1].end = res->start - 1; 880 } 881 } 882 #endif /* CONFIG_PPC64 */ 883 884 /* 885 * We assume that if we have a G3 powermac, we have one bridge called 886 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 887 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 888 */ 889 static int __init pmac_add_bridge(struct device_node *dev) 890 { 891 int len; 892 struct pci_controller *hose; 893 struct resource rsrc; 894 char *disp_name; 895 const int *bus_range; 896 int primary = 1, has_address = 0; 897 898 DBG("Adding PCI host bridge %s\n", dev->full_name); 899 900 /* Fetch host bridge registers address */ 901 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 902 903 /* Get bus range if any */ 904 bus_range = of_get_property(dev, "bus-range", &len); 905 if (bus_range == NULL || len < 2 * sizeof(int)) { 906 printk(KERN_WARNING "Can't get bus-range for %s, assume" 907 " bus 0\n", dev->full_name); 908 } 909 910 hose = pcibios_alloc_controller(dev); 911 if (!hose) 912 return -ENOMEM; 913 hose->first_busno = bus_range ? bus_range[0] : 0; 914 hose->last_busno = bus_range ? bus_range[1] : 0xff; 915 916 disp_name = NULL; 917 918 /* 64 bits only bridges */ 919 #ifdef CONFIG_PPC64 920 if (of_device_is_compatible(dev, "u3-agp")) { 921 setup_u3_agp(hose); 922 disp_name = "U3-AGP"; 923 primary = 0; 924 } else if (of_device_is_compatible(dev, "u3-ht")) { 925 setup_u3_ht(hose); 926 disp_name = "U3-HT"; 927 primary = 1; 928 } else if (of_device_is_compatible(dev, "u4-pcie")) { 929 setup_u4_pcie(hose); 930 disp_name = "U4-PCIE"; 931 primary = 0; 932 } 933 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" 934 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); 935 #endif /* CONFIG_PPC64 */ 936 937 /* 32 bits only bridges */ 938 #ifdef CONFIG_PPC32 939 if (of_device_is_compatible(dev, "uni-north")) { 940 primary = setup_uninorth(hose, &rsrc); 941 disp_name = "UniNorth"; 942 } else if (strcmp(dev->name, "pci") == 0) { 943 /* XXX assume this is a mpc106 (grackle) */ 944 setup_grackle(hose); 945 disp_name = "Grackle (MPC106)"; 946 } else if (strcmp(dev->name, "bandit") == 0) { 947 setup_bandit(hose, &rsrc); 948 disp_name = "Bandit"; 949 } else if (strcmp(dev->name, "chaos") == 0) { 950 setup_chaos(hose, &rsrc); 951 disp_name = "Chaos"; 952 primary = 0; 953 } 954 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " 955 "Firmware bus number: %d->%d\n", 956 disp_name, (unsigned long long)rsrc.start, hose->first_busno, 957 hose->last_busno); 958 #endif /* CONFIG_PPC32 */ 959 960 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 961 hose, hose->cfg_addr, hose->cfg_data); 962 963 /* Interpret the "ranges" property */ 964 /* This also maps the I/O region and sets isa_io/mem_base */ 965 pci_process_bridge_OF_ranges(hose, dev, primary); 966 967 /* Fixup "bus-range" OF property */ 968 fixup_bus_range(dev); 969 970 return 0; 971 } 972 973 void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) 974 { 975 #ifdef CONFIG_PPC32 976 /* Fixup interrupt for the modem/ethernet combo controller. 977 * on machines with a second ohare chip. 978 * The number in the device tree (27) is bogus (correct for 979 * the ethernet-only board but not the combo ethernet/modem 980 * board). The real interrupt is 28 on the second controller 981 * -> 28+32 = 60. 982 */ 983 if (has_second_ohare && 984 dev->vendor == PCI_VENDOR_ID_DEC && 985 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { 986 dev->irq = irq_create_mapping(NULL, 60); 987 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); 988 } 989 #endif /* CONFIG_PPC32 */ 990 } 991 992 void __init pmac_pci_init(void) 993 { 994 struct device_node *np, *root; 995 struct device_node *ht = NULL; 996 997 root = of_find_node_by_path("/"); 998 if (root == NULL) { 999 printk(KERN_CRIT "pmac_pci_init: can't find root " 1000 "of device tree\n"); 1001 return; 1002 } 1003 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 1004 if (np->name == NULL) 1005 continue; 1006 if (strcmp(np->name, "bandit") == 0 1007 || strcmp(np->name, "chaos") == 0 1008 || strcmp(np->name, "pci") == 0) { 1009 if (pmac_add_bridge(np) == 0) 1010 of_node_get(np); 1011 } 1012 if (strcmp(np->name, "ht") == 0) { 1013 of_node_get(np); 1014 ht = np; 1015 } 1016 } 1017 of_node_put(root); 1018 1019 #ifdef CONFIG_PPC64 1020 /* Probe HT last as it relies on the agp resources to be already 1021 * setup 1022 */ 1023 if (ht && pmac_add_bridge(ht) != 0) 1024 of_node_put(ht); 1025 1026 /* Setup the linkage between OF nodes and PHBs */ 1027 pci_devs_phb_init(); 1028 1029 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 1030 * assume there is no P2P bridge on the AGP bus, which should be a 1031 * safe assumptions for now. We should do something better in the 1032 * future though 1033 */ 1034 if (u3_agp) { 1035 struct device_node *np = u3_agp->arch_data; 1036 PCI_DN(np)->busno = 0xf0; 1037 for (np = np->child; np; np = np->sibling) 1038 PCI_DN(np)->busno = 0xf0; 1039 } 1040 /* pmac_check_ht_link(); */ 1041 1042 /* Tell pci.c to not use the common resource allocation mechanism */ 1043 pci_probe_only = 1; 1044 1045 #else /* CONFIG_PPC64 */ 1046 init_p2pbridge(); 1047 init_second_ohare(); 1048 fixup_nec_usb2(); 1049 1050 /* We are still having some issues with the Xserve G4, enabling 1051 * some offset between bus number and domains for now when we 1052 * assign all busses should help for now 1053 */ 1054 if (pci_assign_all_buses) 1055 pcibios_assign_bus_offset = 0x10; 1056 #endif 1057 } 1058 1059 int 1060 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) 1061 { 1062 struct device_node* node; 1063 int updatecfg = 0; 1064 int uninorth_child; 1065 1066 node = pci_device_to_OF_node(dev); 1067 1068 /* We don't want to enable USB controllers absent from the OF tree 1069 * (iBook second controller) 1070 */ 1071 if (dev->vendor == PCI_VENDOR_ID_APPLE 1072 && dev->class == PCI_CLASS_SERIAL_USB_OHCI 1073 && !node) { 1074 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 1075 pci_name(dev)); 1076 return -EINVAL; 1077 } 1078 1079 if (!node) 1080 return 0; 1081 1082 uninorth_child = node->parent && 1083 of_device_is_compatible(node->parent, "uni-north"); 1084 1085 /* Firewire & GMAC were disabled after PCI probe, the driver is 1086 * claiming them, we must re-enable them now. 1087 */ 1088 if (uninorth_child && !strcmp(node->name, "firewire") && 1089 (of_device_is_compatible(node, "pci106b,18") || 1090 of_device_is_compatible(node, "pci106b,30") || 1091 of_device_is_compatible(node, "pci11c1,5811"))) { 1092 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 1093 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 1094 updatecfg = 1; 1095 } 1096 if (uninorth_child && !strcmp(node->name, "ethernet") && 1097 of_device_is_compatible(node, "gmac")) { 1098 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 1099 updatecfg = 1; 1100 } 1101 1102 if (updatecfg) { 1103 u16 cmd; 1104 1105 /* 1106 * Make sure PCI is correctly configured 1107 * 1108 * We use old pci_bios versions of the function since, by 1109 * default, gmac is not powered up, and so will be absent 1110 * from the kernel initial PCI lookup. 1111 * 1112 * Should be replaced by 2.4 new PCI mechanisms and really 1113 * register the device. 1114 */ 1115 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1116 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 1117 | PCI_COMMAND_INVALIDATE; 1118 pci_write_config_word(dev, PCI_COMMAND, cmd); 1119 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1120 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1121 L1_CACHE_BYTES >> 2); 1122 } 1123 1124 return 0; 1125 } 1126 1127 /* We power down some devices after they have been probed. They'll 1128 * be powered back on later on 1129 */ 1130 void __init pmac_pcibios_after_init(void) 1131 { 1132 struct device_node* nd; 1133 1134 #ifdef CONFIG_BLK_DEV_IDE 1135 struct pci_dev *dev = NULL; 1136 1137 /* OF fails to initialize IDE controllers on macs 1138 * (and maybe other machines) 1139 * 1140 * Ideally, this should be moved to the IDE layer, but we need 1141 * to check specifically with Andre Hedrick how to do it cleanly 1142 * since the common IDE code seem to care about the fact that the 1143 * BIOS may have disabled a controller. 1144 * 1145 * -- BenH 1146 */ 1147 for_each_pci_dev(dev) { 1148 if ((dev->class >> 16) != PCI_BASE_CLASS_STORAGE) 1149 continue; 1150 if (pci_enable_device(dev)) 1151 printk(KERN_WARNING 1152 "pci: Failed to enable %s\n", pci_name(dev)); 1153 } 1154 #endif /* CONFIG_BLK_DEV_IDE */ 1155 1156 for_each_node_by_name(nd, "firewire") { 1157 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") || 1158 of_device_is_compatible(nd, "pci106b,30") || 1159 of_device_is_compatible(nd, "pci11c1,5811")) 1160 && of_device_is_compatible(nd->parent, "uni-north")) { 1161 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1162 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1163 } 1164 } 1165 of_node_put(nd); 1166 for_each_node_by_name(nd, "ethernet") { 1167 if (nd->parent && of_device_is_compatible(nd, "gmac") 1168 && of_device_is_compatible(nd->parent, "uni-north")) 1169 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1170 } 1171 of_node_put(nd); 1172 } 1173 1174 #ifdef CONFIG_PPC32 1175 void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1176 { 1177 if (!machine_is(powermac)) 1178 return; 1179 /* 1180 * Fix the interrupt routing on the various cardbus bridges 1181 * used on powerbooks 1182 */ 1183 if (dev->vendor != PCI_VENDOR_ID_TI) 1184 return; 1185 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1186 dev->device == PCI_DEVICE_ID_TI_1131) { 1187 u8 val; 1188 /* Enable PCI interrupt */ 1189 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1190 pci_write_config_byte(dev, 0x91, val | 0x30); 1191 /* Disable ISA interrupt mode */ 1192 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1193 pci_write_config_byte(dev, 0x92, val & ~0x06); 1194 } 1195 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1196 dev->device == PCI_DEVICE_ID_TI_1211 || 1197 dev->device == PCI_DEVICE_ID_TI_1410 || 1198 dev->device == PCI_DEVICE_ID_TI_1510) { 1199 u8 val; 1200 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1201 signal out the MFUNC0 pin */ 1202 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1203 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1204 /* Disable ISA interrupt mode */ 1205 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1206 pci_write_config_byte(dev, 0x92, val & ~0x06); 1207 } 1208 } 1209 1210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1211 1212 void pmac_pci_fixup_pciata(struct pci_dev* dev) 1213 { 1214 u8 progif = 0; 1215 1216 /* 1217 * On PowerMacs, we try to switch any PCI ATA controller to 1218 * fully native mode 1219 */ 1220 if (!machine_is(powermac)) 1221 return; 1222 1223 /* Some controllers don't have the class IDE */ 1224 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1225 switch(dev->device) { 1226 case PCI_DEVICE_ID_PROMISE_20246: 1227 case PCI_DEVICE_ID_PROMISE_20262: 1228 case PCI_DEVICE_ID_PROMISE_20263: 1229 case PCI_DEVICE_ID_PROMISE_20265: 1230 case PCI_DEVICE_ID_PROMISE_20267: 1231 case PCI_DEVICE_ID_PROMISE_20268: 1232 case PCI_DEVICE_ID_PROMISE_20269: 1233 case PCI_DEVICE_ID_PROMISE_20270: 1234 case PCI_DEVICE_ID_PROMISE_20271: 1235 case PCI_DEVICE_ID_PROMISE_20275: 1236 case PCI_DEVICE_ID_PROMISE_20276: 1237 case PCI_DEVICE_ID_PROMISE_20277: 1238 goto good; 1239 } 1240 /* Others, check PCI class */ 1241 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1242 return; 1243 good: 1244 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1245 if ((progif & 5) != 5) { 1246 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", 1247 pci_name(dev)); 1248 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1249 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1250 (progif & 5) != 5) 1251 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1252 } 1253 } 1254 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1255 #endif 1256 1257 /* 1258 * Disable second function on K2-SATA, it's broken 1259 * and disable IO BARs on first one 1260 */ 1261 static void fixup_k2_sata(struct pci_dev* dev) 1262 { 1263 int i; 1264 u16 cmd; 1265 1266 if (PCI_FUNC(dev->devfn) > 0) { 1267 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1268 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1269 pci_write_config_word(dev, PCI_COMMAND, cmd); 1270 for (i = 0; i < 6; i++) { 1271 dev->resource[i].start = dev->resource[i].end = 0; 1272 dev->resource[i].flags = 0; 1273 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1274 0); 1275 } 1276 } else { 1277 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1278 cmd &= ~PCI_COMMAND_IO; 1279 pci_write_config_word(dev, PCI_COMMAND, cmd); 1280 for (i = 0; i < 5; i++) { 1281 dev->resource[i].start = dev->resource[i].end = 0; 1282 dev->resource[i].flags = 0; 1283 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1284 0); 1285 } 1286 } 1287 } 1288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1289 1290