1 /* 2 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au) 3 * Ben. Herrenschmidt (benh@kernel.crashing.org) 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * TODO: 11 * 12 * - Replace mdelay with some schedule loop if possible 13 * - Shorten some obfuscated delays on some routines (like modem 14 * power) 15 * - Refcount some clocks (see darwin) 16 * - Split split split... 17 * 18 */ 19 #include <linux/types.h> 20 #include <linux/init.h> 21 #include <linux/delay.h> 22 #include <linux/kernel.h> 23 #include <linux/sched.h> 24 #include <linux/spinlock.h> 25 #include <linux/adb.h> 26 #include <linux/pmu.h> 27 #include <linux/ioport.h> 28 #include <linux/pci.h> 29 #include <asm/sections.h> 30 #include <asm/errno.h> 31 #include <asm/ohare.h> 32 #include <asm/heathrow.h> 33 #include <asm/keylargo.h> 34 #include <asm/uninorth.h> 35 #include <asm/io.h> 36 #include <asm/prom.h> 37 #include <asm/machdep.h> 38 #include <asm/pmac_feature.h> 39 #include <asm/dbdma.h> 40 #include <asm/pci-bridge.h> 41 #include <asm/pmac_low_i2c.h> 42 43 #undef DEBUG_FEATURE 44 45 #ifdef DEBUG_FEATURE 46 #define DBG(fmt...) printk(KERN_DEBUG fmt) 47 #else 48 #define DBG(fmt...) 49 #endif 50 51 #ifdef CONFIG_6xx 52 extern int powersave_lowspeed; 53 #endif 54 55 extern int powersave_nap; 56 extern struct device_node *k2_skiplist[2]; 57 58 /* 59 * We use a single global lock to protect accesses. Each driver has 60 * to take care of its own locking 61 */ 62 DEFINE_SPINLOCK(feature_lock); 63 64 #define LOCK(flags) spin_lock_irqsave(&feature_lock, flags); 65 #define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags); 66 67 68 /* 69 * Instance of some macio stuffs 70 */ 71 struct macio_chip macio_chips[MAX_MACIO_CHIPS]; 72 73 struct macio_chip *macio_find(struct device_node *child, int type) 74 { 75 while(child) { 76 int i; 77 78 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++) 79 if (child == macio_chips[i].of_node && 80 (!type || macio_chips[i].type == type)) 81 return &macio_chips[i]; 82 child = child->parent; 83 } 84 return NULL; 85 } 86 EXPORT_SYMBOL_GPL(macio_find); 87 88 static const char *macio_names[] = 89 { 90 "Unknown", 91 "Grand Central", 92 "OHare", 93 "OHareII", 94 "Heathrow", 95 "Gatwick", 96 "Paddington", 97 "Keylargo", 98 "Pangea", 99 "Intrepid", 100 "K2", 101 "Shasta", 102 }; 103 104 105 struct device_node *uninorth_node; 106 u32 __iomem *uninorth_base; 107 108 static u32 uninorth_rev; 109 static int uninorth_maj; 110 static void __iomem *u3_ht_base; 111 112 /* 113 * For each motherboard family, we have a table of functions pointers 114 * that handle the various features. 115 */ 116 117 typedef long (*feature_call)(struct device_node *node, long param, long value); 118 119 struct feature_table_entry { 120 unsigned int selector; 121 feature_call function; 122 }; 123 124 struct pmac_mb_def 125 { 126 const char* model_string; 127 const char* model_name; 128 int model_id; 129 struct feature_table_entry* features; 130 unsigned long board_flags; 131 }; 132 static struct pmac_mb_def pmac_mb; 133 134 /* 135 * Here are the chip specific feature functions 136 */ 137 138 static inline int simple_feature_tweak(struct device_node *node, int type, 139 int reg, u32 mask, int value) 140 { 141 struct macio_chip* macio; 142 unsigned long flags; 143 144 macio = macio_find(node, type); 145 if (!macio) 146 return -ENODEV; 147 LOCK(flags); 148 if (value) 149 MACIO_BIS(reg, mask); 150 else 151 MACIO_BIC(reg, mask); 152 (void)MACIO_IN32(reg); 153 UNLOCK(flags); 154 155 return 0; 156 } 157 158 #ifndef CONFIG_POWER4 159 160 static long ohare_htw_scc_enable(struct device_node *node, long param, 161 long value) 162 { 163 struct macio_chip* macio; 164 unsigned long chan_mask; 165 unsigned long fcr; 166 unsigned long flags; 167 int htw, trans; 168 unsigned long rmask; 169 170 macio = macio_find(node, 0); 171 if (!macio) 172 return -ENODEV; 173 if (!strcmp(node->name, "ch-a")) 174 chan_mask = MACIO_FLAG_SCCA_ON; 175 else if (!strcmp(node->name, "ch-b")) 176 chan_mask = MACIO_FLAG_SCCB_ON; 177 else 178 return -ENODEV; 179 180 htw = (macio->type == macio_heathrow || macio->type == macio_paddington 181 || macio->type == macio_gatwick); 182 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */ 183 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && 184 pmac_mb.model_id != PMAC_TYPE_YIKES); 185 if (value) { 186 #ifdef CONFIG_ADB_PMU 187 if ((param & 0xfff) == PMAC_SCC_IRDA) 188 pmu_enable_irled(1); 189 #endif /* CONFIG_ADB_PMU */ 190 LOCK(flags); 191 fcr = MACIO_IN32(OHARE_FCR); 192 /* Check if scc cell need enabling */ 193 if (!(fcr & OH_SCC_ENABLE)) { 194 fcr |= OH_SCC_ENABLE; 195 if (htw) { 196 /* Side effect: this will also power up the 197 * modem, but it's too messy to figure out on which 198 * ports this controls the tranceiver and on which 199 * it controls the modem 200 */ 201 if (trans) 202 fcr &= ~HRW_SCC_TRANS_EN_N; 203 MACIO_OUT32(OHARE_FCR, fcr); 204 fcr |= (rmask = HRW_RESET_SCC); 205 MACIO_OUT32(OHARE_FCR, fcr); 206 } else { 207 fcr |= (rmask = OH_SCC_RESET); 208 MACIO_OUT32(OHARE_FCR, fcr); 209 } 210 UNLOCK(flags); 211 (void)MACIO_IN32(OHARE_FCR); 212 mdelay(15); 213 LOCK(flags); 214 fcr &= ~rmask; 215 MACIO_OUT32(OHARE_FCR, fcr); 216 } 217 if (chan_mask & MACIO_FLAG_SCCA_ON) 218 fcr |= OH_SCCA_IO; 219 if (chan_mask & MACIO_FLAG_SCCB_ON) 220 fcr |= OH_SCCB_IO; 221 MACIO_OUT32(OHARE_FCR, fcr); 222 macio->flags |= chan_mask; 223 UNLOCK(flags); 224 if (param & PMAC_SCC_FLAG_XMON) 225 macio->flags |= MACIO_FLAG_SCC_LOCKED; 226 } else { 227 if (macio->flags & MACIO_FLAG_SCC_LOCKED) 228 return -EPERM; 229 LOCK(flags); 230 fcr = MACIO_IN32(OHARE_FCR); 231 if (chan_mask & MACIO_FLAG_SCCA_ON) 232 fcr &= ~OH_SCCA_IO; 233 if (chan_mask & MACIO_FLAG_SCCB_ON) 234 fcr &= ~OH_SCCB_IO; 235 MACIO_OUT32(OHARE_FCR, fcr); 236 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) { 237 fcr &= ~OH_SCC_ENABLE; 238 if (htw && trans) 239 fcr |= HRW_SCC_TRANS_EN_N; 240 MACIO_OUT32(OHARE_FCR, fcr); 241 } 242 macio->flags &= ~(chan_mask); 243 UNLOCK(flags); 244 mdelay(10); 245 #ifdef CONFIG_ADB_PMU 246 if ((param & 0xfff) == PMAC_SCC_IRDA) 247 pmu_enable_irled(0); 248 #endif /* CONFIG_ADB_PMU */ 249 } 250 return 0; 251 } 252 253 static long ohare_floppy_enable(struct device_node *node, long param, 254 long value) 255 { 256 return simple_feature_tweak(node, macio_ohare, 257 OHARE_FCR, OH_FLOPPY_ENABLE, value); 258 } 259 260 static long ohare_mesh_enable(struct device_node *node, long param, long value) 261 { 262 return simple_feature_tweak(node, macio_ohare, 263 OHARE_FCR, OH_MESH_ENABLE, value); 264 } 265 266 static long ohare_ide_enable(struct device_node *node, long param, long value) 267 { 268 switch(param) { 269 case 0: 270 /* For some reason, setting the bit in set_initial_features() 271 * doesn't stick. I'm still investigating... --BenH. 272 */ 273 if (value) 274 simple_feature_tweak(node, macio_ohare, 275 OHARE_FCR, OH_IOBUS_ENABLE, 1); 276 return simple_feature_tweak(node, macio_ohare, 277 OHARE_FCR, OH_IDE0_ENABLE, value); 278 case 1: 279 return simple_feature_tweak(node, macio_ohare, 280 OHARE_FCR, OH_BAY_IDE_ENABLE, value); 281 default: 282 return -ENODEV; 283 } 284 } 285 286 static long ohare_ide_reset(struct device_node *node, long param, long value) 287 { 288 switch(param) { 289 case 0: 290 return simple_feature_tweak(node, macio_ohare, 291 OHARE_FCR, OH_IDE0_RESET_N, !value); 292 case 1: 293 return simple_feature_tweak(node, macio_ohare, 294 OHARE_FCR, OH_IDE1_RESET_N, !value); 295 default: 296 return -ENODEV; 297 } 298 } 299 300 static long ohare_sleep_state(struct device_node *node, long param, long value) 301 { 302 struct macio_chip* macio = &macio_chips[0]; 303 304 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 305 return -EPERM; 306 if (value == 1) { 307 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE); 308 } else if (value == 0) { 309 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 310 } 311 312 return 0; 313 } 314 315 static long heathrow_modem_enable(struct device_node *node, long param, 316 long value) 317 { 318 struct macio_chip* macio; 319 u8 gpio; 320 unsigned long flags; 321 322 macio = macio_find(node, macio_unknown); 323 if (!macio) 324 return -ENODEV; 325 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1; 326 if (!value) { 327 LOCK(flags); 328 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); 329 UNLOCK(flags); 330 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 331 mdelay(250); 332 } 333 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && 334 pmac_mb.model_id != PMAC_TYPE_YIKES) { 335 LOCK(flags); 336 if (value) 337 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 338 else 339 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 340 UNLOCK(flags); 341 (void)MACIO_IN32(HEATHROW_FCR); 342 mdelay(250); 343 } 344 if (value) { 345 LOCK(flags); 346 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); 347 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 348 UNLOCK(flags); mdelay(250); LOCK(flags); 349 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); 350 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 351 UNLOCK(flags); mdelay(250); LOCK(flags); 352 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); 353 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 354 UNLOCK(flags); mdelay(250); 355 } 356 return 0; 357 } 358 359 static long heathrow_floppy_enable(struct device_node *node, long param, 360 long value) 361 { 362 return simple_feature_tweak(node, macio_unknown, 363 HEATHROW_FCR, 364 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE, 365 value); 366 } 367 368 static long heathrow_mesh_enable(struct device_node *node, long param, 369 long value) 370 { 371 struct macio_chip* macio; 372 unsigned long flags; 373 374 macio = macio_find(node, macio_unknown); 375 if (!macio) 376 return -ENODEV; 377 LOCK(flags); 378 /* Set clear mesh cell enable */ 379 if (value) 380 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE); 381 else 382 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE); 383 (void)MACIO_IN32(HEATHROW_FCR); 384 udelay(10); 385 /* Set/Clear termination power */ 386 if (value) 387 MACIO_BIC(HEATHROW_MBCR, 0x04000000); 388 else 389 MACIO_BIS(HEATHROW_MBCR, 0x04000000); 390 (void)MACIO_IN32(HEATHROW_MBCR); 391 udelay(10); 392 UNLOCK(flags); 393 394 return 0; 395 } 396 397 static long heathrow_ide_enable(struct device_node *node, long param, 398 long value) 399 { 400 switch(param) { 401 case 0: 402 return simple_feature_tweak(node, macio_unknown, 403 HEATHROW_FCR, HRW_IDE0_ENABLE, value); 404 case 1: 405 return simple_feature_tweak(node, macio_unknown, 406 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value); 407 default: 408 return -ENODEV; 409 } 410 } 411 412 static long heathrow_ide_reset(struct device_node *node, long param, 413 long value) 414 { 415 switch(param) { 416 case 0: 417 return simple_feature_tweak(node, macio_unknown, 418 HEATHROW_FCR, HRW_IDE0_RESET_N, !value); 419 case 1: 420 return simple_feature_tweak(node, macio_unknown, 421 HEATHROW_FCR, HRW_IDE1_RESET_N, !value); 422 default: 423 return -ENODEV; 424 } 425 } 426 427 static long heathrow_bmac_enable(struct device_node *node, long param, 428 long value) 429 { 430 struct macio_chip* macio; 431 unsigned long flags; 432 433 macio = macio_find(node, 0); 434 if (!macio) 435 return -ENODEV; 436 if (value) { 437 LOCK(flags); 438 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); 439 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET); 440 UNLOCK(flags); 441 (void)MACIO_IN32(HEATHROW_FCR); 442 mdelay(10); 443 LOCK(flags); 444 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET); 445 UNLOCK(flags); 446 (void)MACIO_IN32(HEATHROW_FCR); 447 mdelay(10); 448 } else { 449 LOCK(flags); 450 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); 451 UNLOCK(flags); 452 } 453 return 0; 454 } 455 456 static long heathrow_sound_enable(struct device_node *node, long param, 457 long value) 458 { 459 struct macio_chip* macio; 460 unsigned long flags; 461 462 /* B&W G3 and Yikes don't support that properly (the 463 * sound appear to never come back after beeing shut down). 464 */ 465 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE || 466 pmac_mb.model_id == PMAC_TYPE_YIKES) 467 return 0; 468 469 macio = macio_find(node, 0); 470 if (!macio) 471 return -ENODEV; 472 if (value) { 473 LOCK(flags); 474 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 475 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 476 UNLOCK(flags); 477 (void)MACIO_IN32(HEATHROW_FCR); 478 } else { 479 LOCK(flags); 480 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); 481 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 482 UNLOCK(flags); 483 } 484 return 0; 485 } 486 487 static u32 save_fcr[6]; 488 static u32 save_mbcr; 489 static struct dbdma_regs save_dbdma[13]; 490 static struct dbdma_regs save_alt_dbdma[13]; 491 492 static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save) 493 { 494 int i; 495 496 /* Save state & config of DBDMA channels */ 497 for (i = 0; i < 13; i++) { 498 volatile struct dbdma_regs __iomem * chan = (void __iomem *) 499 (macio->base + ((0x8000+i*0x100)>>2)); 500 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi); 501 save[i].cmdptr = in_le32(&chan->cmdptr); 502 save[i].intr_sel = in_le32(&chan->intr_sel); 503 save[i].br_sel = in_le32(&chan->br_sel); 504 save[i].wait_sel = in_le32(&chan->wait_sel); 505 } 506 } 507 508 static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save) 509 { 510 int i; 511 512 /* Save state & config of DBDMA channels */ 513 for (i = 0; i < 13; i++) { 514 volatile struct dbdma_regs __iomem * chan = (void __iomem *) 515 (macio->base + ((0x8000+i*0x100)>>2)); 516 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16); 517 while (in_le32(&chan->status) & ACTIVE) 518 mb(); 519 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi); 520 out_le32(&chan->cmdptr, save[i].cmdptr); 521 out_le32(&chan->intr_sel, save[i].intr_sel); 522 out_le32(&chan->br_sel, save[i].br_sel); 523 out_le32(&chan->wait_sel, save[i].wait_sel); 524 } 525 } 526 527 static void heathrow_sleep(struct macio_chip *macio, int secondary) 528 { 529 if (secondary) { 530 dbdma_save(macio, save_alt_dbdma); 531 save_fcr[2] = MACIO_IN32(0x38); 532 save_fcr[3] = MACIO_IN32(0x3c); 533 } else { 534 dbdma_save(macio, save_dbdma); 535 save_fcr[0] = MACIO_IN32(0x38); 536 save_fcr[1] = MACIO_IN32(0x3c); 537 save_mbcr = MACIO_IN32(0x34); 538 /* Make sure sound is shut down */ 539 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); 540 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 541 /* This seems to be necessary as well or the fan 542 * keeps coming up and battery drains fast */ 543 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE); 544 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N); 545 /* Make sure eth is down even if module or sleep 546 * won't work properly */ 547 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET); 548 } 549 /* Make sure modem is shut down */ 550 MACIO_OUT8(HRW_GPIO_MODEM_RESET, 551 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1); 552 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 553 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE); 554 555 /* Let things settle */ 556 (void)MACIO_IN32(HEATHROW_FCR); 557 } 558 559 static void heathrow_wakeup(struct macio_chip *macio, int secondary) 560 { 561 if (secondary) { 562 MACIO_OUT32(0x38, save_fcr[2]); 563 (void)MACIO_IN32(0x38); 564 mdelay(1); 565 MACIO_OUT32(0x3c, save_fcr[3]); 566 (void)MACIO_IN32(0x38); 567 mdelay(10); 568 dbdma_restore(macio, save_alt_dbdma); 569 } else { 570 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE); 571 (void)MACIO_IN32(0x38); 572 mdelay(1); 573 MACIO_OUT32(0x3c, save_fcr[1]); 574 (void)MACIO_IN32(0x38); 575 mdelay(1); 576 MACIO_OUT32(0x34, save_mbcr); 577 (void)MACIO_IN32(0x38); 578 mdelay(10); 579 dbdma_restore(macio, save_dbdma); 580 } 581 } 582 583 static long heathrow_sleep_state(struct device_node *node, long param, 584 long value) 585 { 586 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 587 return -EPERM; 588 if (value == 1) { 589 if (macio_chips[1].type == macio_gatwick) 590 heathrow_sleep(&macio_chips[0], 1); 591 heathrow_sleep(&macio_chips[0], 0); 592 } else if (value == 0) { 593 heathrow_wakeup(&macio_chips[0], 0); 594 if (macio_chips[1].type == macio_gatwick) 595 heathrow_wakeup(&macio_chips[0], 1); 596 } 597 return 0; 598 } 599 600 static long core99_scc_enable(struct device_node *node, long param, long value) 601 { 602 struct macio_chip* macio; 603 unsigned long flags; 604 unsigned long chan_mask; 605 u32 fcr; 606 607 macio = macio_find(node, 0); 608 if (!macio) 609 return -ENODEV; 610 if (!strcmp(node->name, "ch-a")) 611 chan_mask = MACIO_FLAG_SCCA_ON; 612 else if (!strcmp(node->name, "ch-b")) 613 chan_mask = MACIO_FLAG_SCCB_ON; 614 else 615 return -ENODEV; 616 617 if (value) { 618 int need_reset_scc = 0; 619 int need_reset_irda = 0; 620 621 LOCK(flags); 622 fcr = MACIO_IN32(KEYLARGO_FCR0); 623 /* Check if scc cell need enabling */ 624 if (!(fcr & KL0_SCC_CELL_ENABLE)) { 625 fcr |= KL0_SCC_CELL_ENABLE; 626 need_reset_scc = 1; 627 } 628 if (chan_mask & MACIO_FLAG_SCCA_ON) { 629 fcr |= KL0_SCCA_ENABLE; 630 /* Don't enable line drivers for I2S modem */ 631 if ((param & 0xfff) == PMAC_SCC_I2S1) 632 fcr &= ~KL0_SCC_A_INTF_ENABLE; 633 else 634 fcr |= KL0_SCC_A_INTF_ENABLE; 635 } 636 if (chan_mask & MACIO_FLAG_SCCB_ON) { 637 fcr |= KL0_SCCB_ENABLE; 638 /* Perform irda specific inits */ 639 if ((param & 0xfff) == PMAC_SCC_IRDA) { 640 fcr &= ~KL0_SCC_B_INTF_ENABLE; 641 fcr |= KL0_IRDA_ENABLE; 642 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE; 643 fcr |= KL0_IRDA_SOURCE1_SEL; 644 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); 645 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); 646 need_reset_irda = 1; 647 } else 648 fcr |= KL0_SCC_B_INTF_ENABLE; 649 } 650 MACIO_OUT32(KEYLARGO_FCR0, fcr); 651 macio->flags |= chan_mask; 652 if (need_reset_scc) { 653 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET); 654 (void)MACIO_IN32(KEYLARGO_FCR0); 655 UNLOCK(flags); 656 mdelay(15); 657 LOCK(flags); 658 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET); 659 } 660 if (need_reset_irda) { 661 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET); 662 (void)MACIO_IN32(KEYLARGO_FCR0); 663 UNLOCK(flags); 664 mdelay(15); 665 LOCK(flags); 666 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET); 667 } 668 UNLOCK(flags); 669 if (param & PMAC_SCC_FLAG_XMON) 670 macio->flags |= MACIO_FLAG_SCC_LOCKED; 671 } else { 672 if (macio->flags & MACIO_FLAG_SCC_LOCKED) 673 return -EPERM; 674 LOCK(flags); 675 fcr = MACIO_IN32(KEYLARGO_FCR0); 676 if (chan_mask & MACIO_FLAG_SCCA_ON) 677 fcr &= ~KL0_SCCA_ENABLE; 678 if (chan_mask & MACIO_FLAG_SCCB_ON) { 679 fcr &= ~KL0_SCCB_ENABLE; 680 /* Perform irda specific clears */ 681 if ((param & 0xfff) == PMAC_SCC_IRDA) { 682 fcr &= ~KL0_IRDA_ENABLE; 683 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE); 684 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); 685 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); 686 } 687 } 688 MACIO_OUT32(KEYLARGO_FCR0, fcr); 689 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) { 690 fcr &= ~KL0_SCC_CELL_ENABLE; 691 MACIO_OUT32(KEYLARGO_FCR0, fcr); 692 } 693 macio->flags &= ~(chan_mask); 694 UNLOCK(flags); 695 mdelay(10); 696 } 697 return 0; 698 } 699 700 static long 701 core99_modem_enable(struct device_node *node, long param, long value) 702 { 703 struct macio_chip* macio; 704 u8 gpio; 705 unsigned long flags; 706 707 /* Hack for internal USB modem */ 708 if (node == NULL) { 709 if (macio_chips[0].type != macio_keylargo) 710 return -ENODEV; 711 node = macio_chips[0].of_node; 712 } 713 macio = macio_find(node, 0); 714 if (!macio) 715 return -ENODEV; 716 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); 717 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; 718 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; 719 720 if (!value) { 721 LOCK(flags); 722 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 723 UNLOCK(flags); 724 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 725 mdelay(250); 726 } 727 LOCK(flags); 728 if (value) { 729 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 730 UNLOCK(flags); 731 (void)MACIO_IN32(KEYLARGO_FCR2); 732 mdelay(250); 733 } else { 734 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 735 UNLOCK(flags); 736 } 737 if (value) { 738 LOCK(flags); 739 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 740 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 741 UNLOCK(flags); mdelay(250); LOCK(flags); 742 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 743 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 744 UNLOCK(flags); mdelay(250); LOCK(flags); 745 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 746 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 747 UNLOCK(flags); mdelay(250); 748 } 749 return 0; 750 } 751 752 static long 753 pangea_modem_enable(struct device_node *node, long param, long value) 754 { 755 struct macio_chip* macio; 756 u8 gpio; 757 unsigned long flags; 758 759 /* Hack for internal USB modem */ 760 if (node == NULL) { 761 if (macio_chips[0].type != macio_pangea && 762 macio_chips[0].type != macio_intrepid) 763 return -ENODEV; 764 node = macio_chips[0].of_node; 765 } 766 macio = macio_find(node, 0); 767 if (!macio) 768 return -ENODEV; 769 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); 770 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; 771 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; 772 773 if (!value) { 774 LOCK(flags); 775 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 776 UNLOCK(flags); 777 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 778 mdelay(250); 779 } 780 LOCK(flags); 781 if (value) { 782 MACIO_OUT8(KL_GPIO_MODEM_POWER, 783 KEYLARGO_GPIO_OUTPUT_ENABLE); 784 UNLOCK(flags); 785 (void)MACIO_IN32(KEYLARGO_FCR2); 786 mdelay(250); 787 } else { 788 MACIO_OUT8(KL_GPIO_MODEM_POWER, 789 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); 790 UNLOCK(flags); 791 } 792 if (value) { 793 LOCK(flags); 794 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 795 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 796 UNLOCK(flags); mdelay(250); LOCK(flags); 797 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 798 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 799 UNLOCK(flags); mdelay(250); LOCK(flags); 800 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 801 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 802 UNLOCK(flags); mdelay(250); 803 } 804 return 0; 805 } 806 807 static long 808 core99_ata100_enable(struct device_node *node, long value) 809 { 810 unsigned long flags; 811 struct pci_dev *pdev = NULL; 812 u8 pbus, pid; 813 int rc; 814 815 if (uninorth_rev < 0x24) 816 return -ENODEV; 817 818 LOCK(flags); 819 if (value) 820 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); 821 else 822 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); 823 (void)UN_IN(UNI_N_CLOCK_CNTL); 824 UNLOCK(flags); 825 udelay(20); 826 827 if (value) { 828 if (pci_device_from_OF_node(node, &pbus, &pid) == 0) 829 pdev = pci_find_slot(pbus, pid); 830 if (pdev == NULL) 831 return 0; 832 rc = pci_enable_device(pdev); 833 if (rc) 834 return rc; 835 pci_set_master(pdev); 836 } 837 return 0; 838 } 839 840 static long 841 core99_ide_enable(struct device_node *node, long param, long value) 842 { 843 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2 844 * based ata-100 845 */ 846 switch(param) { 847 case 0: 848 return simple_feature_tweak(node, macio_unknown, 849 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value); 850 case 1: 851 return simple_feature_tweak(node, macio_unknown, 852 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value); 853 case 2: 854 return simple_feature_tweak(node, macio_unknown, 855 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value); 856 case 3: 857 return core99_ata100_enable(node, value); 858 default: 859 return -ENODEV; 860 } 861 } 862 863 static long 864 core99_ide_reset(struct device_node *node, long param, long value) 865 { 866 switch(param) { 867 case 0: 868 return simple_feature_tweak(node, macio_unknown, 869 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value); 870 case 1: 871 return simple_feature_tweak(node, macio_unknown, 872 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value); 873 case 2: 874 return simple_feature_tweak(node, macio_unknown, 875 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value); 876 default: 877 return -ENODEV; 878 } 879 } 880 881 static long 882 core99_gmac_enable(struct device_node *node, long param, long value) 883 { 884 unsigned long flags; 885 886 LOCK(flags); 887 if (value) 888 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); 889 else 890 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); 891 (void)UN_IN(UNI_N_CLOCK_CNTL); 892 UNLOCK(flags); 893 udelay(20); 894 895 return 0; 896 } 897 898 static long 899 core99_gmac_phy_reset(struct device_node *node, long param, long value) 900 { 901 unsigned long flags; 902 struct macio_chip *macio; 903 904 macio = &macio_chips[0]; 905 if (macio->type != macio_keylargo && macio->type != macio_pangea && 906 macio->type != macio_intrepid) 907 return -ENODEV; 908 909 LOCK(flags); 910 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE); 911 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET); 912 UNLOCK(flags); 913 mdelay(10); 914 LOCK(flags); 915 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */ 916 KEYLARGO_GPIO_OUTOUT_DATA); 917 UNLOCK(flags); 918 mdelay(10); 919 920 return 0; 921 } 922 923 static long 924 core99_sound_chip_enable(struct device_node *node, long param, long value) 925 { 926 struct macio_chip* macio; 927 unsigned long flags; 928 929 macio = macio_find(node, 0); 930 if (!macio) 931 return -ENODEV; 932 933 /* Do a better probe code, screamer G4 desktops & 934 * iMacs can do that too, add a recalibrate in 935 * the driver as well 936 */ 937 if (pmac_mb.model_id == PMAC_TYPE_PISMO || 938 pmac_mb.model_id == PMAC_TYPE_TITANIUM) { 939 LOCK(flags); 940 if (value) 941 MACIO_OUT8(KL_GPIO_SOUND_POWER, 942 KEYLARGO_GPIO_OUTPUT_ENABLE | 943 KEYLARGO_GPIO_OUTOUT_DATA); 944 else 945 MACIO_OUT8(KL_GPIO_SOUND_POWER, 946 KEYLARGO_GPIO_OUTPUT_ENABLE); 947 (void)MACIO_IN8(KL_GPIO_SOUND_POWER); 948 UNLOCK(flags); 949 } 950 return 0; 951 } 952 953 static long 954 core99_airport_enable(struct device_node *node, long param, long value) 955 { 956 struct macio_chip* macio; 957 unsigned long flags; 958 int state; 959 960 macio = macio_find(node, 0); 961 if (!macio) 962 return -ENODEV; 963 964 /* Hint: we allow passing of macio itself for the sake of the 965 * sleep code 966 */ 967 if (node != macio->of_node && 968 (!node->parent || node->parent != macio->of_node)) 969 return -ENODEV; 970 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0; 971 if (value == state) 972 return 0; 973 if (value) { 974 /* This code is a reproduction of OF enable-cardslot 975 * and init-wireless methods, slightly hacked until 976 * I got it working. 977 */ 978 LOCK(flags); 979 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5); 980 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); 981 UNLOCK(flags); 982 mdelay(10); 983 LOCK(flags); 984 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4); 985 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); 986 UNLOCK(flags); 987 988 mdelay(10); 989 990 LOCK(flags); 991 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); 992 (void)MACIO_IN32(KEYLARGO_FCR2); 993 udelay(10); 994 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0); 995 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb); 996 udelay(10); 997 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28); 998 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa); 999 udelay(10); 1000 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28); 1001 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd); 1002 udelay(10); 1003 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28); 1004 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd); 1005 udelay(10); 1006 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28); 1007 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe); 1008 UNLOCK(flags); 1009 udelay(10); 1010 MACIO_OUT32(0x1c000, 0); 1011 mdelay(1); 1012 MACIO_OUT8(0x1a3e0, 0x41); 1013 (void)MACIO_IN8(0x1a3e0); 1014 udelay(10); 1015 LOCK(flags); 1016 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16); 1017 (void)MACIO_IN32(KEYLARGO_FCR2); 1018 UNLOCK(flags); 1019 mdelay(100); 1020 1021 macio->flags |= MACIO_FLAG_AIRPORT_ON; 1022 } else { 1023 LOCK(flags); 1024 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); 1025 (void)MACIO_IN32(KEYLARGO_FCR2); 1026 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0); 1027 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0); 1028 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0); 1029 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0); 1030 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0); 1031 (void)MACIO_IN8(KL_GPIO_AIRPORT_4); 1032 UNLOCK(flags); 1033 1034 macio->flags &= ~MACIO_FLAG_AIRPORT_ON; 1035 } 1036 return 0; 1037 } 1038 1039 #ifdef CONFIG_SMP 1040 static long 1041 core99_reset_cpu(struct device_node *node, long param, long value) 1042 { 1043 unsigned int reset_io = 0; 1044 unsigned long flags; 1045 struct macio_chip *macio; 1046 struct device_node *np; 1047 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0, 1048 KL_GPIO_RESET_CPU1, 1049 KL_GPIO_RESET_CPU2, 1050 KL_GPIO_RESET_CPU3 }; 1051 1052 macio = &macio_chips[0]; 1053 if (macio->type != macio_keylargo) 1054 return -ENODEV; 1055 1056 np = find_path_device("/cpus"); 1057 if (np == NULL) 1058 return -ENODEV; 1059 for (np = np->child; np != NULL; np = np->sibling) { 1060 const u32 *num = get_property(np, "reg", NULL); 1061 const u32 *rst = get_property(np, "soft-reset", NULL); 1062 if (num == NULL || rst == NULL) 1063 continue; 1064 if (param == *num) { 1065 reset_io = *rst; 1066 break; 1067 } 1068 } 1069 if (np == NULL || reset_io == 0) 1070 reset_io = dflt_reset_lines[param]; 1071 1072 LOCK(flags); 1073 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); 1074 (void)MACIO_IN8(reset_io); 1075 udelay(1); 1076 MACIO_OUT8(reset_io, 0); 1077 (void)MACIO_IN8(reset_io); 1078 UNLOCK(flags); 1079 1080 return 0; 1081 } 1082 #endif /* CONFIG_SMP */ 1083 1084 static long 1085 core99_usb_enable(struct device_node *node, long param, long value) 1086 { 1087 struct macio_chip *macio; 1088 unsigned long flags; 1089 const char *prop; 1090 int number; 1091 u32 reg; 1092 1093 macio = &macio_chips[0]; 1094 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1095 macio->type != macio_intrepid) 1096 return -ENODEV; 1097 1098 prop = get_property(node, "AAPL,clock-id", NULL); 1099 if (!prop) 1100 return -ENODEV; 1101 if (strncmp(prop, "usb0u048", 8) == 0) 1102 number = 0; 1103 else if (strncmp(prop, "usb1u148", 8) == 0) 1104 number = 2; 1105 else if (strncmp(prop, "usb2u248", 8) == 0) 1106 number = 4; 1107 else 1108 return -ENODEV; 1109 1110 /* Sorry for the brute-force locking, but this is only used during 1111 * sleep and the timing seem to be critical 1112 */ 1113 LOCK(flags); 1114 if (value) { 1115 /* Turn ON */ 1116 if (number == 0) { 1117 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); 1118 (void)MACIO_IN32(KEYLARGO_FCR0); 1119 UNLOCK(flags); 1120 mdelay(1); 1121 LOCK(flags); 1122 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); 1123 } else if (number == 2) { 1124 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); 1125 UNLOCK(flags); 1126 (void)MACIO_IN32(KEYLARGO_FCR0); 1127 mdelay(1); 1128 LOCK(flags); 1129 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); 1130 } else if (number == 4) { 1131 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); 1132 UNLOCK(flags); 1133 (void)MACIO_IN32(KEYLARGO_FCR1); 1134 mdelay(1); 1135 LOCK(flags); 1136 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE); 1137 } 1138 if (number < 4) { 1139 reg = MACIO_IN32(KEYLARGO_FCR4); 1140 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | 1141 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number)); 1142 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | 1143 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1)); 1144 MACIO_OUT32(KEYLARGO_FCR4, reg); 1145 (void)MACIO_IN32(KEYLARGO_FCR4); 1146 udelay(10); 1147 } else { 1148 reg = MACIO_IN32(KEYLARGO_FCR3); 1149 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | 1150 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0)); 1151 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | 1152 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1)); 1153 MACIO_OUT32(KEYLARGO_FCR3, reg); 1154 (void)MACIO_IN32(KEYLARGO_FCR3); 1155 udelay(10); 1156 } 1157 if (macio->type == macio_intrepid) { 1158 /* wait for clock stopped bits to clear */ 1159 u32 test0 = 0, test1 = 0; 1160 u32 status0, status1; 1161 int timeout = 1000; 1162 1163 UNLOCK(flags); 1164 switch (number) { 1165 case 0: 1166 test0 = UNI_N_CLOCK_STOPPED_USB0; 1167 test1 = UNI_N_CLOCK_STOPPED_USB0PCI; 1168 break; 1169 case 2: 1170 test0 = UNI_N_CLOCK_STOPPED_USB1; 1171 test1 = UNI_N_CLOCK_STOPPED_USB1PCI; 1172 break; 1173 case 4: 1174 test0 = UNI_N_CLOCK_STOPPED_USB2; 1175 test1 = UNI_N_CLOCK_STOPPED_USB2PCI; 1176 break; 1177 } 1178 do { 1179 if (--timeout <= 0) { 1180 printk(KERN_ERR "core99_usb_enable: " 1181 "Timeout waiting for clocks\n"); 1182 break; 1183 } 1184 mdelay(1); 1185 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0); 1186 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1); 1187 } while ((status0 & test0) | (status1 & test1)); 1188 LOCK(flags); 1189 } 1190 } else { 1191 /* Turn OFF */ 1192 if (number < 4) { 1193 reg = MACIO_IN32(KEYLARGO_FCR4); 1194 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | 1195 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number); 1196 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | 1197 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1); 1198 MACIO_OUT32(KEYLARGO_FCR4, reg); 1199 (void)MACIO_IN32(KEYLARGO_FCR4); 1200 udelay(1); 1201 } else { 1202 reg = MACIO_IN32(KEYLARGO_FCR3); 1203 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | 1204 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0); 1205 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | 1206 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1); 1207 MACIO_OUT32(KEYLARGO_FCR3, reg); 1208 (void)MACIO_IN32(KEYLARGO_FCR3); 1209 udelay(1); 1210 } 1211 if (number == 0) { 1212 if (macio->type != macio_intrepid) 1213 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); 1214 (void)MACIO_IN32(KEYLARGO_FCR0); 1215 udelay(1); 1216 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); 1217 (void)MACIO_IN32(KEYLARGO_FCR0); 1218 } else if (number == 2) { 1219 if (macio->type != macio_intrepid) 1220 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); 1221 (void)MACIO_IN32(KEYLARGO_FCR0); 1222 udelay(1); 1223 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); 1224 (void)MACIO_IN32(KEYLARGO_FCR0); 1225 } else if (number == 4) { 1226 udelay(1); 1227 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); 1228 (void)MACIO_IN32(KEYLARGO_FCR1); 1229 } 1230 udelay(1); 1231 } 1232 UNLOCK(flags); 1233 1234 return 0; 1235 } 1236 1237 static long 1238 core99_firewire_enable(struct device_node *node, long param, long value) 1239 { 1240 unsigned long flags; 1241 struct macio_chip *macio; 1242 1243 macio = &macio_chips[0]; 1244 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1245 macio->type != macio_intrepid) 1246 return -ENODEV; 1247 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) 1248 return -ENODEV; 1249 1250 LOCK(flags); 1251 if (value) { 1252 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); 1253 (void)UN_IN(UNI_N_CLOCK_CNTL); 1254 } else { 1255 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); 1256 (void)UN_IN(UNI_N_CLOCK_CNTL); 1257 } 1258 UNLOCK(flags); 1259 mdelay(1); 1260 1261 return 0; 1262 } 1263 1264 static long 1265 core99_firewire_cable_power(struct device_node *node, long param, long value) 1266 { 1267 unsigned long flags; 1268 struct macio_chip *macio; 1269 1270 /* Trick: we allow NULL node */ 1271 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0) 1272 return -ENODEV; 1273 macio = &macio_chips[0]; 1274 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1275 macio->type != macio_intrepid) 1276 return -ENODEV; 1277 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) 1278 return -ENODEV; 1279 1280 LOCK(flags); 1281 if (value) { 1282 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0); 1283 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); 1284 udelay(10); 1285 } else { 1286 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4); 1287 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10); 1288 } 1289 UNLOCK(flags); 1290 mdelay(1); 1291 1292 return 0; 1293 } 1294 1295 static long 1296 intrepid_aack_delay_enable(struct device_node *node, long param, long value) 1297 { 1298 unsigned long flags; 1299 1300 if (uninorth_rev < 0xd2) 1301 return -ENODEV; 1302 1303 LOCK(flags); 1304 if (param) 1305 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); 1306 else 1307 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); 1308 UNLOCK(flags); 1309 1310 return 0; 1311 } 1312 1313 1314 #endif /* CONFIG_POWER4 */ 1315 1316 static long 1317 core99_read_gpio(struct device_node *node, long param, long value) 1318 { 1319 struct macio_chip *macio = &macio_chips[0]; 1320 1321 return MACIO_IN8(param); 1322 } 1323 1324 1325 static long 1326 core99_write_gpio(struct device_node *node, long param, long value) 1327 { 1328 struct macio_chip *macio = &macio_chips[0]; 1329 1330 MACIO_OUT8(param, (u8)(value & 0xff)); 1331 return 0; 1332 } 1333 1334 #ifdef CONFIG_POWER4 1335 static long g5_gmac_enable(struct device_node *node, long param, long value) 1336 { 1337 struct macio_chip *macio = &macio_chips[0]; 1338 unsigned long flags; 1339 1340 if (node == NULL) 1341 return -ENODEV; 1342 1343 LOCK(flags); 1344 if (value) { 1345 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); 1346 mb(); 1347 k2_skiplist[0] = NULL; 1348 } else { 1349 k2_skiplist[0] = node; 1350 mb(); 1351 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); 1352 } 1353 1354 UNLOCK(flags); 1355 mdelay(1); 1356 1357 return 0; 1358 } 1359 1360 static long g5_fw_enable(struct device_node *node, long param, long value) 1361 { 1362 struct macio_chip *macio = &macio_chips[0]; 1363 unsigned long flags; 1364 1365 if (node == NULL) 1366 return -ENODEV; 1367 1368 LOCK(flags); 1369 if (value) { 1370 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); 1371 mb(); 1372 k2_skiplist[1] = NULL; 1373 } else { 1374 k2_skiplist[1] = node; 1375 mb(); 1376 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); 1377 } 1378 1379 UNLOCK(flags); 1380 mdelay(1); 1381 1382 return 0; 1383 } 1384 1385 static long g5_mpic_enable(struct device_node *node, long param, long value) 1386 { 1387 unsigned long flags; 1388 struct device_node *parent = of_get_parent(node); 1389 int is_u3; 1390 1391 if (parent == NULL) 1392 return 0; 1393 is_u3 = strcmp(parent->name, "u3") == 0 || 1394 strcmp(parent->name, "u4") == 0; 1395 of_node_put(parent); 1396 if (!is_u3) 1397 return 0; 1398 1399 LOCK(flags); 1400 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE); 1401 UNLOCK(flags); 1402 1403 return 0; 1404 } 1405 1406 static long g5_eth_phy_reset(struct device_node *node, long param, long value) 1407 { 1408 struct macio_chip *macio = &macio_chips[0]; 1409 struct device_node *phy; 1410 int need_reset; 1411 1412 /* 1413 * We must not reset the combo PHYs, only the BCM5221 found in 1414 * the iMac G5. 1415 */ 1416 phy = of_get_next_child(node, NULL); 1417 if (!phy) 1418 return -ENODEV; 1419 need_reset = device_is_compatible(phy, "B5221"); 1420 of_node_put(phy); 1421 if (!need_reset) 1422 return 0; 1423 1424 /* PHY reset is GPIO 29, not in device-tree unfortunately */ 1425 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 1426 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); 1427 /* Thankfully, this is now always called at a time when we can 1428 * schedule by sungem. 1429 */ 1430 msleep(10); 1431 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0); 1432 1433 return 0; 1434 } 1435 1436 static long g5_i2s_enable(struct device_node *node, long param, long value) 1437 { 1438 /* Very crude implementation for now */ 1439 struct macio_chip *macio = &macio_chips[0]; 1440 unsigned long flags; 1441 int cell; 1442 u32 fcrs[3][3] = { 1443 { 0, 1444 K2_FCR1_I2S0_CELL_ENABLE | 1445 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE, 1446 KL3_I2S0_CLK18_ENABLE 1447 }, 1448 { KL0_SCC_A_INTF_ENABLE, 1449 K2_FCR1_I2S1_CELL_ENABLE | 1450 K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE, 1451 KL3_I2S1_CLK18_ENABLE 1452 }, 1453 { KL0_SCC_B_INTF_ENABLE, 1454 SH_FCR1_I2S2_CELL_ENABLE | 1455 SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE, 1456 SH_FCR3_I2S2_CLK18_ENABLE 1457 }, 1458 }; 1459 1460 if (macio->type != macio_keylargo2 && macio->type != macio_shasta) 1461 return -ENODEV; 1462 if (strncmp(node->name, "i2s-", 4)) 1463 return -ENODEV; 1464 cell = node->name[4] - 'a'; 1465 switch(cell) { 1466 case 0: 1467 case 1: 1468 break; 1469 case 2: 1470 if (macio->type == macio_shasta) 1471 break; 1472 default: 1473 return -ENODEV; 1474 } 1475 1476 LOCK(flags); 1477 if (value) { 1478 MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]); 1479 MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]); 1480 MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]); 1481 } else { 1482 MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]); 1483 MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]); 1484 MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]); 1485 } 1486 udelay(10); 1487 UNLOCK(flags); 1488 1489 return 0; 1490 } 1491 1492 1493 #ifdef CONFIG_SMP 1494 static long g5_reset_cpu(struct device_node *node, long param, long value) 1495 { 1496 unsigned int reset_io = 0; 1497 unsigned long flags; 1498 struct macio_chip *macio; 1499 struct device_node *np; 1500 1501 macio = &macio_chips[0]; 1502 if (macio->type != macio_keylargo2 && macio->type != macio_shasta) 1503 return -ENODEV; 1504 1505 np = find_path_device("/cpus"); 1506 if (np == NULL) 1507 return -ENODEV; 1508 for (np = np->child; np != NULL; np = np->sibling) { 1509 const u32 *num = get_property(np, "reg", NULL); 1510 const u32 *rst = get_property(np, "soft-reset", NULL); 1511 if (num == NULL || rst == NULL) 1512 continue; 1513 if (param == *num) { 1514 reset_io = *rst; 1515 break; 1516 } 1517 } 1518 if (np == NULL || reset_io == 0) 1519 return -ENODEV; 1520 1521 LOCK(flags); 1522 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); 1523 (void)MACIO_IN8(reset_io); 1524 udelay(1); 1525 MACIO_OUT8(reset_io, 0); 1526 (void)MACIO_IN8(reset_io); 1527 UNLOCK(flags); 1528 1529 return 0; 1530 } 1531 #endif /* CONFIG_SMP */ 1532 1533 /* 1534 * This can be called from pmac_smp so isn't static 1535 * 1536 * This takes the second CPU off the bus on dual CPU machines 1537 * running UP 1538 */ 1539 void g5_phy_disable_cpu1(void) 1540 { 1541 if (uninorth_maj == 3) 1542 UN_OUT(U3_API_PHY_CONFIG_1, 0); 1543 } 1544 #endif /* CONFIG_POWER4 */ 1545 1546 #ifndef CONFIG_POWER4 1547 1548 1549 #ifdef CONFIG_PM 1550 static u32 save_gpio_levels[2]; 1551 static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT]; 1552 static u8 save_gpio_normal[KEYLARGO_GPIO_CNT]; 1553 static u32 save_unin_clock_ctl; 1554 1555 static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode) 1556 { 1557 u32 temp; 1558 1559 if (sleep_mode) { 1560 mdelay(1); 1561 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND); 1562 (void)MACIO_IN32(KEYLARGO_FCR0); 1563 mdelay(1); 1564 } 1565 1566 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1567 KL0_SCC_CELL_ENABLE | 1568 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE | 1569 KL0_IRDA_CLK19_ENABLE); 1570 1571 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK); 1572 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE); 1573 1574 MACIO_BIC(KEYLARGO_FCR1, 1575 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | 1576 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | 1577 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1578 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1579 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1580 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N | 1581 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N | 1582 KL1_UIDE_ENABLE); 1583 1584 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 1585 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE); 1586 1587 temp = MACIO_IN32(KEYLARGO_FCR3); 1588 if (macio->rev >= 2) { 1589 temp |= KL3_SHUTDOWN_PLL2X; 1590 if (sleep_mode) 1591 temp |= KL3_SHUTDOWN_PLL_TOTAL; 1592 } 1593 1594 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | 1595 KL3_SHUTDOWN_PLLKW35; 1596 if (sleep_mode) 1597 temp |= KL3_SHUTDOWN_PLLKW12; 1598 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE 1599 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); 1600 if (sleep_mode) 1601 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE); 1602 MACIO_OUT32(KEYLARGO_FCR3, temp); 1603 1604 /* Flush posted writes & wait a bit */ 1605 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); 1606 } 1607 1608 static void pangea_shutdown(struct macio_chip *macio, int sleep_mode) 1609 { 1610 u32 temp; 1611 1612 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1613 KL0_SCC_CELL_ENABLE | 1614 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE); 1615 1616 MACIO_BIC(KEYLARGO_FCR1, 1617 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | 1618 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | 1619 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1620 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1621 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1622 KL1_UIDE_ENABLE); 1623 if (pmac_mb.board_flags & PMAC_MB_MOBILE) 1624 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); 1625 1626 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 1627 1628 temp = MACIO_IN32(KEYLARGO_FCR3); 1629 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | 1630 KL3_SHUTDOWN_PLLKW35; 1631 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE 1632 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE); 1633 if (sleep_mode) 1634 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE); 1635 MACIO_OUT32(KEYLARGO_FCR3, temp); 1636 1637 /* Flush posted writes & wait a bit */ 1638 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); 1639 } 1640 1641 static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode) 1642 { 1643 u32 temp; 1644 1645 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1646 KL0_SCC_CELL_ENABLE); 1647 1648 MACIO_BIC(KEYLARGO_FCR1, 1649 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1650 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1651 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1652 KL1_EIDE0_ENABLE); 1653 if (pmac_mb.board_flags & PMAC_MB_MOBILE) 1654 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); 1655 1656 temp = MACIO_IN32(KEYLARGO_FCR3); 1657 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | 1658 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); 1659 if (sleep_mode) 1660 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE); 1661 MACIO_OUT32(KEYLARGO_FCR3, temp); 1662 1663 /* Flush posted writes & wait a bit */ 1664 (void)MACIO_IN32(KEYLARGO_FCR0); 1665 mdelay(10); 1666 } 1667 1668 1669 static int 1670 core99_sleep(void) 1671 { 1672 struct macio_chip *macio; 1673 int i; 1674 1675 macio = &macio_chips[0]; 1676 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1677 macio->type != macio_intrepid) 1678 return -ENODEV; 1679 1680 /* We power off the wireless slot in case it was not done 1681 * by the driver. We don't power it on automatically however 1682 */ 1683 if (macio->flags & MACIO_FLAG_AIRPORT_ON) 1684 core99_airport_enable(macio->of_node, 0, 0); 1685 1686 /* We power off the FW cable. Should be done by the driver... */ 1687 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) { 1688 core99_firewire_enable(NULL, 0, 0); 1689 core99_firewire_cable_power(NULL, 0, 0); 1690 } 1691 1692 /* We make sure int. modem is off (in case driver lost it) */ 1693 if (macio->type == macio_keylargo) 1694 core99_modem_enable(macio->of_node, 0, 0); 1695 else 1696 pangea_modem_enable(macio->of_node, 0, 0); 1697 1698 /* We make sure the sound is off as well */ 1699 core99_sound_chip_enable(macio->of_node, 0, 0); 1700 1701 /* 1702 * Save various bits of KeyLargo 1703 */ 1704 1705 /* Save the state of the various GPIOs */ 1706 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0); 1707 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1); 1708 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++) 1709 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i); 1710 for (i=0; i<KEYLARGO_GPIO_CNT; i++) 1711 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i); 1712 1713 /* Save the FCRs */ 1714 if (macio->type == macio_keylargo) 1715 save_mbcr = MACIO_IN32(KEYLARGO_MBCR); 1716 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0); 1717 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1); 1718 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2); 1719 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3); 1720 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4); 1721 if (macio->type == macio_pangea || macio->type == macio_intrepid) 1722 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5); 1723 1724 /* Save state & config of DBDMA channels */ 1725 dbdma_save(macio, save_dbdma); 1726 1727 /* 1728 * Turn off as much as we can 1729 */ 1730 if (macio->type == macio_pangea) 1731 pangea_shutdown(macio, 1); 1732 else if (macio->type == macio_intrepid) 1733 intrepid_shutdown(macio, 1); 1734 else if (macio->type == macio_keylargo) 1735 keylargo_shutdown(macio, 1); 1736 1737 /* 1738 * Put the host bridge to sleep 1739 */ 1740 1741 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL); 1742 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it 1743 * enabled ! 1744 */ 1745 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl & 1746 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/)); 1747 udelay(100); 1748 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); 1749 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP); 1750 mdelay(10); 1751 1752 /* 1753 * FIXME: A bit of black magic with OpenPIC (don't ask me why) 1754 */ 1755 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { 1756 MACIO_BIS(0x506e0, 0x00400000); 1757 MACIO_BIS(0x506e0, 0x80000000); 1758 } 1759 return 0; 1760 } 1761 1762 static int 1763 core99_wake_up(void) 1764 { 1765 struct macio_chip *macio; 1766 int i; 1767 1768 macio = &macio_chips[0]; 1769 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1770 macio->type != macio_intrepid) 1771 return -ENODEV; 1772 1773 /* 1774 * Wakeup the host bridge 1775 */ 1776 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); 1777 udelay(10); 1778 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); 1779 udelay(10); 1780 1781 /* 1782 * Restore KeyLargo 1783 */ 1784 1785 if (macio->type == macio_keylargo) { 1786 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr); 1787 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10); 1788 } 1789 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]); 1790 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10); 1791 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]); 1792 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10); 1793 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]); 1794 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10); 1795 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]); 1796 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10); 1797 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]); 1798 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10); 1799 if (macio->type == macio_pangea || macio->type == macio_intrepid) { 1800 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]); 1801 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10); 1802 } 1803 1804 dbdma_restore(macio, save_dbdma); 1805 1806 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]); 1807 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]); 1808 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++) 1809 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]); 1810 for (i=0; i<KEYLARGO_GPIO_CNT; i++) 1811 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]); 1812 1813 /* FIXME more black magic with OpenPIC ... */ 1814 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { 1815 MACIO_BIC(0x506e0, 0x00400000); 1816 MACIO_BIC(0x506e0, 0x80000000); 1817 } 1818 1819 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl); 1820 udelay(100); 1821 1822 return 0; 1823 } 1824 1825 #endif /* CONFIG_PM */ 1826 1827 static long 1828 core99_sleep_state(struct device_node *node, long param, long value) 1829 { 1830 /* Param == 1 means to enter the "fake sleep" mode that is 1831 * used for CPU speed switch 1832 */ 1833 if (param == 1) { 1834 if (value == 1) { 1835 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); 1836 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2); 1837 } else { 1838 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); 1839 udelay(10); 1840 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); 1841 udelay(10); 1842 } 1843 return 0; 1844 } 1845 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 1846 return -EPERM; 1847 1848 #ifdef CONFIG_PM 1849 if (value == 1) 1850 return core99_sleep(); 1851 else if (value == 0) 1852 return core99_wake_up(); 1853 1854 #endif /* CONFIG_PM */ 1855 return 0; 1856 } 1857 1858 #endif /* CONFIG_POWER4 */ 1859 1860 static long 1861 generic_dev_can_wake(struct device_node *node, long param, long value) 1862 { 1863 /* Todo: eventually check we are really dealing with on-board 1864 * video device ... 1865 */ 1866 1867 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP) 1868 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP; 1869 return 0; 1870 } 1871 1872 static long generic_get_mb_info(struct device_node *node, long param, long value) 1873 { 1874 switch(param) { 1875 case PMAC_MB_INFO_MODEL: 1876 return pmac_mb.model_id; 1877 case PMAC_MB_INFO_FLAGS: 1878 return pmac_mb.board_flags; 1879 case PMAC_MB_INFO_NAME: 1880 /* hack hack hack... but should work */ 1881 *((const char **)value) = pmac_mb.model_name; 1882 return 0; 1883 } 1884 return -EINVAL; 1885 } 1886 1887 1888 /* 1889 * Table definitions 1890 */ 1891 1892 /* Used on any machine 1893 */ 1894 static struct feature_table_entry any_features[] = { 1895 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info }, 1896 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake }, 1897 { 0, NULL } 1898 }; 1899 1900 #ifndef CONFIG_POWER4 1901 1902 /* OHare based motherboards. Currently, we only use these on the 1903 * 2400,3400 and 3500 series powerbooks. Some older desktops seem 1904 * to have issues with turning on/off those asic cells 1905 */ 1906 static struct feature_table_entry ohare_features[] = { 1907 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1908 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable }, 1909 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable }, 1910 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable}, 1911 { PMAC_FTR_IDE_RESET, ohare_ide_reset}, 1912 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state }, 1913 { 0, NULL } 1914 }; 1915 1916 /* Heathrow desktop machines (Beige G3). 1917 * Separated as some features couldn't be properly tested 1918 * and the serial port control bits appear to confuse it. 1919 */ 1920 static struct feature_table_entry heathrow_desktop_features[] = { 1921 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1922 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1923 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1924 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1925 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1926 { 0, NULL } 1927 }; 1928 1929 /* Heathrow based laptop, that is the Wallstreet and mainstreet 1930 * powerbooks. 1931 */ 1932 static struct feature_table_entry heathrow_laptop_features[] = { 1933 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1934 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable }, 1935 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1936 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1937 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1938 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1939 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1940 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable }, 1941 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state }, 1942 { 0, NULL } 1943 }; 1944 1945 /* Paddington based machines 1946 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4. 1947 */ 1948 static struct feature_table_entry paddington_features[] = { 1949 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1950 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable }, 1951 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1952 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1953 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1954 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1955 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1956 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable }, 1957 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state }, 1958 { 0, NULL } 1959 }; 1960 1961 /* Core99 & MacRISC 2 machines (all machines released since the 1962 * iBook (included), that is all AGP machines, except pangea 1963 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo 1964 * used on iBook2 & iMac "flow power". 1965 */ 1966 static struct feature_table_entry core99_features[] = { 1967 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 1968 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable }, 1969 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 1970 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 1971 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 1972 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 1973 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 1974 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 1975 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 1976 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 1977 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 1978 #ifdef CONFIG_PM 1979 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 1980 #endif 1981 #ifdef CONFIG_SMP 1982 { PMAC_FTR_RESET_CPU, core99_reset_cpu }, 1983 #endif /* CONFIG_SMP */ 1984 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 1985 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 1986 { 0, NULL } 1987 }; 1988 1989 /* RackMac 1990 */ 1991 static struct feature_table_entry rackmac_features[] = { 1992 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 1993 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 1994 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 1995 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 1996 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 1997 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 1998 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 1999 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2000 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2001 #ifdef CONFIG_SMP 2002 { PMAC_FTR_RESET_CPU, core99_reset_cpu }, 2003 #endif /* CONFIG_SMP */ 2004 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2005 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2006 { 0, NULL } 2007 }; 2008 2009 /* Pangea features 2010 */ 2011 static struct feature_table_entry pangea_features[] = { 2012 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2013 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable }, 2014 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2015 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2016 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2017 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2018 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 2019 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 2020 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2021 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2022 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2023 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2024 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2025 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2026 { 0, NULL } 2027 }; 2028 2029 /* Intrepid features 2030 */ 2031 static struct feature_table_entry intrepid_features[] = { 2032 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2033 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable }, 2034 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2035 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2036 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2037 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2038 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 2039 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 2040 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2041 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2042 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2043 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2044 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2045 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2046 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable }, 2047 { 0, NULL } 2048 }; 2049 2050 #else /* CONFIG_POWER4 */ 2051 2052 /* G5 features 2053 */ 2054 static struct feature_table_entry g5_features[] = { 2055 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable }, 2056 { PMAC_FTR_1394_ENABLE, g5_fw_enable }, 2057 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable }, 2058 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset }, 2059 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable }, 2060 #ifdef CONFIG_SMP 2061 { PMAC_FTR_RESET_CPU, g5_reset_cpu }, 2062 #endif /* CONFIG_SMP */ 2063 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2064 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2065 { 0, NULL } 2066 }; 2067 2068 #endif /* CONFIG_POWER4 */ 2069 2070 static struct pmac_mb_def pmac_mb_defs[] = { 2071 #ifndef CONFIG_POWER4 2072 /* 2073 * Desktops 2074 */ 2075 2076 { "AAPL,8500", "PowerMac 8500/8600", 2077 PMAC_TYPE_PSURGE, NULL, 2078 0 2079 }, 2080 { "AAPL,9500", "PowerMac 9500/9600", 2081 PMAC_TYPE_PSURGE, NULL, 2082 0 2083 }, 2084 { "AAPL,7200", "PowerMac 7200", 2085 PMAC_TYPE_PSURGE, NULL, 2086 0 2087 }, 2088 { "AAPL,7300", "PowerMac 7200/7300", 2089 PMAC_TYPE_PSURGE, NULL, 2090 0 2091 }, 2092 { "AAPL,7500", "PowerMac 7500", 2093 PMAC_TYPE_PSURGE, NULL, 2094 0 2095 }, 2096 { "AAPL,ShinerESB", "Apple Network Server", 2097 PMAC_TYPE_ANS, NULL, 2098 0 2099 }, 2100 { "AAPL,e407", "Alchemy", 2101 PMAC_TYPE_ALCHEMY, NULL, 2102 0 2103 }, 2104 { "AAPL,e411", "Gazelle", 2105 PMAC_TYPE_GAZELLE, NULL, 2106 0 2107 }, 2108 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)", 2109 PMAC_TYPE_GOSSAMER, heathrow_desktop_features, 2110 0 2111 }, 2112 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)", 2113 PMAC_TYPE_SILK, heathrow_desktop_features, 2114 0 2115 }, 2116 { "PowerMac1,1", "Blue&White G3", 2117 PMAC_TYPE_YOSEMITE, paddington_features, 2118 0 2119 }, 2120 { "PowerMac1,2", "PowerMac G4 PCI Graphics", 2121 PMAC_TYPE_YIKES, paddington_features, 2122 0 2123 }, 2124 { "PowerMac2,1", "iMac FireWire", 2125 PMAC_TYPE_FW_IMAC, core99_features, 2126 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2127 }, 2128 { "PowerMac2,2", "iMac FireWire", 2129 PMAC_TYPE_FW_IMAC, core99_features, 2130 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2131 }, 2132 { "PowerMac3,1", "PowerMac G4 AGP Graphics", 2133 PMAC_TYPE_SAWTOOTH, core99_features, 2134 PMAC_MB_OLD_CORE99 2135 }, 2136 { "PowerMac3,2", "PowerMac G4 AGP Graphics", 2137 PMAC_TYPE_SAWTOOTH, core99_features, 2138 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2139 }, 2140 { "PowerMac3,3", "PowerMac G4 AGP Graphics", 2141 PMAC_TYPE_SAWTOOTH, core99_features, 2142 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2143 }, 2144 { "PowerMac3,4", "PowerMac G4 Silver", 2145 PMAC_TYPE_QUICKSILVER, core99_features, 2146 PMAC_MB_MAY_SLEEP 2147 }, 2148 { "PowerMac3,5", "PowerMac G4 Silver", 2149 PMAC_TYPE_QUICKSILVER, core99_features, 2150 PMAC_MB_MAY_SLEEP 2151 }, 2152 { "PowerMac3,6", "PowerMac G4 Windtunnel", 2153 PMAC_TYPE_WINDTUNNEL, core99_features, 2154 PMAC_MB_MAY_SLEEP, 2155 }, 2156 { "PowerMac4,1", "iMac \"Flower Power\"", 2157 PMAC_TYPE_PANGEA_IMAC, pangea_features, 2158 PMAC_MB_MAY_SLEEP 2159 }, 2160 { "PowerMac4,2", "Flat panel iMac", 2161 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features, 2162 PMAC_MB_CAN_SLEEP 2163 }, 2164 { "PowerMac4,4", "eMac", 2165 PMAC_TYPE_EMAC, core99_features, 2166 PMAC_MB_MAY_SLEEP 2167 }, 2168 { "PowerMac5,1", "PowerMac G4 Cube", 2169 PMAC_TYPE_CUBE, core99_features, 2170 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2171 }, 2172 { "PowerMac6,1", "Flat panel iMac", 2173 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2174 PMAC_MB_MAY_SLEEP, 2175 }, 2176 { "PowerMac6,3", "Flat panel iMac", 2177 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2178 PMAC_MB_MAY_SLEEP, 2179 }, 2180 { "PowerMac6,4", "eMac", 2181 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2182 PMAC_MB_MAY_SLEEP, 2183 }, 2184 { "PowerMac10,1", "Mac mini", 2185 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2186 PMAC_MB_MAY_SLEEP, 2187 }, 2188 { "iMac,1", "iMac (first generation)", 2189 PMAC_TYPE_ORIG_IMAC, paddington_features, 2190 0 2191 }, 2192 2193 /* 2194 * Xserve's 2195 */ 2196 2197 { "RackMac1,1", "XServe", 2198 PMAC_TYPE_RACKMAC, rackmac_features, 2199 0, 2200 }, 2201 { "RackMac1,2", "XServe rev. 2", 2202 PMAC_TYPE_RACKMAC, rackmac_features, 2203 0, 2204 }, 2205 2206 /* 2207 * Laptops 2208 */ 2209 2210 { "AAPL,3400/2400", "PowerBook 3400", 2211 PMAC_TYPE_HOOPER, ohare_features, 2212 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2213 }, 2214 { "AAPL,3500", "PowerBook 3500", 2215 PMAC_TYPE_KANGA, ohare_features, 2216 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2217 }, 2218 { "AAPL,PowerBook1998", "PowerBook Wallstreet", 2219 PMAC_TYPE_WALLSTREET, heathrow_laptop_features, 2220 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2221 }, 2222 { "PowerBook1,1", "PowerBook 101 (Lombard)", 2223 PMAC_TYPE_101_PBOOK, paddington_features, 2224 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2225 }, 2226 { "PowerBook2,1", "iBook (first generation)", 2227 PMAC_TYPE_ORIG_IBOOK, core99_features, 2228 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2229 }, 2230 { "PowerBook2,2", "iBook FireWire", 2231 PMAC_TYPE_FW_IBOOK, core99_features, 2232 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | 2233 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2234 }, 2235 { "PowerBook3,1", "PowerBook Pismo", 2236 PMAC_TYPE_PISMO, core99_features, 2237 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | 2238 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2239 }, 2240 { "PowerBook3,2", "PowerBook Titanium", 2241 PMAC_TYPE_TITANIUM, core99_features, 2242 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2243 }, 2244 { "PowerBook3,3", "PowerBook Titanium II", 2245 PMAC_TYPE_TITANIUM2, core99_features, 2246 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2247 }, 2248 { "PowerBook3,4", "PowerBook Titanium III", 2249 PMAC_TYPE_TITANIUM3, core99_features, 2250 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2251 }, 2252 { "PowerBook3,5", "PowerBook Titanium IV", 2253 PMAC_TYPE_TITANIUM4, core99_features, 2254 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2255 }, 2256 { "PowerBook4,1", "iBook 2", 2257 PMAC_TYPE_IBOOK2, pangea_features, 2258 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2259 }, 2260 { "PowerBook4,2", "iBook 2", 2261 PMAC_TYPE_IBOOK2, pangea_features, 2262 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2263 }, 2264 { "PowerBook4,3", "iBook 2 rev. 2", 2265 PMAC_TYPE_IBOOK2, pangea_features, 2266 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2267 }, 2268 { "PowerBook5,1", "PowerBook G4 17\"", 2269 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2270 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2271 }, 2272 { "PowerBook5,2", "PowerBook G4 15\"", 2273 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2274 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2275 }, 2276 { "PowerBook5,3", "PowerBook G4 17\"", 2277 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2278 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2279 }, 2280 { "PowerBook5,4", "PowerBook G4 15\"", 2281 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2282 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2283 }, 2284 { "PowerBook5,5", "PowerBook G4 17\"", 2285 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2286 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2287 }, 2288 { "PowerBook5,6", "PowerBook G4 15\"", 2289 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2290 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2291 }, 2292 { "PowerBook5,7", "PowerBook G4 17\"", 2293 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2294 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2295 }, 2296 { "PowerBook5,8", "PowerBook G4 15\"", 2297 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2298 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE, 2299 }, 2300 { "PowerBook5,9", "PowerBook G4 17\"", 2301 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2302 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE, 2303 }, 2304 { "PowerBook6,1", "PowerBook G4 12\"", 2305 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2306 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2307 }, 2308 { "PowerBook6,2", "PowerBook G4", 2309 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2310 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2311 }, 2312 { "PowerBook6,3", "iBook G4", 2313 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2314 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2315 }, 2316 { "PowerBook6,4", "PowerBook G4 12\"", 2317 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2318 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2319 }, 2320 { "PowerBook6,5", "iBook G4", 2321 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2322 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2323 }, 2324 { "PowerBook6,7", "iBook G4", 2325 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2326 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2327 }, 2328 { "PowerBook6,8", "PowerBook G4 12\"", 2329 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2330 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2331 }, 2332 #else /* CONFIG_POWER4 */ 2333 { "PowerMac7,2", "PowerMac G5", 2334 PMAC_TYPE_POWERMAC_G5, g5_features, 2335 0, 2336 }, 2337 #ifdef CONFIG_PPC64 2338 { "PowerMac7,3", "PowerMac G5", 2339 PMAC_TYPE_POWERMAC_G5, g5_features, 2340 0, 2341 }, 2342 { "PowerMac8,1", "iMac G5", 2343 PMAC_TYPE_IMAC_G5, g5_features, 2344 0, 2345 }, 2346 { "PowerMac9,1", "PowerMac G5", 2347 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2348 0, 2349 }, 2350 { "PowerMac11,2", "PowerMac G5 Dual Core", 2351 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2352 0, 2353 }, 2354 { "PowerMac12,1", "iMac G5 (iSight)", 2355 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2356 0, 2357 }, 2358 { "RackMac3,1", "XServe G5", 2359 PMAC_TYPE_XSERVE_G5, g5_features, 2360 0, 2361 }, 2362 #endif /* CONFIG_PPC64 */ 2363 #endif /* CONFIG_POWER4 */ 2364 }; 2365 2366 /* 2367 * The toplevel feature_call callback 2368 */ 2369 long pmac_do_feature_call(unsigned int selector, ...) 2370 { 2371 struct device_node *node; 2372 long param, value; 2373 int i; 2374 feature_call func = NULL; 2375 va_list args; 2376 2377 if (pmac_mb.features) 2378 for (i=0; pmac_mb.features[i].function; i++) 2379 if (pmac_mb.features[i].selector == selector) { 2380 func = pmac_mb.features[i].function; 2381 break; 2382 } 2383 if (!func) 2384 for (i=0; any_features[i].function; i++) 2385 if (any_features[i].selector == selector) { 2386 func = any_features[i].function; 2387 break; 2388 } 2389 if (!func) 2390 return -ENODEV; 2391 2392 va_start(args, selector); 2393 node = (struct device_node*)va_arg(args, void*); 2394 param = va_arg(args, long); 2395 value = va_arg(args, long); 2396 va_end(args); 2397 2398 return func(node, param, value); 2399 } 2400 2401 static int __init probe_motherboard(void) 2402 { 2403 int i; 2404 struct macio_chip *macio = &macio_chips[0]; 2405 const char *model = NULL; 2406 struct device_node *dt; 2407 2408 /* Lookup known motherboard type in device-tree. First try an 2409 * exact match on the "model" property, then try a "compatible" 2410 * match is none is found. 2411 */ 2412 dt = find_devices("device-tree"); 2413 if (dt != NULL) 2414 model = get_property(dt, "model", NULL); 2415 for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) { 2416 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) { 2417 pmac_mb = pmac_mb_defs[i]; 2418 goto found; 2419 } 2420 } 2421 for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) { 2422 if (machine_is_compatible(pmac_mb_defs[i].model_string)) { 2423 pmac_mb = pmac_mb_defs[i]; 2424 goto found; 2425 } 2426 } 2427 2428 /* Fallback to selection depending on mac-io chip type */ 2429 switch(macio->type) { 2430 #ifndef CONFIG_POWER4 2431 case macio_grand_central: 2432 pmac_mb.model_id = PMAC_TYPE_PSURGE; 2433 pmac_mb.model_name = "Unknown PowerSurge"; 2434 break; 2435 case macio_ohare: 2436 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE; 2437 pmac_mb.model_name = "Unknown OHare-based"; 2438 break; 2439 case macio_heathrow: 2440 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW; 2441 pmac_mb.model_name = "Unknown Heathrow-based"; 2442 pmac_mb.features = heathrow_desktop_features; 2443 break; 2444 case macio_paddington: 2445 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON; 2446 pmac_mb.model_name = "Unknown Paddington-based"; 2447 pmac_mb.features = paddington_features; 2448 break; 2449 case macio_keylargo: 2450 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99; 2451 pmac_mb.model_name = "Unknown Keylargo-based"; 2452 pmac_mb.features = core99_features; 2453 break; 2454 case macio_pangea: 2455 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA; 2456 pmac_mb.model_name = "Unknown Pangea-based"; 2457 pmac_mb.features = pangea_features; 2458 break; 2459 case macio_intrepid: 2460 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID; 2461 pmac_mb.model_name = "Unknown Intrepid-based"; 2462 pmac_mb.features = intrepid_features; 2463 break; 2464 #else /* CONFIG_POWER4 */ 2465 case macio_keylargo2: 2466 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2; 2467 pmac_mb.model_name = "Unknown K2-based"; 2468 pmac_mb.features = g5_features; 2469 break; 2470 case macio_shasta: 2471 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA; 2472 pmac_mb.model_name = "Unknown Shasta-based"; 2473 pmac_mb.features = g5_features; 2474 break; 2475 #endif /* CONFIG_POWER4 */ 2476 default: 2477 return -ENODEV; 2478 } 2479 found: 2480 #ifndef CONFIG_POWER4 2481 /* Fixup Hooper vs. Comet */ 2482 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) { 2483 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4); 2484 if (!mach_id_ptr) 2485 return -ENODEV; 2486 /* Here, I used to disable the media-bay on comet. It 2487 * appears this is wrong, the floppy connector is actually 2488 * a kind of media-bay and works with the current driver. 2489 */ 2490 if (__raw_readl(mach_id_ptr) & 0x20000000UL) 2491 pmac_mb.model_id = PMAC_TYPE_COMET; 2492 iounmap(mach_id_ptr); 2493 } 2494 2495 /* Set default value of powersave_nap on machines that support it. 2496 * It appears that uninorth rev 3 has a problem with it, we don't 2497 * enable it on those. In theory, the flush-on-lock property is 2498 * supposed to be set when not supported, but I'm not very confident 2499 * that all Apple OF revs did it properly, I do it the paranoid way. 2500 */ 2501 while (uninorth_base && uninorth_rev > 3) { 2502 struct device_node *np = find_path_device("/cpus"); 2503 if (!np || !np->child) { 2504 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n"); 2505 break; 2506 } 2507 np = np->child; 2508 /* Nap mode not supported on SMP */ 2509 if (np->sibling) 2510 break; 2511 /* Nap mode not supported if flush-on-lock property is present */ 2512 if (get_property(np, "flush-on-lock", NULL)) 2513 break; 2514 powersave_nap = 1; 2515 printk(KERN_DEBUG "Processor NAP mode on idle enabled.\n"); 2516 break; 2517 } 2518 2519 /* On CPUs that support it (750FX), lowspeed by default during 2520 * NAP mode 2521 */ 2522 powersave_lowspeed = 1; 2523 2524 #else /* CONFIG_POWER4 */ 2525 powersave_nap = 1; 2526 #endif /* CONFIG_POWER4 */ 2527 2528 /* Check for "mobile" machine */ 2529 if (model && (strncmp(model, "PowerBook", 9) == 0 2530 || strncmp(model, "iBook", 5) == 0)) 2531 pmac_mb.board_flags |= PMAC_MB_MOBILE; 2532 2533 2534 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name); 2535 return 0; 2536 } 2537 2538 /* Initialize the Core99 UniNorth host bridge and memory controller 2539 */ 2540 static void __init probe_uninorth(void) 2541 { 2542 const u32 *addrp; 2543 phys_addr_t address; 2544 unsigned long actrl; 2545 2546 /* Locate core99 Uni-N */ 2547 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 2548 /* Locate G5 u3 */ 2549 if (uninorth_node == NULL) { 2550 uninorth_node = of_find_node_by_name(NULL, "u3"); 2551 uninorth_maj = 3; 2552 } 2553 /* Locate G5 u4 */ 2554 if (uninorth_node == NULL) { 2555 uninorth_node = of_find_node_by_name(NULL, "u4"); 2556 uninorth_maj = 4; 2557 } 2558 if (uninorth_node == NULL) 2559 return; 2560 2561 addrp = get_property(uninorth_node, "reg", NULL); 2562 if (addrp == NULL) 2563 return; 2564 address = of_translate_address(uninorth_node, addrp); 2565 if (address == 0) 2566 return; 2567 uninorth_base = ioremap(address, 0x40000); 2568 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION)); 2569 if (uninorth_maj == 3 || uninorth_maj == 4) 2570 u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000); 2571 2572 printk(KERN_INFO "Found %s memory controller & host bridge" 2573 " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" : 2574 uninorth_maj == 4 ? "U4" : "UniNorth", 2575 (unsigned int)address, uninorth_rev); 2576 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base); 2577 2578 /* Set the arbitrer QAck delay according to what Apple does 2579 */ 2580 if (uninorth_rev < 0x11) { 2581 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK; 2582 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 : 2583 UNI_N_ARB_CTRL_QACK_DELAY) << 2584 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT; 2585 UN_OUT(UNI_N_ARB_CTRL, actrl); 2586 } 2587 2588 /* Some more magic as done by them in recent MacOS X on UniNorth 2589 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI 2590 * memory timeout 2591 */ 2592 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || 2593 uninorth_rev == 0xc0) 2594 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff); 2595 } 2596 2597 static void __init probe_one_macio(const char *name, const char *compat, int type) 2598 { 2599 struct device_node* node; 2600 int i; 2601 volatile u32 __iomem *base; 2602 const u32 *addrp, *revp; 2603 phys_addr_t addr; 2604 u64 size; 2605 2606 for (node = NULL; (node = of_find_node_by_name(node, name)) != NULL;) { 2607 if (!compat) 2608 break; 2609 if (device_is_compatible(node, compat)) 2610 break; 2611 } 2612 if (!node) 2613 return; 2614 for(i=0; i<MAX_MACIO_CHIPS; i++) { 2615 if (!macio_chips[i].of_node) 2616 break; 2617 if (macio_chips[i].of_node == node) 2618 return; 2619 } 2620 2621 if (i >= MAX_MACIO_CHIPS) { 2622 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n"); 2623 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name); 2624 return; 2625 } 2626 addrp = of_get_pci_address(node, 0, &size, NULL); 2627 if (addrp == NULL) { 2628 printk(KERN_ERR "pmac_feature: %s: can't find base !\n", 2629 node->full_name); 2630 return; 2631 } 2632 addr = of_translate_address(node, addrp); 2633 if (addr == 0) { 2634 printk(KERN_ERR "pmac_feature: %s, can't translate base !\n", 2635 node->full_name); 2636 return; 2637 } 2638 base = ioremap(addr, (unsigned long)size); 2639 if (!base) { 2640 printk(KERN_ERR "pmac_feature: %s, can't map mac-io chip !\n", 2641 node->full_name); 2642 return; 2643 } 2644 if (type == macio_keylargo || type == macio_keylargo2) { 2645 const u32 *did = get_property(node, "device-id", NULL); 2646 if (*did == 0x00000025) 2647 type = macio_pangea; 2648 if (*did == 0x0000003e) 2649 type = macio_intrepid; 2650 if (*did == 0x0000004f) 2651 type = macio_shasta; 2652 } 2653 macio_chips[i].of_node = node; 2654 macio_chips[i].type = type; 2655 macio_chips[i].base = base; 2656 macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON; 2657 macio_chips[i].name = macio_names[type]; 2658 revp = get_property(node, "revision-id", NULL); 2659 if (revp) 2660 macio_chips[i].rev = *revp; 2661 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n", 2662 macio_names[type], macio_chips[i].rev, macio_chips[i].base); 2663 } 2664 2665 static int __init 2666 probe_macios(void) 2667 { 2668 /* Warning, ordering is important */ 2669 probe_one_macio("gc", NULL, macio_grand_central); 2670 probe_one_macio("ohare", NULL, macio_ohare); 2671 probe_one_macio("pci106b,7", NULL, macio_ohareII); 2672 probe_one_macio("mac-io", "keylargo", macio_keylargo); 2673 probe_one_macio("mac-io", "paddington", macio_paddington); 2674 probe_one_macio("mac-io", "gatwick", macio_gatwick); 2675 probe_one_macio("mac-io", "heathrow", macio_heathrow); 2676 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2); 2677 2678 /* Make sure the "main" macio chip appear first */ 2679 if (macio_chips[0].type == macio_gatwick 2680 && macio_chips[1].type == macio_heathrow) { 2681 struct macio_chip temp = macio_chips[0]; 2682 macio_chips[0] = macio_chips[1]; 2683 macio_chips[1] = temp; 2684 } 2685 if (macio_chips[0].type == macio_ohareII 2686 && macio_chips[1].type == macio_ohare) { 2687 struct macio_chip temp = macio_chips[0]; 2688 macio_chips[0] = macio_chips[1]; 2689 macio_chips[1] = temp; 2690 } 2691 macio_chips[0].lbus.index = 0; 2692 macio_chips[1].lbus.index = 1; 2693 2694 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0; 2695 } 2696 2697 static void __init 2698 initial_serial_shutdown(struct device_node *np) 2699 { 2700 int len; 2701 const struct slot_names_prop { 2702 int count; 2703 char name[1]; 2704 } *slots; 2705 const char *conn; 2706 int port_type = PMAC_SCC_ASYNC; 2707 int modem = 0; 2708 2709 slots = get_property(np, "slot-names", &len); 2710 conn = get_property(np, "AAPL,connector", &len); 2711 if (conn && (strcmp(conn, "infrared") == 0)) 2712 port_type = PMAC_SCC_IRDA; 2713 else if (device_is_compatible(np, "cobalt")) 2714 modem = 1; 2715 else if (slots && slots->count > 0) { 2716 if (strcmp(slots->name, "IrDA") == 0) 2717 port_type = PMAC_SCC_IRDA; 2718 else if (strcmp(slots->name, "Modem") == 0) 2719 modem = 1; 2720 } 2721 if (modem) 2722 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0); 2723 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0); 2724 } 2725 2726 static void __init 2727 set_initial_features(void) 2728 { 2729 struct device_node *np; 2730 2731 /* That hack appears to be necessary for some StarMax motherboards 2732 * but I'm not too sure it was audited for side-effects on other 2733 * ohare based machines... 2734 * Since I still have difficulties figuring the right way to 2735 * differenciate them all and since that hack was there for a long 2736 * time, I'll keep it around 2737 */ 2738 if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) { 2739 struct macio_chip *macio = &macio_chips[0]; 2740 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES); 2741 } else if (macio_chips[0].type == macio_ohare) { 2742 struct macio_chip *macio = &macio_chips[0]; 2743 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 2744 } else if (macio_chips[1].type == macio_ohare) { 2745 struct macio_chip *macio = &macio_chips[1]; 2746 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 2747 } 2748 2749 #ifdef CONFIG_POWER4 2750 if (macio_chips[0].type == macio_keylargo2 || 2751 macio_chips[0].type == macio_shasta) { 2752 #ifndef CONFIG_SMP 2753 /* On SMP machines running UP, we have the second CPU eating 2754 * bus cycles. We need to take it off the bus. This is done 2755 * from pmac_smp for SMP kernels running on one CPU 2756 */ 2757 np = of_find_node_by_type(NULL, "cpu"); 2758 if (np != NULL) 2759 np = of_find_node_by_type(np, "cpu"); 2760 if (np != NULL) { 2761 g5_phy_disable_cpu1(); 2762 of_node_put(np); 2763 } 2764 #endif /* CONFIG_SMP */ 2765 /* Enable GMAC for now for PCI probing. It will be disabled 2766 * later on after PCI probe 2767 */ 2768 np = of_find_node_by_name(NULL, "ethernet"); 2769 while(np) { 2770 if (device_is_compatible(np, "K2-GMAC")) 2771 g5_gmac_enable(np, 0, 1); 2772 np = of_find_node_by_name(np, "ethernet"); 2773 } 2774 2775 /* Enable FW before PCI probe. Will be disabled later on 2776 * Note: We should have a batter way to check that we are 2777 * dealing with uninorth internal cell and not a PCI cell 2778 * on the external PCI. The code below works though. 2779 */ 2780 np = of_find_node_by_name(NULL, "firewire"); 2781 while(np) { 2782 if (device_is_compatible(np, "pci106b,5811")) { 2783 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; 2784 g5_fw_enable(np, 0, 1); 2785 } 2786 np = of_find_node_by_name(np, "firewire"); 2787 } 2788 } 2789 #else /* CONFIG_POWER4 */ 2790 2791 if (macio_chips[0].type == macio_keylargo || 2792 macio_chips[0].type == macio_pangea || 2793 macio_chips[0].type == macio_intrepid) { 2794 /* Enable GMAC for now for PCI probing. It will be disabled 2795 * later on after PCI probe 2796 */ 2797 np = of_find_node_by_name(NULL, "ethernet"); 2798 while(np) { 2799 if (np->parent 2800 && device_is_compatible(np->parent, "uni-north") 2801 && device_is_compatible(np, "gmac")) 2802 core99_gmac_enable(np, 0, 1); 2803 np = of_find_node_by_name(np, "ethernet"); 2804 } 2805 2806 /* Enable FW before PCI probe. Will be disabled later on 2807 * Note: We should have a batter way to check that we are 2808 * dealing with uninorth internal cell and not a PCI cell 2809 * on the external PCI. The code below works though. 2810 */ 2811 np = of_find_node_by_name(NULL, "firewire"); 2812 while(np) { 2813 if (np->parent 2814 && device_is_compatible(np->parent, "uni-north") 2815 && (device_is_compatible(np, "pci106b,18") || 2816 device_is_compatible(np, "pci106b,30") || 2817 device_is_compatible(np, "pci11c1,5811"))) { 2818 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; 2819 core99_firewire_enable(np, 0, 1); 2820 } 2821 np = of_find_node_by_name(np, "firewire"); 2822 } 2823 2824 /* Enable ATA-100 before PCI probe. */ 2825 np = of_find_node_by_name(NULL, "ata-6"); 2826 while(np) { 2827 if (np->parent 2828 && device_is_compatible(np->parent, "uni-north") 2829 && device_is_compatible(np, "kauai-ata")) { 2830 core99_ata100_enable(np, 1); 2831 } 2832 np = of_find_node_by_name(np, "ata-6"); 2833 } 2834 2835 /* Switch airport off */ 2836 np = find_devices("radio"); 2837 while(np) { 2838 if (np && np->parent == macio_chips[0].of_node) { 2839 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON; 2840 core99_airport_enable(np, 0, 0); 2841 } 2842 np = np->next; 2843 } 2844 } 2845 2846 /* On all machines that support sound PM, switch sound off */ 2847 if (macio_chips[0].of_node) 2848 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE, 2849 macio_chips[0].of_node, 0, 0); 2850 2851 /* While on some desktop G3s, we turn it back on */ 2852 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow 2853 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER || 2854 pmac_mb.model_id == PMAC_TYPE_SILK)) { 2855 struct macio_chip *macio = &macio_chips[0]; 2856 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 2857 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 2858 } 2859 2860 #endif /* CONFIG_POWER4 */ 2861 2862 /* On all machines, switch modem & serial ports off */ 2863 np = find_devices("ch-a"); 2864 while(np) { 2865 initial_serial_shutdown(np); 2866 np = np->next; 2867 } 2868 np = find_devices("ch-b"); 2869 while(np) { 2870 initial_serial_shutdown(np); 2871 np = np->next; 2872 } 2873 } 2874 2875 void __init 2876 pmac_feature_init(void) 2877 { 2878 /* Detect the UniNorth memory controller */ 2879 probe_uninorth(); 2880 2881 /* Probe mac-io controllers */ 2882 if (probe_macios()) { 2883 printk(KERN_WARNING "No mac-io chip found\n"); 2884 return; 2885 } 2886 2887 /* Probe machine type */ 2888 if (probe_motherboard()) 2889 printk(KERN_WARNING "Unknown PowerMac !\n"); 2890 2891 /* Set some initial features (turn off some chips that will 2892 * be later turned on) 2893 */ 2894 set_initial_features(); 2895 } 2896 2897 #if 0 2898 static void dump_HT_speeds(char *name, u32 cfg, u32 frq) 2899 { 2900 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 }; 2901 int bits[8] = { 8,16,0,32,2,4,0,0 }; 2902 int freq = (frq >> 8) & 0xf; 2903 2904 if (freqs[freq] == 0) 2905 printk("%s: Unknown HT link frequency %x\n", name, freq); 2906 else 2907 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n", 2908 name, freqs[freq], 2909 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]); 2910 } 2911 2912 void __init pmac_check_ht_link(void) 2913 { 2914 u32 ufreq, freq, ucfg, cfg; 2915 struct device_node *pcix_node; 2916 u8 px_bus, px_devfn; 2917 struct pci_controller *px_hose; 2918 2919 (void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND); 2920 ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG); 2921 ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ); 2922 dump_HT_speeds("U3 HyperTransport", cfg, freq); 2923 2924 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x"); 2925 if (pcix_node == NULL) { 2926 printk("No PCI-X bridge found\n"); 2927 return; 2928 } 2929 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) { 2930 printk("PCI-X bridge found but not matched to pci\n"); 2931 return; 2932 } 2933 px_hose = pci_find_hose_for_OF_device(pcix_node); 2934 if (px_hose == NULL) { 2935 printk("PCI-X bridge found but not matched to host\n"); 2936 return; 2937 } 2938 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg); 2939 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq); 2940 dump_HT_speeds("PCI-X HT Uplink", cfg, freq); 2941 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg); 2942 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq); 2943 dump_HT_speeds("PCI-X HT Downlink", cfg, freq); 2944 } 2945 #endif /* 0 */ 2946 2947 /* 2948 * Early video resume hook 2949 */ 2950 2951 static void (*pmac_early_vresume_proc)(void *data); 2952 static void *pmac_early_vresume_data; 2953 2954 void pmac_set_early_video_resume(void (*proc)(void *data), void *data) 2955 { 2956 if (!machine_is(powermac)) 2957 return; 2958 preempt_disable(); 2959 pmac_early_vresume_proc = proc; 2960 pmac_early_vresume_data = data; 2961 preempt_enable(); 2962 } 2963 EXPORT_SYMBOL(pmac_set_early_video_resume); 2964 2965 void pmac_call_early_video_resume(void) 2966 { 2967 if (pmac_early_vresume_proc) 2968 pmac_early_vresume_proc(pmac_early_vresume_data); 2969 } 2970 2971 /* 2972 * AGP related suspend/resume code 2973 */ 2974 2975 static struct pci_dev *pmac_agp_bridge; 2976 static int (*pmac_agp_suspend)(struct pci_dev *bridge); 2977 static int (*pmac_agp_resume)(struct pci_dev *bridge); 2978 2979 void pmac_register_agp_pm(struct pci_dev *bridge, 2980 int (*suspend)(struct pci_dev *bridge), 2981 int (*resume)(struct pci_dev *bridge)) 2982 { 2983 if (suspend || resume) { 2984 pmac_agp_bridge = bridge; 2985 pmac_agp_suspend = suspend; 2986 pmac_agp_resume = resume; 2987 return; 2988 } 2989 if (bridge != pmac_agp_bridge) 2990 return; 2991 pmac_agp_suspend = pmac_agp_resume = NULL; 2992 return; 2993 } 2994 EXPORT_SYMBOL(pmac_register_agp_pm); 2995 2996 void pmac_suspend_agp_for_card(struct pci_dev *dev) 2997 { 2998 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL) 2999 return; 3000 if (pmac_agp_bridge->bus != dev->bus) 3001 return; 3002 pmac_agp_suspend(pmac_agp_bridge); 3003 } 3004 EXPORT_SYMBOL(pmac_suspend_agp_for_card); 3005 3006 void pmac_resume_agp_for_card(struct pci_dev *dev) 3007 { 3008 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL) 3009 return; 3010 if (pmac_agp_bridge->bus != dev->bus) 3011 return; 3012 pmac_agp_resume(pmac_agp_bridge); 3013 } 3014 EXPORT_SYMBOL(pmac_resume_agp_for_card); 3015