1 /* 2 * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem 3 * ctlr/EPIC/etc. 4 * 5 * Author: Mark A. Greer 6 * mgreer@mvista.com 7 * 8 * 2001 (c) MontaVista, Software, Inc. This file is licensed under 9 * the terms of the GNU General Public License version 2. This program 10 * is licensed "as is" without any warranty of any kind, whether express 11 * or implied. 12 */ 13 #ifndef __PPC_KERNEL_MPC10X_H 14 #define __PPC_KERNEL_MPC10X_H 15 16 #include <linux/pci_ids.h> 17 #include <asm/pci-bridge.h> 18 19 /* 20 * The values here don't completely map everything but should work in most 21 * cases. 22 * 23 * MAP A (PReP Map) 24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff 25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff 26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 27 * 28 * MAP B (CHRP Map) 29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff 30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff 31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 32 */ 33 34 /* 35 * Define the vendor/device IDs for the various bridges--should be added to 36 * <linux/pci_ids.h> 37 */ 38 #define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ 39 PCI_VENDOR_ID_MOTOROLA) 40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) 41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) 42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) 43 44 /* Define the type of map to use */ 45 #define MPC10X_MEM_MAP_A 1 46 #define MPC10X_MEM_MAP_B 2 47 48 /* Map A (PReP Map) Defines */ 49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 50 #define MPC10X_MAPA_CNFG_DATA 0x80000cfc 51 52 #define MPC10X_MAPA_ISA_IO_BASE 0x80000000 53 #define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 54 #define MPC10X_MAPA_DRAM_OFFSET 0x80000000 55 56 #define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0 57 #define MPC10X_MAPA_PCI_IO_START 0x00000000 58 #define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) 59 #define MPC10X_MAPA_PCI_MEM_START 0x00000000 60 #define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) 61 62 #define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ 63 MPC10X_MAPA_PCI_MEM_START) 64 65 /* Map B (CHRP Map) Defines */ 66 #define MPC10X_MAPB_CNFG_ADDR 0xfec00000 67 #define MPC10X_MAPB_CNFG_DATA 0xfee00000 68 69 #define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 70 #define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 71 #define MPC10X_MAPB_DRAM_OFFSET 0x00000000 72 73 #define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000 74 #define MPC10X_MAPB_PCI_IO_START 0x00000000 75 #define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) 76 #define MPC10X_MAPB_PCI_MEM_START 0x80000000 77 #define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) 78 79 #define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ 80 MPC10X_MAPB_PCI_MEM_START) 81 82 /* Miscellaneous Configuration register offsets */ 83 #define MPC10X_CFG_PIR_REG 0x09 84 #define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 85 #define MPC10X_CFG_PIR_AGENT 0x01 86 87 #define MPC10X_CFG_EUMBBAR 0x78 88 89 #define MPC10X_CFG_PICR1_REG 0xa8 90 #define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 91 #define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 92 #define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 93 #define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 94 #define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 95 96 #define MPC10X_CFG_PICR2_REG 0xac 97 #define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 98 99 #define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 100 #define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ 101 #define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ 102 #define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ 103 #define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ 104 #define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ 105 106 /* Define offsets for the memory controller registers in the config space */ 107 #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ 108 #define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ 109 #define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ 110 #define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ 111 112 #define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ 113 #define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ 114 #define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ 115 #define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ 116 117 #define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 118 119 /* Define some offset in the EUMB */ 120 #define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ 121 122 #define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ 123 #define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ 124 #define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ 125 #define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ 126 #define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ 127 #define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ 128 #define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ 129 #define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ 130 #define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ 131 #define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ 132 #define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ 133 #define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ 134 #define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ 135 #define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ 136 #define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ 137 #define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ 138 139 enum ppc_sys_devices { 140 MPC10X_IIC1, 141 MPC10X_DMA0, 142 MPC10X_DMA1, 143 MPC10X_UART0, 144 MPC10X_UART1, 145 NUM_PPC_SYS_DEVS, 146 }; 147 148 int mpc10x_bridge_init(struct pci_controller *hose, 149 uint current_map, 150 uint new_map, 151 uint phys_eumb_base); 152 unsigned long mpc10x_get_mem_size(uint mem_map); 153 int mpc10x_enable_store_gathering(struct pci_controller *hose); 154 int mpc10x_disable_store_gathering(struct pci_controller *hose); 155 156 /* For MPC107 boards that use the built-in openpic */ 157 void mpc10x_set_openpic(void); 158 159 #endif /* __PPC_KERNEL_MPC10X_H */ 160