1 /* 2 * Copyright (C) 1995 Linus Torvalds 3 * Adapted from 'alpha' version by Gary Thomas 4 * Modified by Cort Dougan (cort@cs.nmt.edu) 5 */ 6 7 /* 8 * bootup setup stuff.. 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/sched.h> 13 #include <linux/kernel.h> 14 #include <linux/mm.h> 15 #include <linux/stddef.h> 16 #include <linux/unistd.h> 17 #include <linux/ptrace.h> 18 #include <linux/slab.h> 19 #include <linux/user.h> 20 #include <linux/a.out.h> 21 #include <linux/tty.h> 22 #include <linux/major.h> 23 #include <linux/interrupt.h> 24 #include <linux/reboot.h> 25 #include <linux/init.h> 26 #include <linux/pci.h> 27 #include <linux/utsrelease.h> 28 #include <linux/adb.h> 29 #include <linux/module.h> 30 #include <linux/delay.h> 31 #include <linux/ide.h> 32 #include <linux/console.h> 33 #include <linux/seq_file.h> 34 #include <linux/root_dev.h> 35 #include <linux/initrd.h> 36 #include <linux/module.h> 37 #include <linux/timer.h> 38 39 #include <asm/io.h> 40 #include <asm/pgtable.h> 41 #include <asm/prom.h> 42 #include <asm/gg2.h> 43 #include <asm/pci-bridge.h> 44 #include <asm/dma.h> 45 #include <asm/machdep.h> 46 #include <asm/irq.h> 47 #include <asm/hydra.h> 48 #include <asm/sections.h> 49 #include <asm/time.h> 50 #include <asm/i8259.h> 51 #include <asm/mpic.h> 52 #include <asm/rtas.h> 53 #include <asm/xmon.h> 54 55 #include "chrp.h" 56 57 void rtas_indicator_progress(char *, unsigned short); 58 59 int _chrp_type; 60 EXPORT_SYMBOL(_chrp_type); 61 62 static struct mpic *chrp_mpic; 63 64 /* Used for doing CHRP event-scans */ 65 DEFINE_PER_CPU(struct timer_list, heartbeat_timer); 66 unsigned long event_scan_interval; 67 68 /* 69 * XXX this should be in xmon.h, but putting it there means xmon.h 70 * has to include <linux/interrupt.h> (to get irqreturn_t), which 71 * causes all sorts of problems. -- paulus 72 */ 73 extern irqreturn_t xmon_irq(int, void *); 74 75 extern unsigned long loops_per_jiffy; 76 77 /* To be replaced by RTAS when available */ 78 static unsigned int __iomem *briq_SPOR; 79 80 #ifdef CONFIG_SMP 81 extern struct smp_ops_t chrp_smp_ops; 82 #endif 83 84 static const char *gg2_memtypes[4] = { 85 "FPM", "SDRAM", "EDO", "BEDO" 86 }; 87 static const char *gg2_cachesizes[4] = { 88 "256 KB", "512 KB", "1 MB", "Reserved" 89 }; 90 static const char *gg2_cachetypes[4] = { 91 "Asynchronous", "Reserved", "Flow-Through Synchronous", 92 "Pipelined Synchronous" 93 }; 94 static const char *gg2_cachemodes[4] = { 95 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" 96 }; 97 98 static const char *chrp_names[] = { 99 "Unknown", 100 "","","", 101 "Motorola", 102 "IBM or Longtrail", 103 "Genesi Pegasos", 104 "Total Impact Briq" 105 }; 106 107 void chrp_show_cpuinfo(struct seq_file *m) 108 { 109 int i, sdramen; 110 unsigned int t; 111 struct device_node *root; 112 const char *model = ""; 113 114 root = find_path_device("/"); 115 if (root) 116 model = get_property(root, "model", NULL); 117 seq_printf(m, "machine\t\t: CHRP %s\n", model); 118 119 /* longtrail (goldengate) stuff */ 120 if (!strncmp(model, "IBM,LongTrail", 13)) { 121 /* VLSI VAS96011/12 `Golden Gate 2' */ 122 /* Memory banks */ 123 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) 124 >>31) & 1; 125 for (i = 0; i < (sdramen ? 4 : 6); i++) { 126 t = in_le32(gg2_pci_config_base+ 127 GG2_PCI_DRAM_BANK0+ 128 i*4); 129 if (!(t & 1)) 130 continue; 131 switch ((t>>8) & 0x1f) { 132 case 0x1f: 133 model = "4 MB"; 134 break; 135 case 0x1e: 136 model = "8 MB"; 137 break; 138 case 0x1c: 139 model = "16 MB"; 140 break; 141 case 0x18: 142 model = "32 MB"; 143 break; 144 case 0x10: 145 model = "64 MB"; 146 break; 147 case 0x00: 148 model = "128 MB"; 149 break; 150 default: 151 model = "Reserved"; 152 break; 153 } 154 seq_printf(m, "memory bank %d\t: %s %s\n", i, model, 155 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); 156 } 157 /* L2 cache */ 158 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); 159 seq_printf(m, "board l2\t: %s %s (%s)\n", 160 gg2_cachesizes[(t>>7) & 3], 161 gg2_cachetypes[(t>>2) & 3], 162 gg2_cachemodes[t & 3]); 163 } 164 } 165 166 /* 167 * Fixes for the National Semiconductor PC78308VUL SuperI/O 168 * 169 * Some versions of Open Firmware incorrectly initialize the IRQ settings 170 * for keyboard and mouse 171 */ 172 static inline void __init sio_write(u8 val, u8 index) 173 { 174 outb(index, 0x15c); 175 outb(val, 0x15d); 176 } 177 178 static inline u8 __init sio_read(u8 index) 179 { 180 outb(index, 0x15c); 181 return inb(0x15d); 182 } 183 184 static void __init sio_fixup_irq(const char *name, u8 device, u8 level, 185 u8 type) 186 { 187 u8 level0, type0, active; 188 189 /* select logical device */ 190 sio_write(device, 0x07); 191 active = sio_read(0x30); 192 level0 = sio_read(0x70); 193 type0 = sio_read(0x71); 194 if (level0 != level || type0 != type || !active) { 195 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " 196 "remapping to level %d, type %d, active\n", 197 name, level0, type0, !active ? "in" : "", level, type); 198 sio_write(0x01, 0x30); 199 sio_write(level, 0x70); 200 sio_write(type, 0x71); 201 } 202 } 203 204 static void __init sio_init(void) 205 { 206 struct device_node *root; 207 208 if ((root = find_path_device("/")) && 209 !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) { 210 /* logical device 0 (KBC/Keyboard) */ 211 sio_fixup_irq("keyboard", 0, 1, 2); 212 /* select logical device 1 (KBC/Mouse) */ 213 sio_fixup_irq("mouse", 1, 12, 2); 214 } 215 } 216 217 218 static void __init pegasos_set_l2cr(void) 219 { 220 struct device_node *np; 221 222 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ 223 if (_chrp_type != _CHRP_Pegasos) 224 return; 225 226 /* Enable L2 cache if needed */ 227 np = find_type_devices("cpu"); 228 if (np != NULL) { 229 const unsigned int *l2cr = get_property(np, "l2cr", NULL); 230 if (l2cr == NULL) { 231 printk ("Pegasos l2cr : no cpu l2cr property found\n"); 232 return; 233 } 234 if (!((*l2cr) & 0x80000000)) { 235 printk ("Pegasos l2cr : L2 cache was not active, " 236 "activating\n"); 237 _set_L2CR(0); 238 _set_L2CR((*l2cr) | 0x80000000); 239 } 240 } 241 } 242 243 static void briq_restart(char *cmd) 244 { 245 local_irq_disable(); 246 if (briq_SPOR) 247 out_be32(briq_SPOR, 0); 248 for(;;); 249 } 250 251 void __init chrp_setup_arch(void) 252 { 253 struct device_node *root = find_path_device ("/"); 254 const char *machine = NULL; 255 256 /* init to some ~sane value until calibrate_delay() runs */ 257 loops_per_jiffy = 50000000/HZ; 258 259 if (root) 260 machine = get_property(root, "model", NULL); 261 if (machine && strncmp(machine, "Pegasos", 7) == 0) { 262 _chrp_type = _CHRP_Pegasos; 263 } else if (machine && strncmp(machine, "IBM", 3) == 0) { 264 _chrp_type = _CHRP_IBM; 265 } else if (machine && strncmp(machine, "MOT", 3) == 0) { 266 _chrp_type = _CHRP_Motorola; 267 } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) { 268 _chrp_type = _CHRP_briq; 269 /* Map the SPOR register on briq and change the restart hook */ 270 briq_SPOR = ioremap(0xff0000e8, 4); 271 ppc_md.restart = briq_restart; 272 } else { 273 /* Let's assume it is an IBM chrp if all else fails */ 274 _chrp_type = _CHRP_IBM; 275 } 276 printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]); 277 278 rtas_initialize(); 279 if (rtas_token("display-character") >= 0) 280 ppc_md.progress = rtas_progress; 281 282 /* use RTAS time-of-day routines if available */ 283 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) { 284 ppc_md.get_boot_time = rtas_get_boot_time; 285 ppc_md.get_rtc_time = rtas_get_rtc_time; 286 ppc_md.set_rtc_time = rtas_set_rtc_time; 287 } 288 289 #ifdef CONFIG_BLK_DEV_INITRD 290 /* this is fine for chrp */ 291 initrd_below_start_ok = 1; 292 293 if (initrd_start) 294 ROOT_DEV = Root_RAM0; 295 else 296 #endif 297 ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */ 298 299 /* On pegasos, enable the L2 cache if not already done by OF */ 300 pegasos_set_l2cr(); 301 302 /* Lookup PCI host bridges */ 303 chrp_find_bridges(); 304 305 /* 306 * Temporary fixes for PCI devices. 307 * -- Geert 308 */ 309 hydra_init(); /* Mac I/O */ 310 311 /* 312 * Fix the Super I/O configuration 313 */ 314 sio_init(); 315 316 pci_create_OF_bus_map(); 317 318 /* 319 * Print the banner, then scroll down so boot progress 320 * can be printed. -- Cort 321 */ 322 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); 323 } 324 325 void 326 chrp_event_scan(unsigned long unused) 327 { 328 unsigned char log[1024]; 329 int ret = 0; 330 331 /* XXX: we should loop until the hardware says no more error logs -- Cort */ 332 rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, 333 __pa(log), 1024); 334 mod_timer(&__get_cpu_var(heartbeat_timer), 335 jiffies + event_scan_interval); 336 } 337 338 static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) 339 { 340 unsigned int cascade_irq = i8259_irq(); 341 if (cascade_irq != NO_IRQ) 342 generic_handle_irq(cascade_irq); 343 desc->chip->eoi(irq); 344 } 345 346 /* 347 * Finds the open-pic node and sets up the mpic driver. 348 */ 349 static void __init chrp_find_openpic(void) 350 { 351 struct device_node *np, *root; 352 int len, i, j; 353 int isu_size, idu_size; 354 const unsigned int *iranges, *opprop = NULL; 355 int oplen = 0; 356 unsigned long opaddr; 357 int na = 1; 358 359 np = of_find_node_by_type(NULL, "open-pic"); 360 if (np == NULL) 361 return; 362 root = of_find_node_by_path("/"); 363 if (root) { 364 opprop = get_property(root, "platform-open-pic", &oplen); 365 na = prom_n_addr_cells(root); 366 } 367 if (opprop && oplen >= na * sizeof(unsigned int)) { 368 opaddr = opprop[na-1]; /* assume 32-bit */ 369 oplen /= na * sizeof(unsigned int); 370 } else { 371 struct resource r; 372 if (of_address_to_resource(np, 0, &r)) { 373 goto bail; 374 } 375 opaddr = r.start; 376 oplen = 0; 377 } 378 379 printk(KERN_INFO "OpenPIC at %lx\n", opaddr); 380 381 iranges = get_property(np, "interrupt-ranges", &len); 382 if (iranges == NULL) 383 len = 0; /* non-distributed mpic */ 384 else 385 len /= 2 * sizeof(unsigned int); 386 387 /* 388 * The first pair of cells in interrupt-ranges refers to the 389 * IDU; subsequent pairs refer to the ISUs. 390 */ 391 if (oplen < len) { 392 printk(KERN_ERR "Insufficient addresses for distributed" 393 " OpenPIC (%d < %d)\n", oplen, len); 394 len = oplen; 395 } 396 397 isu_size = 0; 398 idu_size = 0; 399 if (len > 0 && iranges[1] != 0) { 400 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", 401 iranges[0], iranges[0] + iranges[1] - 1); 402 idu_size = iranges[1]; 403 } 404 if (len > 1) 405 isu_size = iranges[3]; 406 407 chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY, 408 isu_size, 0, " MPIC "); 409 if (chrp_mpic == NULL) { 410 printk(KERN_ERR "Failed to allocate MPIC structure\n"); 411 goto bail; 412 } 413 j = na - 1; 414 for (i = 1; i < len; ++i) { 415 iranges += 2; 416 j += na; 417 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n", 418 iranges[0], iranges[0] + iranges[1] - 1, 419 opprop[j]); 420 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]); 421 } 422 423 mpic_init(chrp_mpic); 424 ppc_md.get_irq = mpic_get_irq; 425 bail: 426 of_node_put(root); 427 of_node_put(np); 428 } 429 430 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) 431 static struct irqaction xmon_irqaction = { 432 .handler = xmon_irq, 433 .mask = CPU_MASK_NONE, 434 .name = "XMON break", 435 }; 436 #endif 437 438 static void __init chrp_find_8259(void) 439 { 440 struct device_node *np, *pic = NULL; 441 unsigned long chrp_int_ack = 0; 442 unsigned int cascade_irq; 443 444 /* Look for cascade */ 445 for_each_node_by_type(np, "interrupt-controller") 446 if (device_is_compatible(np, "chrp,iic")) { 447 pic = np; 448 break; 449 } 450 /* Ok, 8259 wasn't found. We need to handle the case where 451 * we have a pegasos that claims to be chrp but doesn't have 452 * a proper interrupt tree 453 */ 454 if (pic == NULL && chrp_mpic != NULL) { 455 printk(KERN_ERR "i8259: Not found in device-tree" 456 " assuming no legacy interrupts\n"); 457 return; 458 } 459 460 /* Look for intack. In a perfect world, we would look for it on 461 * the ISA bus that holds the 8259 but heh... Works that way. If 462 * we ever see a problem, we can try to re-use the pSeries code here. 463 * Also, Pegasos-type platforms don't have a proper node to start 464 * from anyway 465 */ 466 for (np = find_devices("pci"); np != NULL; np = np->next) { 467 const unsigned int *addrp = get_property(np, 468 "8259-interrupt-acknowledge", NULL); 469 470 if (addrp == NULL) 471 continue; 472 chrp_int_ack = addrp[prom_n_addr_cells(np)-1]; 473 break; 474 } 475 if (np == NULL) 476 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge" 477 " address, polling\n"); 478 479 i8259_init(pic, chrp_int_ack); 480 if (ppc_md.get_irq == NULL) { 481 ppc_md.get_irq = i8259_irq; 482 irq_set_default_host(i8259_get_host()); 483 } 484 if (chrp_mpic != NULL) { 485 cascade_irq = irq_of_parse_and_map(pic, 0); 486 if (cascade_irq == NO_IRQ) 487 printk(KERN_ERR "i8259: failed to map cascade irq\n"); 488 else 489 set_irq_chained_handler(cascade_irq, 490 chrp_8259_cascade); 491 } 492 } 493 494 void __init chrp_init_IRQ(void) 495 { 496 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) 497 struct device_node *kbd; 498 #endif 499 chrp_find_openpic(); 500 chrp_find_8259(); 501 502 #ifdef CONFIG_SMP 503 /* Pegasos has no MPIC, those ops would make it crash. It might be an 504 * option to move setting them to after we probe the PIC though 505 */ 506 if (chrp_mpic != NULL) 507 smp_ops = &chrp_smp_ops; 508 #endif /* CONFIG_SMP */ 509 510 if (_chrp_type == _CHRP_Pegasos) 511 ppc_md.get_irq = i8259_irq; 512 513 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) 514 /* see if there is a keyboard in the device tree 515 with a parent of type "adb" */ 516 for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next) 517 if (kbd->parent && kbd->parent->type 518 && strcmp(kbd->parent->type, "adb") == 0) 519 break; 520 if (kbd) 521 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); 522 #endif 523 } 524 525 void __init 526 chrp_init2(void) 527 { 528 struct device_node *device; 529 const unsigned int *p = NULL; 530 531 #ifdef CONFIG_NVRAM 532 chrp_nvram_init(); 533 #endif 534 535 request_region(0x20,0x20,"pic1"); 536 request_region(0xa0,0x20,"pic2"); 537 request_region(0x00,0x20,"dma1"); 538 request_region(0x40,0x20,"timer"); 539 request_region(0x80,0x10,"dma page reg"); 540 request_region(0xc0,0x20,"dma2"); 541 542 /* Get the event scan rate for the rtas so we know how 543 * often it expects a heartbeat. -- Cort 544 */ 545 device = find_devices("rtas"); 546 if (device) 547 p = get_property(device, "rtas-event-scan-rate", NULL); 548 if (p && *p) { 549 /* 550 * Arrange to call chrp_event_scan at least *p times 551 * per minute. We use 59 rather than 60 here so that 552 * the rate will be slightly higher than the minimum. 553 * This all assumes we don't do hotplug CPU on any 554 * machine that needs the event scans done. 555 */ 556 unsigned long interval, offset; 557 int cpu, ncpus; 558 struct timer_list *timer; 559 560 interval = HZ * 59 / *p; 561 offset = HZ; 562 ncpus = num_online_cpus(); 563 event_scan_interval = ncpus * interval; 564 for (cpu = 0; cpu < ncpus; ++cpu) { 565 timer = &per_cpu(heartbeat_timer, cpu); 566 setup_timer(timer, chrp_event_scan, 0); 567 timer->expires = jiffies + offset; 568 add_timer_on(timer, cpu); 569 offset += interval; 570 } 571 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", 572 *p, interval); 573 } 574 575 if (ppc_md.progress) 576 ppc_md.progress(" Have fun! ", 0x7777); 577 } 578 579 static int __init chrp_probe(void) 580 { 581 char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), 582 "device_type", NULL); 583 if (dtype == NULL) 584 return 0; 585 if (strcmp(dtype, "chrp")) 586 return 0; 587 588 ISA_DMA_THRESHOLD = ~0L; 589 DMA_MODE_READ = 0x44; 590 DMA_MODE_WRITE = 0x48; 591 592 return 1; 593 } 594 595 define_machine(chrp) { 596 .name = "CHRP", 597 .probe = chrp_probe, 598 .setup_arch = chrp_setup_arch, 599 .init = chrp_init2, 600 .show_cpuinfo = chrp_show_cpuinfo, 601 .init_IRQ = chrp_init_IRQ, 602 .restart = rtas_restart, 603 .power_off = rtas_power_off, 604 .halt = rtas_halt, 605 .time_init = chrp_time_init, 606 .set_rtc_time = chrp_set_rtc_time, 607 .get_rtc_time = chrp_get_rtc_time, 608 .calibrate_decr = generic_calibrate_decr, 609 .phys_mem_access_prot = pci_phys_mem_access_prot, 610 }; 611